CN108390673A - A kind of high-speed ADC interleave samples system - Google Patents
A kind of high-speed ADC interleave samples system Download PDFInfo
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- CN108390673A CN108390673A CN201810109473.3A CN201810109473A CN108390673A CN 108390673 A CN108390673 A CN 108390673A CN 201810109473 A CN201810109473 A CN 201810109473A CN 108390673 A CN108390673 A CN 108390673A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0626—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by filtering
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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Abstract
The invention discloses a kind of high-speed ADC interleave samples system, including difference channel and clock circuit, difference channel and clock circuit are connect with the ADC of N channel by differential pair transmission line respectively；Difference channel includes that the first transformer of concatenated in order and the second transformer and signal output module, the input terminal of signal output module are connected to the output end of the second transformer；Clock circuit includes the rear class clock module for distinguishing input difference to clock signal to the ADC of N channel, and the first clock chip for having dephased differential pair signal to the input of rear class clock module；Rear class clock module includes the matched second clock chip of ADC difference of N/2 blocks and N channel, and N/2 block second clock chips are connected respectively to the output end of the first clock chip.The present invention can inhibit unbalance differential signal and lifting system Signal-to-Noise-and-distortion ratio and spurious-free dynamic range, be conducive to the overall performance of raising system.
Description
Technical field
The present invention relates to high-speed data acquisition field, especially a kind of high-speed ADC interleave samples system.
Background technology
It is higher and higher to the sample rate requirement of ADC in wireless communication transmitting-receiving field, comply with adopting for TIADC systems
Sample standard, it is therefore desirable to the front-end circuit of ADC is transformed, mainly power splitter and clock circuit are transformed.At present
Power splitter the single-ended signal of input is generally converted by differential signal using single transformer, but due to its internal distribution electricity
The presence of appearance can cause the unbalance of differential signal, harmonic distortion, amplitude fading, phase imbalance etc. to cause ADC channel；
Clock circuit in the art at present generally generates output to the differential clock signal of ADC using external level, and external level is not
Stablize so that phase error is larger, and system Signal-to-Noise-and-distortion ratio (SINAD), spurious-free dynamic range (SFDR) is further made significantly to drop
It is low；These problems are unfavorable for the overall performance of raising system.
Invention content
To solve the above-mentioned problems, the object of the present invention is to provide a kind of high-speed ADC interleave samples system, it can inhibit difference
Signal imbalance and lifting system Signal-to-Noise-and-distortion ratio and spurious-free dynamic range, are conducive to the overall performance of raising system.
In order to make up for the deficiencies of the prior art, the technical solution adopted by the present invention is：
A kind of high-speed ADC interleave samples system, including difference channel and clock circuit, difference channel and clock circuit difference
It is connect by differential pair transmission line with the ADC of N channel；Difference channel includes the first transformer and the second transformation of concatenated in order
Device, and for distinguishing input difference to the signal output module of signal, the input terminal of signal output module to the ADC of N channel
It is connected to the output end of the second transformer；Clock circuit includes for distinguishing input difference to clock signal to the ADC of N channel
Rear class clock module, and the first clock chip for having dephased differential pair signal to the input of rear class clock module；
Rear class clock module includes the matched second clock chip of ADC difference of N/2 blocks and N channel, N/2 block second clock chips difference
It is connected to the output end of the first clock chip.
Further, difference channel further include for the first transformer input single-ended signal the first input module, first
Input module is connected to the input terminal of the first transformer.
Further, difference channel further includes for the matched matching module of output as the second transformer, matching module
It is connected to the output end of the second transformer.
Further, difference channel further includes the filtering mould that the differential pair signal for being exported to the second transformer is filtered
Block, filter module are arranged between the output end and signal output module of the second transformer.
Further, signal output module includes N number of difference block to match with N channel ADC, N number of difference block difference
It is connected to the output end of the second transformer.
Further, difference block includes the first resistor and second resistance for promoting channel isolation, further includes being used for
Convert differential pair signal to from current source type the 3rd resistor of voltage-type；First resistor and second resistance are separately positioned on two
On signal wire, 3rd resistor terminates between two signal lines.
Further, the invention also includes for the first clock chip input initial signal the second input module, second
Input module and the first clock chip are terminated at together.
Further, the internal resistance parallel end connection of the input terminal of second clock chip and the chip.
The beneficial effects of the invention are as follows：Power splitter is formed using two transformers of concatenated in order, for ADC channel, energy
The generation for enough inhibiting its second harmonic ensures the stabilization of output amplitude to reduce the distortion of phase；Using the first clock chip
Has dephased differential pair signal to the output of the clock chip of rear class clock module, what it is due to output is two letters to interweave
Number, therefore transmission rate is faster, drives the effect of clock chip good, high stability ensure that the quality of output signal；According to difference
The inversion principle to signal, these clock chips is divided to produce corresponding differential-pair clock signals using the reversion of internal level,
Due to being the reversion for carrying level inside clock chip, level is more stable, can reduce phase error.Therefore, of the invention
Unbalance differential signal and lifting system Signal-to-Noise-and-distortion ratio and spurious-free dynamic range are can inhibit, the globality of raising system is conducive to
Energy.
Description of the drawings
Present pre-ferred embodiments are provided below in conjunction with the accompanying drawings, with the embodiment that the present invention will be described in detail.
Fig. 1 is the structural principle block diagram of the present invention；
Fig. 2 is the schematic diagram of the difference channel of the present invention；
Fig. 3 is the schematic diagram of the clock circuit of the present invention.
Specific implementation mode
- Fig. 3 referring to Fig.1, a kind of high-speed ADC interleave samples system of the invention, including difference channel a and clock circuit b,
Difference channel a and clock circuit b are connect with the ADC of N channel by differential pair transmission line respectively；Difference channel a includes order levels
The the first transformer T1 and the second transformer T2 of connection, and for defeated to the signal of signal to the ADC of N channel difference input differences
Go out module 4, the input terminal of signal output module 4 is connected to the output end of the second transformer T2；Clock circuit b includes for N
The ADC in channel distinguishes rear class clock module 6 of the input difference to clock signal, and has for being inputted to rear class clock module 6
First clock chip U1A of dephased differential pair signal；Rear class clock module 6 includes the ADC difference of N/2 blocks and N channel
Matched second clock chip U2A, N/2 block second clock chip U2A is connected respectively to the output end of the first clock chip U1A.
Wherein, further include the first input for inputting single-ended signal to the first transformer T1 with reference to Fig. 2, difference channel a
Module 1, the first input module 1 are connected to the input terminal of the first transformer T1.
Wherein, with reference to Fig. 3, the invention also includes the second inputs for inputting initial signal to the first clock chip U1A
Module 5, the second input module 5 and the first ends clock chip U1A are connected to together.
Wherein, with reference to Fig. 3, it is preferable that rear class clock module 6 includes 2 pieces of second clocks to match with the ADC in 4 channels
Chip U2A, 2 pieces of second clock chip U2A are connected respectively to the output end of the first clock chip U1A.
Wherein, the internal resistance parallel end connection of the input terminal of second clock chip U2A and the chip.
Specifically, the desirable even numbers more than 2 of N；Preferably, in the present embodiment, N=4, but do not limit, for example, into one
The ADC in 8 channels can be achieved in step, i.e. N may be 8 or other numbers, as long as system structure can be matching on the whole.
Specifically, radio-frequency transformer MABA-007159 may be used in the first transformer T1 and the second transformer T2, this transformation
Device uses 1:1 radio-frequency transmission line, bandwidth 4.5Hz-3000MHz, the first input module 1 are transmitting one just to the first transformer T1
String single-ended signal is converted into differential signal after the first transformer T1 and passes to the second transformer T2 again, to output difference pair
Then signal ADC_P and ADC_N export four groups of differential pair signals by via T-type structure on pcb board, i.e. ADC1_P,
ADC1_N, ADC2_P, ADC2_N, ADC3_P, ADC3_N, ADC4_P, ADC4_N, using the input as four-way ADC.
Initial signal is exported to the first clock chip U1A using the second input module 5, then the first clock chip U1A productions
Bear the differential-pair clock signals that two-way phase difference is 90 ° is conducive to differential pair signal according to the inversion principle of differential pair signal
The signal combination that a pair of of amplitude is opposite, equal in magnitude, amplitude is the two difference a, it is assumed that signal phase is 0 °, then it is reversed
Phase is 180 °, and correspondingly, another signal phase is 90 °, and reverse phase is 270 °, also just produces four road clock letters in this way
Number CLK0_P, CLK0_N, CLK90_P, CLK90_N, CLK180_P, CLK180_N, CLK270_P, CLK270_N, to export
To the ADC in 4 channels.
Chip in clock circuit b using 95ps propagation delays, 7.5GHz triggerings rate, randomized jitter clock core
Piece, and the relational expression of clock jitter and signal-to-noise ratio is as follows：
SNRj=-20log (2 π fadcμadc)……1
SNR=-20log (2 π fadcσj)……2
When input signal frequency to timing, the intrinsic jitter σ of ADC can be calculated according to chip handbook and formula 1adc, by formula
3 it is found that clock jitter σclkSmall as possible, the Signal to Noise Ratio (SNR) of system just can be high at this time, wherein SNRjFor Signal-to-Noise-and-distortion ratio, fadcFor ADC
Eigenfrequency, σjFor thrashing, by calculating, result of calculation is more than freely shaking inside the clock chip used
60fs, i.e. clock jitter meet the requirements, then Signal-to-Noise-and-distortion ratio is also satisfactory, and do not interfere with the overall performance of system.
For the first clock chip U1A and second clock chip U2A, input letter can be effectively eliminated by the way of termination
Number reflection, coupled as AC wherein the input terminal of the first clock chip U1A has accessed the capacitance of 100nF one by one, cooperation
Its internal resistance is attached, and without connecting non-essential resistance, it is nervous can to alleviate PCB layouts；The parallel connection of second clock chip U2A
Termination is pulled up using the voltage of the additional 1.3V of resistance of chip interior to complete, and is not necessarily to non-essential resistance, can equally be alleviated PCB
Layout is nervous.
Power splitter is formed using two transformers of concatenated in order, the generation of second harmonic can be inhibited, to reduce phase
The distortion of position, ensures the stabilization of output amplitude；It is exported to the clock chip of rear class clock module 6 using the first clock chip U1A
Has dephased differential pair signal, what it is due to output is two signals to interweave, therefore transmission rate is faster, drives clock chip
Effect it is more preferable, high stability ensure that the quality of output signal；According to the inversion principle of differential pair signal, these clocks
Chip produces corresponding differential-pair clock signals using the reversion of internal level, due to being to carry level inside clock chip
Reversion, therefore level is more stablized, and phase error can be reduced.Therefore, the present invention can inhibit differential signal it is unbalance and promoted system
System Signal-to-Noise-and-distortion ratio and spurious-free dynamic range, are conducive to the overall performance of raising system.
Wherein, with reference to Fig. 2, difference channel a further includes for the matched matching module of output as the second transformer T2
2, matching module 2 is connected to the output end of the second transformer T2, and matching module 2 includes being connected to the second transformer T2 output ends
4th resistance R4 and the 5th resistance R5, the 4th resistance R4 and the 5th resistance R5 are connected in series；Further include the second capacitance C2, the second electricity
The point of intersection in the 4th resistance R4 and the 5th resistance R5 is arranged in the one end for holding C2, and the other end is connected to reference ground；Matching module 2 makes
Next stage can be delivered to by stabilization by obtaining differential pair signal.
Wherein, further include being filtered for the differential pair signal to the second transformer T2 outputs with reference to Fig. 2, difference channel a
The filter module 3 of wave, filter module 3 are arranged between the output end and signal output module 4 of the second transformer T2, filter module
3 use two filter capacitors, i.e. the first capacitance C1 and third capacitance C3 to realize, can get rid of miscellaneous in differential pair signal
Matter so that the differential pair signal quality higher of output；First capacitance C1 and third capacitance C3 are connected to the defeated of the second transformer T2
Outlet.
Wherein, with reference to Fig. 2, signal output module 4 includes N number of difference block 41 to match with N channel ADC, N number of difference
Module 41 is connected respectively to the output end of the second transformer T2, and the effect of difference block 41 is to reduce the loss of differential pair signal,
It is set completely to be delivered to ADC.
Wherein, with reference to Fig. 2, difference block 41 includes the first resistor R1 and second resistance for promoting channel isolation
R2 further includes the 3rd resistor R3 for converting differential pair signal to from current source type voltage-type；First resistor R1 and second
Resistance R2 is separately positioned in two signal lines, and the ends 3rd resistor R3 are connected between two signal lines.
Specifically, first resistor R1 and second resistance R2 is for promoting channel isolation, to reduce the insertion of passive channel
Loss, and differential pair signal is current source type, so current source type is turned to signal using 3rd resistor R3 terminating differentials
At voltage-type.
Presently preferred embodiments of the present invention and basic principle is discussed in detail in the above content, but the invention is not limited in
The above embodiment, those skilled in the art should be recognized that also had under the premise of without prejudice to spirit of that invention it is various
Equivalent variations and replacement, these equivalent variations and replacement all fall within the protetion scope of the claimed invention.
Claims (8)
1. a kind of high-speed ADC interleave samples system, it is characterised in that：Including difference channel (a) and clock circuit (b), the difference
Parallel circuit (a) and clock circuit (b) are connect with the ADC of N channel by differential pair transmission line respectively；Difference channel (a) packet
The first transformer (T1) and the second transformer (T2) of concatenated in order are included, and for distinguishing input difference pair to the ADC of N channel
The input terminal of the signal output module (4) of signal, the signal output module (4) is connected to the output of the second transformer (T2)
End；The clock circuit (b) includes the rear class clock module for distinguishing input difference to clock signal to the ADC of N channel
(6), and for the first clock chip (U1A) to the dephased differential pair signal of rear class clock module (6) input tool；Institute
State the matched second clock chip (U2A) of ADC difference that rear class clock module (6) includes N/2 blocks and N channel, the N/2 blocks
Two clock chips (U2A) are connected respectively to the output end of the first clock chip (U1A).
2. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：The difference channel (a) is also
The first input module (1) including being used to input from single-ended signal to the first transformer (T1), the first input module (1) connection
To the input terminal of the first transformer (T1).
3. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：The difference channel (a) is also
Including being used for the matched matching module of output (2) as the second transformer (T2), the matching module (2) is connected to the second change
The output end of depressor (T2).
4. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：The difference channel (a) is also
Including the filter module (3) for being used to be filtered the differential pair signal that the second transformer (T2) exports, the filter module (3)
It is arranged between the output end and signal output module (4) of the second transformer (T2).
5. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：The signal output module
(4) difference block (41) that include N number of and N channel ADC matches, N number of difference block (41) are connected respectively to the second change
The output end of depressor (T2).
6. a kind of high-speed ADC interleave samples system according to claim 5, it is characterised in that：The difference block (41)
Include for promoting the first resistor of channel isolation (R1) and second resistance (R2), further include for by differential pair signal from electricity
Stream source type is converted into the 3rd resistor (R3) of voltage-type；The first resistor (R1) and second resistance (R2) are separately positioned on two
On signal wire, the 3rd resistor (R3) terminates between two signal lines.
7. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：Further include for first
Clock chip (U1A) inputs the second input module (5) of initial signal, second input module (5) and the first clock chip
(U1A) it is terminated at together.
8. a kind of high-speed ADC interleave samples system according to claim 1, it is characterised in that：The second clock chip
(U2A) the internal resistance parallel end connection of input terminal and the chip.
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| CN201810109473.3A CN108390673A (en) | 2018-02-05 | 2018-02-05 | A kind of high-speed ADC interleave samples system |
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| CN201810109473.3A CN108390673A (en) | 2018-02-05 | 2018-02-05 | A kind of high-speed ADC interleave samples system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113945834A (en) * | 2021-09-30 | 2022-01-18 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113945834B (en) * | 2021-09-30 | 2024-03-19 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
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Application publication date: 20180810 |