CN110109006A - A kind of JTAG level pinboard, veneer and debugging single board system - Google Patents
A kind of JTAG level pinboard, veneer and debugging single board system Download PDFInfo
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- CN110109006A CN110109006A CN201910265779.2A CN201910265779A CN110109006A CN 110109006 A CN110109006 A CN 110109006A CN 201910265779 A CN201910265779 A CN 201910265779A CN 110109006 A CN110109006 A CN 110109006A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318597—JTAG or boundary scan test of memory devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Present description provides a kind of JTAG level pinboard, veneer and debugging single board systems, the JTAG level pinboard is used for the jtag test of veneer, the level pinboard includes printed circuit board, the printed circuit board is equipped with the JTAG switching interface of at least two varying levels, level shifting circuit is equipped between the JTAG switching interface of at least two varying level, the level shifting circuit is used to convert the signal level of interaction between two JTAG switching interfaces.The present invention is in view of only can just use level conversion in test phase, usually the electrical level transferring chip on veneer does not work, therefore the present invention removes the electrical level transferring chip on veneer, an individually designed level pinboard, in debugging, the level pinboard of design is connect with veneer, after debugging, is disconnected；Pass through the independent design of level pinboard, it is possible to reduce the boom cost of veneer and the complexity of design, and the reliability of single board system is improved, reduce the power consumption of Board Power up road system.
Description
Technical field
This specification is related to the communications field more particularly to a kind of JTAG level pinboard, veneer and debugging single board system.
Background technique
JTAG is a kind of international standard test protocol (IEEE 1149.1 is compatible), is mainly used for chip interior test.Now
Most high-grade devices all support JTAG protocol, such as DSP, FPGA, ARM, part single-chip microcontroller device, due to jtag interface feature
It is that interface is simple, speed of download is fast, versatility is good, these devices nearly all use jtag interface to connect as program downloading, debugging
Mouthful.The jtag interface of standard is 4 lines, and respectively model selection (TMS), clock (TCK), Data In-Line (TDI) and data are defeated
Outlet (TDO)；Related JTAG pin is defined as: TCK is test clock input；TDI is test data input, and data pass through
TDI pin inputs jtag interface；TDO is test data output, and data are exported by TDO pin from jtag interface；TMS is test
Model selection, TMS, which is used to that jtag interface is arranged, is in certain specific test pattern.
With the development of electronic technology, the integrated level of various chips is higher and higher, and volume power consumption is also smaller and smaller, each chip
The level voltage of I/O port is also lower and lower, meanwhile, the level of the jtag interface of each chip is also lower and lower, generally 1.51V, and
The corresponding level of JTAG cable is generally 3.3V on JTAG connector, greater than the level of the jtag interface of each chip, therefore needs
An electrical level transferring chip is added on circuit single plate, the JTAG cable on the JTAG connector of debugging is first connected to level conversion
Chip when connecting with the jtag interface of chip, needs electrical level transferring chip on veneer by the jtag interface of chip to be debugged
The level that level conversion is supported to JTAG cable.In this way, just can be achieved to carry out emulation testing to veneer.
Summary of the invention
To overcome the problems in correlation technique, present description provides a kind of JTAG level pinboard, veneer and lists
Plate debugging system.
According to this specification embodiment in a first aspect, providing a kind of JTAG level pinboard, the level pinboard is used
In the jtag test of veneer, the level pinboard includes printed circuit board, and the printed circuit board is equipped at least two not
With the JTAG switching interface of level, level shifting circuit is equipped between the JTAG switching interface of at least two varying level,
The level shifting circuit is used to convert the signal level of interaction between two JTAG switching interfaces.
According to the second aspect of this specification embodiment, a kind of veneer is provided, the veneer includes printed circuit board, described
Printed circuit board is equipped at least one chip, at least one described chip is connected with jtag interface, wherein the jtag interface
Level and at least one described chip on the level of JTAG signal pin that has the function of it is identical.
According to the third aspect of this specification embodiment, a kind of debugging single board system is provided, the system comprises:
Veneer, the veneer include the first printed circuit board, and first printed circuit board is equipped at least one chip, institute
State at least one chip and be connected with jtag interface, wherein the level of the jtag interface at least one described chip have phase
It is identical with the level of the pin of semiotic function；
Level conversion plate, the level conversion plate include the second printed circuit board, and second printed circuit board is equipped with
First JTAG switching interface and the 2nd JTAG switching interface, the first JTAG switching interface connect with the 2nd JTAG
Level shifting circuit is equipped between mouthful, the level shifting circuit is for converting the first JTAG switching interface and described second
The signal level of interaction between JTAG switching interface；Wherein, the first JTAG switching interface is connect with the jtag interface.
The technical solution that the embodiment of this specification provides can include the following benefits:
In this specification embodiment, a kind of veneer is provided, electrical level transferring chip is not provided on the veneer, it directly will be to
The pin for testing the identical semiotic function of chip leads to jtag interface, and then, which is transferred with the level provided
Corresponding first JTAG switching interface connection on plate receives corresponding signal, then passes through the level switching electricity on level pinboard
The signal level that road supports the level conversion of signal to JTAG cable, and the signal that the JTAG cable is supported is sent to second
JTAG switching interface is connected to the 2nd JTAG switching interface by JTAG cable, to read and write the letter that the JTAG cable is supported
Number.Wherein, due to only can just use level conversion in the debugging stage, usually the electrical level transferring chip on veneer does not work,
Therefore the present invention removes the electrical level transferring chip on veneer, an individually designed level pinboard, in debugging, by the electricity of design
Flat turn fishplate bar is connect with veneer, after debugging, is disconnected；Pass through the independent design of level pinboard, it is possible to reduce veneer
Boom cost and design complexity, and improve the reliability of single board system, reduce the power consumption of Board Power up road system.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
This specification can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the reality for meeting this specification
Example is applied, and is used to explain the principle of this specification together with specification.
Fig. 1 is a kind of this specification veneer shown according to an exemplary embodiment.
Fig. 2 is this specification another veneer shown according to an exemplary embodiment.
Fig. 3 is this specification another veneer shown according to an exemplary embodiment.
Fig. 4 is a kind of this specification JTAG level pinboard shown according to an exemplary embodiment.
Fig. 5 is a kind of this specification debugging single board system shown according to an exemplary embodiment.
Specific embodiment
Example embodiments are described in detail here, and the example is illustrated in the accompanying drawings.Following description is related to
When attached drawing, unless otherwise indicated, the same numbers in different drawings indicate the same or similar elements.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with this specification.On the contrary, they are only and such as institute
The example of the consistent device and method of some aspects be described in detail in attached claims, this specification.
It is only to be not intended to be limiting this explanation merely for for the purpose of describing particular embodiments in the term that this specification uses
Book.The "an" of used singular, " described " and "the" are also intended to packet in this specification and in the appended claims
Most forms are included, unless the context clearly indicates other meaning.It is also understood that term "and/or" used herein is
Refer to and includes that one or more associated any or all of project listed may combine.
It will be appreciated that though various information may be described using term first, second, third, etc. in this specification, but
These information should not necessarily be limited by these terms.These terms are only used to for same type of information being distinguished from each other out.For example, not taking off
In the case where this specification range, the first information can also be referred to as the second information, and similarly, the second information can also be claimed
For the first information.Depending on context, word as used in this " if " can be construed to " ... when " or
" when ... " or " in response to determination ".
Next this specification embodiment is described in detail.
As shown in Figure 1, Fig. 1 is a kind of this specification veneer shown according to an exemplary embodiment.It is wrapped on the veneer
Include integrated chip to be tested, such as CPU, FPGA or DSP etc., the JTAG function pin of the chip, such as TCK, TMS,
These pins of TDI and TDO, the signal level supported is generally lower, generally 1.5V.JTAG is additionally provided on the veneer to connect
Mouthful, the jtag interface with the JTAG cable of external testing for connecting, due to supporting the signal transmitted on JTAG cable
Level is comparatively larger, generally 3.3V, therefore props up in the signal level and JTAG cable supported at the jtag interface on veneer
The level for holding the signal of transmission is identical, is also 3.3V.Therefore JTAG function pin is connect with the jtag interface on chip to be realized,
Realize that data signal transmission devises an electrical level transferring chip in the related technology on veneer, for realizing chip JTAG function
The conversion between the level of signal can be supported at pin at the level and jtag interface of signal, with matching chip and jtag interface it
Between level.It is found that the electrical level transferring chip realizes, signal level is 1.5V and signal level is between 3.3V in figure
Conversion.
The technical problem is solved by increasing by an electrical level transferring chip on veneer, it is contemplated that veneer normally makes
In the case where, do not need only just to use the level conversion core in debugging single board using to the electrical level transferring chip
Piece.In this way, the electrical level transferring chip utilization rate on veneer is lower, and increase on veneer a chip will increase BOOM cost with
And increase the design complexities of veneer；In addition also making the reliability of veneer reduces, and power consumption increases.
In an embodiment of the invention, as shown in Fig. 2, Fig. 2 is that this specification is shown according to an exemplary embodiment
Another veneer, the veneer include printed circuit board, and the printed circuit board is equipped at least one chip, which can be with
It is one or more of CPU, FPGA or DSP etc., at least one described chip is connected with jtag interface, that is to say, that chip
Upper JTAG function pin (TCK, TMS, TDI and TDO) is connected directly to the jtag interface on veneer.Wherein, the JTAG connects
Has the function of the level of the pin (i.e. JTAG signal pin) of identical semiotic function on the level and at least one described chip of mouth
Identical, i.e., JTAG signal function pin is correspondingly connected with jtag interface basis signal function on the described chip, wherein jtag interface
Locate signal level with the level of signal is identical at JTAG function pin on chip, be all lower level, such as 1.5V.
In addition, there are also the supply voltage obtained from external or chip on jtag interface, V1.5 as described in Figure and
V3.3。
In one embodiment, as shown in figure 3, Fig. 3 is this specification another kind shown according to an exemplary embodiment
Veneer, the printed circuit board are equipped at least two chips (CPU and FPGA in such as figure), and at least two chip all connects
It is connected to the jtag interface, the JTAG signal function pin at least two chip is corresponding with the jtag interface
Complexing pin connection.Wherein, by as shown in the figure, from the corresponding complexing pin of the jtag interface (TCK_, TMS_, TDI_ and
TDO_ 4 root functionality lines have been drawn at) respectively, have been correspondingly connected with respectively with the JTAG signal function pin of each chip.
In one embodiment, the JTAG signal function pin of a chip at least two chip with it is described multiple
With gating circuit is equipped between pin, the gating circuit is for selecting a chip at least two chip
It is logical.As seen from Figure 3, a gating circuit is designed between each chip and the jtag interface, in the functional line
There are multiple gating circuits corresponding with each chip, one of gating circuit is gated, and other gating circuits do not gate, then select
Logical gating circuit corresponds to chip and is connected to jtag interface, by the circuit outside jtag interface connects, can be realized
The chip is tested.
In one embodiment, the gating circuit includes toggle switch, described toggle switch one end and one of them
The JTAG signal function pin of chip connects, and the other end is connect with the complexing pin.Herein, by the setting of toggle switch come
It realizes the gating to gating circuit or shutdown, specifically may is that toggle switch has 0 and 1 two state, represent and correspond to when pushing 1
Gating circuit gating, push 0 Shi Ze represent for gating circuit it is not gated, it is every time when test, chip to be tested is corresponding
Gating circuit in toggle switch state be set to 1, and the toggle switch state in other gating circuits is set to 0, then can be real
Connection when now testing chip to be tested.
In the present embodiment, at jtag interface above-mentioned on the level and chip of signal at JTAG function pin signal electricity
Flat is all 1.5V, this is exemplary, and level value is also possible to other lower levels, herein with no restrictions.In addition, if single
When having multiple chips on plate, signal level at the complexing pin of jtag interface and the JTAG function pin of the chip of corresponding gating
The signal level at place is identical.In general, the signal level at the JTAG function pin of each chip is 1.5V, therefore exemplary one
In embodiment, the signal level at the complexing pin of the jtag interface is also 1.5V.
In the present embodiment, on the veneer and electrical level transferring chip, the signal level of the jtag interface are not provided with
The signal level supported with external JTAG cable is not identical, therefore in chip testing, JTAG cable can not be connected directly
To the jtag interface.
In an embodiment of the invention, as shown in figure 4, Fig. 4 is one kind shown in one exemplary embodiment of this specification
JTAG level pinboard, the level pinboard are used for the jtag test of veneer, and the level pinboard includes printed circuit board,
The printed circuit board is equipped with the JTAG switching interface of at least two varying levels, the JTAG of at least two varying level
Level shifting circuit is equipped between switching interface, the level shifting circuit is for converting between two JTAG switching interfaces
Interactive signal level.Wherein, the JTAG switching interface of at least two varying level includes: on veneer to be tested
First JTAG switching interface of jtag interface connection, and the 2nd JTAG switching interface being connect with the JTAG cable of debugging.
Wherein, the signal level at the first JTAG switching interface is consistent with the signal level at the jtag interface on veneer, generally
For 1.5V；The signal level one that the JTAG cable of signal level and external testing at the 2nd JTAG switching interface is supported
It causes, generally 3.3V.
In one embodiment, the first JTAG switching interface receives the power supply that veneer to be debugged provides, and is described
Level shifting circuit provides power supply.Wherein, due to receiving the power supply V1.5 and V3.3 that have on veneer on jtag interface, when described
When first JTAG switching interface is connect with the jtag interface on the veneer of aforementioned proposition, the first JTAG switching interface is then
The power supply V1.5 and V3.3 on jtag interface are obtained, and is based on the power supply, for level shifting circuit power supply.
In the present embodiment, independent to devise a JTAG level pinboard, it is arranged on the JTAG level pinboard
There is a JTAG switching interface for connecting with the external veneer, and is additionally provided with for being connect with external JTAG cable
Another JTAG switching interface, it is however generally that, the signal level at two JTAG switching interfaces is different, therefore at the two
Being added between JTAG switching interface has level shifting circuit, to realize turning for the signal level at two JTAG switching interfaces
It changes.
In one embodiment, as shown in figure 5, Fig. 5 is a kind of debugging single board system shown according to an exemplary embodiment
System, the system comprises have:
Veneer, the veneer include the first printed circuit board, and first printed circuit board is equipped at least one chip
(CPU/FPGA), at least one described chip is connected with jtag interface, wherein the level of the jtag interface and described at least one
Have the function of that the level of the pin (the JTAG pin of i.e. each chip) of identical semiotic function is identical on a chip；
Level conversion plate, the level conversion plate include the second printed circuit board, and second printed circuit board is equipped with
First JTAG switching interface and the 2nd JTAG switching interface, the first JTAG switching interface connect with the 2nd JTAG
Level shifting circuit is equipped between mouthful, the level shifting circuit is for converting the first JTAG switching interface and described second
The signal level of interaction between JTAG switching interface；
Wherein, the first JTAG switching interface on the level conversion plate is connect with the jtag interface on the veneer.Institute
The 2nd JTAG switching interface stated on level conversion plate is connect with external JTAG cable.
In one embodiment, the jtag interface on the veneer connects with the first JTAG on the level conversion plate
Mouth is connected by cable, it is also possible that the first JTAG switching interface on the level conversion plate is plugged on the veneer
Jtag interface, to realize connection, specific connection type, the present invention is not particularly limited.In addition, the veneer passes through after connection
The jtag interface and the first JTAG switching interface provide power supply for the level conversion plate.
It in one embodiment, further include debugging emulation device in the system, the debugging emulation device passes through JTAG cable
It is connected to the 2nd JTAG switching interface.
Below for a specific example, illustrate this programme, specifically:
As shown in figure 5, the level at the JTAG function pin of the chip is 1.5V, and the JTAG cable of test is supported
Level be 3.3V, then need level conversion that the signal that level is 1.5V is converted to the signal that level is 3.3V at this time, come
At test.It is that electrical level transferring chip is placed on veneer, so that the electricity at the jtag interface on veneer in traditional technical solution
Flat is 3.3V, can directly be connect with JTAG cable.
And in the present solution, level shifting circuit is individually designed, and design two JTAG with level shifting circuit cooperation
Switching interface, by them on a level pinboard, when needing to test single chip on board, then first by the level
Pinboard is connected on veneer, and then JTAG cable is connect with level pinboard again.Wherein, it is then no longer set on veneer to be tested
It is equipped with electrical level transferring chip, level conversion is not carried out to signal on veneer to be tested in this way, then at the jtag interface on veneer
Signal level is still 1.5V.
Specific connection are as follows: connect the jtag interface of veneer with the first JTAG switching interface of the level pinboard, then
Signal level at first JTAG switching interface of the level pinboard is also 1.5V, and after connection, the veneer is the electricity
The signal that the level at the first JTAG switching interface is 1.5V is converted in the power supply of flat turn fishplate bar, the level translation circuit work
The 2nd JTAG switching interface is given at the signal that level is 3.3V, then, then JTAG cable is connected on the level pinboard
The 2nd JTAG switching interface, and JTAG cable supports that the level of signal of transmission is also 3.3V, in this way, can then be debugged
?.Wherein, the first JTAG switching interface is different from the level of the 2nd JTAG switching interface, and when design makes two interfaces different,
It is directly connected to JTAG cable to prevent veneer from not passing through level conversion plate and damages chip.
After to be debugged, it is contemplated that in the normal working of single board stage, do not need level pinboard, therefore veneer disconnect with it is described
The level pinboard is extracted in the connection of level pinboard.
As it can be seen that provide a kind of veneer in this specification embodiment, be not provided with electrical level transferring chip on the veneer,
Directly the pin of the identical semiotic function of chip to be tested is led into jtag interface, then, by the jtag interface with provide
Corresponding first JTAG switching interface connection, receives corresponding signal, then pass through the electricity on level pinboard on level pinboard
The signal level that flat built-up circuit supports the level conversion of signal to JTAG cable, and the signal that the JTAG cable is supported is sent out
It send to the 2nd JTAG switching interface, the 2nd JTAG switching interface is connected to by JTAG cable, to read and write the JTAG cable
The signal of support.Wherein, due to only can just use level conversion in the debugging stage, usually the electrical level transferring chip on veneer is simultaneously
It does not work, therefore the present invention removes the electrical level transferring chip on veneer, an individually designed level pinboard will in debugging
The level pinboard of design is connect with veneer, after debugging, is disconnected；It, can be with by the independent design of level pinboard
The boom cost of veneer and the complexity of design are reduced, and improves the reliability of single board system, reduces Board Power up road system
The power consumption of system.
Those skilled in the art will readily occur to this specification after considering specification and practicing the invention applied here
Other embodiments.This specification is intended to cover any variations, uses, or adaptations of this specification, these modifications,
Purposes or adaptive change follow the general principle of this specification and do not apply in the art including this specification
Common knowledge or conventional techniques.The description and examples are only to be considered as illustrative, the true scope of this specification and
Spirit is indicated by the following claims.
It should be understood that this specification is not limited to the precise structure that has been described above and shown in the drawings,
And various modifications and changes may be made without departing from the scope thereof.The range of this specification is only limited by the attached claims
System.
The foregoing is merely the preferred embodiments of this specification, all in this explanation not to limit this specification
Within the spirit and principle of book, any modification, equivalent substitution, improvement and etc. done should be included in the model of this specification protection
Within enclosing.
Claims (10)
1. a kind of JTAG level pinboard, which is characterized in that the level pinboard is used for the jtag test of veneer, the level
Pinboard includes printed circuit board, and the printed circuit board is equipped with the JTAG switching interface of at least two varying levels, described
Level shifting circuit is equipped between the JTAG switching interface of at least two varying levels, the level shifting circuit is for converting two
The signal level of interaction between a JTAG switching interface.
2. a kind of JTAG level pinboard according to claim 1, which is characterized in that at least two varying level
JTAG switching interface includes: the first JTAG switching interface connecting with the jtag interface on veneer to be tested, and with tune
2nd JTAG switching interface of JTAG cable connection on probation.
3. a kind of JTAG level pinboard according to claim 2, which is characterized in that the first JTAG switching interface connects
The power supply that veneer to be debugged provides is received, and provides power supply for the level shifting circuit.
4. a kind of veneer, which is characterized in that the veneer includes printed circuit board, and the printed circuit board is equipped at least one
Chip, at least one described chip are connected with jtag interface, wherein the level of the jtag interface and at least one described chip
On the level of JTAG signal pin that has the function of it is identical.
5. a kind of veneer according to claim 4, which is characterized in that the printed circuit board is equipped at least two cores
Piece, at least two chip are connected to the jtag interface, the JTAG signal function pin at least two chip
Connected with complexing pin corresponding in the jtag interface.
6. a kind of veneer according to claim 5, which is characterized in that a chip at least two chip
Gating circuit is equipped between JTAG signal function pin and the complexing pin, the gating circuit is used for described at least two
A chip in chip is gated.
7. a kind of veneer according to claim 6, which is characterized in that the gating circuit includes toggle switch, described
Toggle switch one end is connect with the JTAG signal function pin of one of chip, and the other end is connect with the complexing pin.
8. a kind of debugging single board system, which is characterized in that the system comprises:
Veneer, the veneer include the first printed circuit board, first printed circuit board be equipped at least one chip, it is described extremely
A few chip is connected with jtag interface, wherein the level of the jtag interface at least one described chip with identical letter
The level of the pin of number function is identical；
Level conversion plate, the level conversion plate include the second printed circuit board, and second printed circuit board is equipped with first
JTAG switching interface and the 2nd JTAG switching interface, the first JTAG switching interface and the 2nd JTAG switching interface it
Between be equipped with level shifting circuit, the level shifting circuit is for converting the first JTAG switching interface and the 2nd JTAG
The signal level of interaction between switching interface；Wherein, the first JTAG switching interface is connect with the jtag interface.
9. a kind of debugging single board system according to claim 8, which is characterized in that jtag interface and institute on the veneer
The first JTAG switching interface stated on level conversion plate is connected by cable, and the veneer is the level conversion plate after connection
Power supply is provided.
10. a kind of debugging single board system according to claim 8, which is characterized in that the system also includes debugging emulations
Device, the debugging emulation device are connected to the 2nd JTAG switching interface by JTAG cable.
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| CN201910265779.2A CN110109006A (en) | 2019-04-03 | 2019-04-03 | A kind of JTAG level pinboard, veneer and debugging single board system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110780183A (en) * | 2019-10-16 | 2020-02-11 | 中国航空工业集团公司洛阳电光设备研究所 | Interface circuit for JTAG boundary scan test |
| CN117728899A (en) * | 2024-02-06 | 2024-03-19 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
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| CN207198842U (en) * | 2017-07-27 | 2018-04-06 | 中国航空综合技术研究所 | A kind of universal parallel port fault injection device based on JTAG |
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|---|---|---|---|---|
| CN110780183A (en) * | 2019-10-16 | 2020-02-11 | 中国航空工业集团公司洛阳电光设备研究所 | Interface circuit for JTAG boundary scan test |
| CN117728899A (en) * | 2024-02-06 | 2024-03-19 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
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Application publication date: 20190809 |