CN104485135A - Multimode SRAM single-particle testing method and device - Google Patents
Multimode SRAM single-particle testing method and device Download PDFInfo
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Abstract
The invention provides a multimode SRAM single-particle testing method and a multimode SRAM single-particle testing device. The device comprises a control board and a testing board, wherein the control board comprises a power supply module, a communication module, a buffering module, a main control module, a current monitoring module, a level conversion module and a first interface module; the testing board comprises a second interface module and a testing clamp. The invention further provides the multimode SRAM single-particle testing method. The device provided by the invention can utilize three modes to test multiple SRAM chips; during testing, a power supply of a to-be-tested SRAM and a signal voltage value can be configured in an upper computer as required so as to facilitate the testing. A data comparison operation of a testing system is performed by an FPGA, and a quick error bit counting algorithm is utilized, so that compared error data can be quickly obtained in real time.
Description
Technical field
The present invention relates to the fields such as device reliability, Aeronautics and Astronautics field, automotive electronics, communication, particularly relate to a kind of multi-mode SRAM single-particle method of testing and device.
Background technology
SRAM (static RAM) storer has the advantages such as access speed is fast, and therefore in the development of Aeronautics and Astronautics device electronic system, a large amount of SRAM that uses comes store configuration information, test data etc.And spacecraft flies in space, be in the radiation environment of charged particle formation always, high energy proton in space radiation environment, heavy ion, neutron in atmospheric environment can cause the SRAM device generation single particle effect in Aeronautics and Astronautics device, make the data stored in SRAM that random change occur, affect the reliability of device, so the ability direct relation of SRAM device anti-single particle effect the stability of spacecraft in spacecraft.In addition, along with reducing of device critical dimensions, the α particle during uphole equipment SRAM encapsulates is also to causing single particle effect, have a strong impact on the normal work of equipment, control system particularly in automobile, the equipment such as the switch of communication, financial field, bring hidden danger can to the property of people and safety.
Existing single-particle test macro, function ratio is more single, when testing SRAM device single particle effect, can not many-sided single particle effect parameter measuring SRAM device, thus ignore the single particle effect of some aspect of SRAM device.
Therefore, it is desirable to propose a kind of maturation, the single-particle method of testing of the SRAM of complete function improves the accuracy estimated measured device anti-single particle effect capability.
Summary of the invention
The invention provides a kind of multi-mode SRAM single-particle method of testing and device.
According to an aspect of the present invention, provide a kind of multi-mode SRAM single-particle proving installation, this device comprises following structure:
Control panel, described control panel comprises power module, communication module, cache module, main control module, current monitoring module, level switch module and first interface module;
Test board, described test board comprises the second interface module and test fixture.
According to another aspect of the present invention, additionally provide a kind of multi-mode SRAM single-particle method of testing, the method comprises the following steps:
A) host computer operation interface writes the vector file of test;
B) host computer transmits control signal to main control module;
C) host computer in cache module stored in the vector file that step a) is write;
D) main control module test data writes in chip to be measured;
E) data in chip to be measured are read;
F) in main control module FPGA by step e) in read chip to be measured in data and step c) in stored in vector file contrast, if comparing result is inconsistent, then return step a), if unanimously, then continue step g);
G) irradiation apparatus is opened;
H) selected test pattern in host computer, starts test;
I) host computer receives test data, and controls test end.
Compared with prior art, technical scheme tool provided by the invention is adopted to have the following advantages: the device that the present invention proposes can adopt Three models to test multi-disc sram chip, during test, the power supply of tested SRAM and signal voltage value can be arranged on demand in host computer, convenient test.Undertaken by the Data Comparison work of test macro is placed in FPGA, and adopt error bit statistic algorithm fast, the misdata of acquisition contrast that can be quick, real-time.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious.
Fig. 1 is multi-mode SRAM single-particle proving installation structural representation according to an embodiment of the invention;
Fig. 2 is according to Data Comparison algorithm flow chart of the present invention.
Embodiment
Embodiments of the invention are described below in detail.
The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.Disclosing hereafter provides many different embodiments or example is used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can in different example repeat reference numerals and/or letter.This repetition is to simplify and clearly object, itself does not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific device that the invention provides and the example of structure, but those of ordinary skill in the art can recognize the property of can be applicable to of other devices and/or the use of other structures.
According to an aspect of the present invention, a kind of multi-mode SRAM single-particle proving installation is provided.Below, by by one embodiment of the present of invention, the multi-mode SRAM single-particle proving installation shown in Fig. 1 is specifically described.As shown in Figure 1, multi-mode SRAM single-particle proving installation provided by the present invention comprises:
Two large divisions, a part is control panel 100, each main functional modules of described proving installation all on control panel 100, for the major function of test macro realizes part; Another part is test board 200, for installing SRAM device to be measured, and provides the connecting path of described device under test and control panel, will be specifically introduced below to these two parts.
Proving installation of the present invention is except above-mentioned two large modules, and also comprise a host computer, described host computer is connected with the communication module 103 in control panel 100, so just achieves the communication of host computer and control panel 100.Described host computer selects the common PC can running the required program of this test.
Control panel 100, described control panel comprises power module 101, communication module 103, cache module 102, main control module 104, current monitoring module 105, level switch module 106 and first interface module 107.
Wherein, power module 101 specifically comprises: fixed voltage output, and described fixed voltage output connects with each modular power source interface on control panel 100 and test board 200, for being above-mentioned each module for power supply.Described fixed voltage output at least comprises a power management chip, for input voltage being converted to the magnitude of voltage of each module on control panel 100 and test board 200.In one embodiment of the invention, input voltage is 12V, and the voltage needed for each module of test macro is respectively 3.3V, 2.5V, 1.2V, that therefore described fixed voltage output is that corresponding photovoltaic conversion chip selects is TPS65053, and those skilled in the art can reselect power management chip according to the different demands of design itself.
Programmable power supply part, described programmable power supply part is used for, and described programmable power supply part comprises two-way altogether, and each road all comprises following structure: high precision analog-digital chip, and described high precision analog-digital chip exports a small voltage by master control module controls; Differential amplifier, the small voltage that high precision analog-digital chip exports by described differential amplifier amplifies, and exports given voltage; Step-down switching regulator, described step-down switching regulator output voltage is to program-controlled resistor; Program-controlled resistor, described program-controlled resistor regulates the output voltage of step-down switching regulator, and the Darlington transistor connect for differential amplifier is powered.Described Darlington transistor can improve the electric current of output voltage, increases load capacity.In one embodiment of the invention, that wherein said high precision analog-digital chip, differential amplifier, step-down switching regulator, program-controlled resistor and Darlington transistor are selected respectively is DAC8685, AD8021, LT3685, AD5160 and TIP122, and those skilled in the art can choose the device of other models according to the actual requirements in other embodiments.
Wherein, described cache module 102 connects with power module, communication module and main control module respectively, for the data produced in On-board test.Concrete, cache module 102 comprises two parts: the first cache module, for preserving the data-signal in write SRAM; Second cache module, for preserving contrast misdata and address information.This carries out because SRAM data to contrast in the FPGA that work has been put in main control module by this proving installation, only uploads in host computer by last result data, therefore need to increase cache module on control panel, preserve comparing result.In embodiment at one of the present invention, the SRAM of IS61WV102416BLL model that what the first cache module adopted is, the SRAM of S61WV51232BLL model that what the second cache module adopted is.Those skilled in the art can choose the memory device of other models according to the actual requirements in other embodiments.
Wherein, described communication module 103 is connected with host computer, power module, cache module and main control module respectively, for realizing the communication between host computer and control panel.In an embodiment of the present invention, described communication module 103 is made up of USB control chip, such host computer just can be communicated by USB interface with between master control borad, in other embodiments, those skilled in the art are also by selecting other communication chip to realize communication to the interface mode using it corresponding.During test, namely tester sends instruction by this communication module, controls the break-make of whole test.In one embodiment of the invention, that USB control chip adopts is CY68013A, and those skilled in the art can choose the device of other models according to the actual requirements in other embodiments.
Wherein, described main control module 104 is core components of whole proving installation, be connected with power module, cache module, communication module and level switch module respectively, and receive the command signal from host computer by communication module, there is provided Control timing sequence for above-mentioned each module normally works, coordinate the work between each module.Meanwhile, the contrast work of SRAM data also completes in described main control module 104.In one embodiment of the invention, described main control module 104 is made up of FPGA and configuration circuit thereof, and selected FPGA is altera corp CycloneIII series EP3C120F780.Those skilled in the art can choose the device of other models according to the actual requirements in other embodiments.
Wherein, described current monitoring module 105 respectively with power module and first interface model calling, for monitoring the size sending into electric current in chip to be measured, after current value exceedes default threshold value, main control module transmits control signal disconnection relay, cut off the electricity supply, this ensures that there the safety of whole proving installation.
Described current monitoring module 105 specifically comprises: sense resistance, for current signal is converted to voltage signal; Differential amplifier, amplifies for voltage signal sense resistance be converted to; High precision analogue conversion chip, is converted to digital signal for the voltage signal after being amplified by differential amplifier and sends into main control module 104.Relay, by master control module controls, for controlling the break-make of chip power to be measured.In one embodiment of the invention, that wherein said sense resistance, high precision analog-digital chip, differential amplifier are selected respectively is 0.1 ohm, AD7689, AD8202, and relay is 5V Power supply.Those skilled in the art can choose the device of other models according to the actual requirements in other embodiments.
Wherein, described level switch module 106 respectively with main control module and first interface model calling.Described level switch module is made up of multi-disc level transferring chip, for chip under test interface level and FPGA interface level being changed.Because chip under test interface level variation range is comparatively wide, therefore level transferring chip need choose the chip had compared with wide voltage conversion range parameter.In one embodiment of the invention, selected level transferring chip is 74LVCH8T245.Those skilled in the art can choose the device of other models according to the actual requirements in other embodiments.
Wherein, described first interface module 107 is connected with the second interface module 201 on current monitoring module, level switch module and beta version 200 respectively, as the signal path between control panel and test board, make to communicate between control panel with test board, the test signal be about to from control panel is delivered to test board, and returns the test data that test board collects.
Test board 200, described test board comprises the second interface module 201 and test fixture 202.
Wherein, described second interface module 201 is connected with the first interface module 107 on each test fixture and control panel 100 respectively.Described first interface module 107 and choosing of the second interface module 201 can go out send consideration according to factors such as the data-handling capacities of the quantity of test fixture, control module.
Wherein, described test fixture 202 for fixing SRAM to be measured, and is connected with the test point of SRAM to be measured, as the signal path between test board and SRAM to be measured, during test, selects chip to be measured by chip selection signal.Meanwhile, the supply voltage of tested SRAM and signal voltage also can be arranged as required in the operation interface of host computer.Those skilled in the art can select the number of test fixture according to the data-handling capacity of selftest demand and control module, by the step selecting chip to be measured can save artificial handling from the chip selection signal of control module, accelerate testing efficiency, simplify testing process.
According to another aspect of the present invention, additionally provide a kind of multi-mode SRAM single-particle method of testing, the method comprises:
A) host computer 300 operation interface writes the vector file of test.
During test, operating personnel only need to select test vector in operation interface, and click generation button, and program can generate scale-of-two test vector file automatically, and described test vector file includes the test data in write SRAM to be measured.
B) host computer 300 transmits control signal to main control module 104.
Concrete, after the operation interface of host computer writes the vector file of test, the control signal from host computer can be sent to main control module by communication module by test macro.
C) vector file a) write stored in step in cache module 102 of host computer 300.
D) test data writes in chip to be measured by main control module 104.
E) data in chip to be measured are read.
F) FPGA in main control module 104 is by step e) in read chip to be measured in data and step c) in stored in vector file contrast, if comparing result is inconsistent, then return step a), if unanimously, then continue step g).
G) irradiation apparatus is opened.
H) selected test pattern in host computer, starts test.
Concrete, multi-mode SRAM single-particle proving installation of the present invention, there are three kinds of test patterns: the first is the current monitoring pattern under stationary state, namely current value to be uploaded in host computer by main control module and shows at operation interface by setting-up time, and this pattern can survey chip quiescent current; The second is the current monitoring pattern under continuous WriteMode, namely main control module writes test data continuously in SRAM to be measured, continuous monitoring chip to be measured current value used in the process, and upload in host computer and show record, this pattern can be surveyed chip and write the current value under state; The third is Data Comparison pattern, namely write data check errorless after, main control module is read continuously and is carried out Data Comparison record, in the process the current value of system monitoring chip under read states, and uploads in host computer and show record.Algorithm flow chart when carrying out Data Comparison in FPGA as shown in Figure 2.In Fig. 2, c is bit error count device, and n is the XOR value of correlation data and initialize data.The process of Data Comparison, namely calculates the process of the number of in n 1.By n value and n-1 value position with after value be assigned to n, if n value is not 0, then bit error count device c is added 1, continue present n value and n-1 value to carry out afterwards position and and judge; If n value is 0, then terminate whole Data Comparison process.The number of times of this contrast algorithm circulation is the number of in n 1, and when normal irradiation test, error bit is less, and namely in n, the number of 1 is less, so adopt this algorithm can effectively reduce the Data Comparison time.
Under irradiation behaviour, above-mentioned Three models can be selected as required to carry out the performance of test chip, test according to the first pattern, then current value to be uploaded in host computer by main control module and shows at operation interface by setting-up time.Test according to the second pattern, then main control module writes test data continuously in SRAM to be measured, in the process continuous monitoring chip to be measured current value used, and uploads in host computer and show record.Test according to the third pattern, then main control module constantly reads the data in chip to be measured, and the data of reading and preset data is contrasted, then by misdata stored in cache module.When main control module receives testing end signal, misdata to be imported in host computer and record through communication module.In the test process of the third pattern, host computer constantly reads erroneous values and the current value of contrast, facilitates tester's control and measuring process.
I) host computer receives test data, and controls test end.
Compared with prior art, the present invention has the following advantages: the present invention can adopt Three models to test multi-disc sram chip, and during test, the power supply of tested SRAM can be arranged on demand with signal voltage value in host computer, conveniently tests.Data Comparison of the present invention is operated in FPGA and carries out, and adopts error bit statistic algorithm fast, the misdata of acquisition contrast that can be quick, real-time.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection domain of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in instructions, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection domain.
Claims (20)
1. a multi-mode SRAM single-particle proving installation, this device comprises following structure:
Control panel (100), described control panel comprises power module (101), communication module (103), cache module (102), main control module (104), current monitoring module (105), level switch module (106) and first interface module (107);
Test board (200), described test board comprises the second interface module (201) and test fixture (202).
2. circuit according to claim 1, also comprises a host computer (300) and connects with communication module.
3. circuit according to claim 1, wherein, described power module (101) specifically comprises:
Fixed voltage output, described fixed voltage output connects with each modular power source interface on control panel (100) and test board (200), for being above-mentioned each module for power supply;
Programmable power supply part.
4. circuit according to claim 3, wherein, described fixed voltage output at least comprises a power management chip, for input voltage being converted to the magnitude of voltage of each module on control panel (100) and test board (200).
5. circuit according to claim 3, wherein, described programmable power supply part comprises two-way altogether, and each road comprises following structure:
High precision analog-digital chip, described high precision analog-digital chip exports a small voltage by master control module controls;
Differential amplifier, the small voltage that high precision analog-digital chip exports by described differential amplifier amplifies, and exports given voltage;
Step-down switching regulator, described step-down switching regulator output voltage is to program-controlled resistor;
Program-controlled resistor, described program-controlled resistor regulates the output voltage of step-down switching regulator, and the Darlington transistor connect for differential amplifier is powered.
6. circuit according to claim 1, wherein, described cache module (102) is connected with power module, communication module and main control module respectively.
7. circuit according to claim 1, wherein, described cache module (102) specifically comprises:
First cache module, for preserving the data-signal in write SRAM;
Second cache module, for preserving contrast misdata and address information.
8. circuit according to claim 1, wherein, described communication module (103) is connected with host computer, power module, cache module and main control module respectively.
9. circuit according to claim 1, wherein, described communication module (103) is made up of USB control chip, makes to be communicated by USB interface between host computer with master control borad.
10. circuit according to claim 1, wherein, described main control module (104) is connected with power module, cache module, communication module and level switch module respectively.
11. circuit according to claim 1, wherein, described main control module (104) is made up of FPGA and configuration circuit thereof, for receiving the control signal from host computer, provides Control timing sequence for other each modules normally work.
12. circuit according to claim 1, wherein, described current monitoring module (105) respectively with power module and first interface model calling.
13. circuit according to claim 1, wherein, described current monitoring module (105) specifically comprises:
Sense resistance, for being converted to voltage signal by current signal;
Differential amplifier, amplifies for voltage signal sense resistance be converted to;
High precision analogue conversion chip, is converted to digital signal for the voltage signal after being amplified by differential amplifier and sends into main control module (104).
Relay, by master control module controls, after the digital signal of high precision analogue conversion chip feeding main control module (104) exceedes certain setting value, disconnects described relay, cuts off the electricity supply.
14. circuit according to claim 1, wherein, described level switch module (106) respectively with main control module and first interface model calling.
15. circuit according to claim 1, wherein, described level switch module (106) is made up of multi-disc level transferring chip, for chip under test interface level and FPGA interface level being changed.
16. circuit according to claim 1, wherein, described first interface module (107) is connected, as the signal path between control panel and test board with the second interface module (201) on current monitoring module, level switch module and beta version (200) respectively.
17. circuit according to claim 1, wherein, described second interface module (201) is connected with the first interface module (107) on each test fixture and control panel (100) respectively.
18. circuit according to claim 1, wherein, described test fixture (202) for fixing SRAM to be measured, and is connected with the test point of SRAM to be measured, as the signal path between test board and SRAM to be measured.
19. 1 kinds of multi-mode SRAM single-particle method of testings, the method comprises the following steps:
A) host computer (300) operation interface writes the vector file of test;
B) host computer (300) transmits control signal to main control module (104);
C) host computer (300) is to interior vector file a) write stored in step of cache module (102);
D) main control module (104) test data writes in chip to be measured;
E) data in chip to be measured are read;
F) in main control module (104) FPGA by step e) in data in the chip to be measured that reads and step c) in stored in vector file contrast, if comparing result is inconsistent, then return step a), if unanimously, then continue step g);
G) irradiation apparatus is opened;
H) selected test pattern in host computer, starts test;
I) host computer receives test data, and controls test end.
20. according to step h described in claim 13) in test pattern comprise following three kinds:
Current monitoring pattern under stationary state, in such a mode, current value to be uploaded in host computer by main control module and shows at operation interface by setting-up time;
Current monitoring pattern under continuous WriteMode, in such a mode, main control module writes test data continuously in SRAM to be measured, in the process continuous monitoring chip to be measured current value used, and uploads in host computer and show record;
Data Comparison pattern, in such a mode, main control module constantly reads the data in chip to be measured, and the data of reading and preset data is contrasted, then by misdata stored in cache module.When main control module receives testing end signal, misdata to be imported in host computer and record through communication module, in test process, host computer constantly reads erroneous values and the current value of contrast, and shows.
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