CN105280243A - FPGA-based NOR Flash anti-radiation performance test system - Google Patents
FPGA-based NOR Flash anti-radiation performance test system Download PDFInfo
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- CN105280243A CN105280243A CN201510788950.XA CN201510788950A CN105280243A CN 105280243 A CN105280243 A CN 105280243A CN 201510788950 A CN201510788950 A CN 201510788950A CN 105280243 A CN105280243 A CN 105280243A
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Abstract
The invention discloses an FPGA-based NOR Flash anti-radiation performance test system. The technical problems that an existing test system is low in test efficiency and poor in safety performance are solved. The FPGA-based NOR Flash anti-radiation performance test system comprises an upper computer and a lower computer which are connected through a gigabit Ethernet. The upper computer is used for sending out an operation instruction, carrying out statistics on test result data and displaying test working states. The lower computer comprises a gigabit Ethernet chip used for achieving physical layer data receiving and transmitting, an FPGA control module, a crystal oscillator and a procedure configuration port. The FPGA control module comprises an Ethernet communication module, an instruction analysis module, a chip selection signal module, an address bus driving module, a control bus driving module, a read data caching module and a connection port. According to the FPGA-based NOR Flash anti-radiation performance test system, one or more NOR Flashes can be measured at a time, the upper computer is away from a radiation source, and error occurrence probability data of NOR Flash under the radiation environment can be obtained.
Description
Technical field
The invention belongs to Space Radiation Effects and field of reinforcement, relate to a kind of NORFlash anti-radiation performance test macro based on FPGA, by the ground simulation test to NORFlash anti-radiation performance, the probability data that NORFlash under radiation environment makes a mistake can be obtained.
Background technology
Integrated circuit testing is component part important in IC industrial chain, is applied to the whole process of the production of integrated circuit, in guarantee properties of product, has irreplaceable effect qualitatively.
As the main class of in integrated circuit (IC) products, NORFlash is a kind of erasable and possess the storer of overprogram ability, there is Large Copacity, power down be non-volatile, lightweight, volume is little, the advantage such as shock resistance is good, low-power consumption, more and more adapt to the actual demand of each field of storage.The structure of NORFlash uniqueness and erasable mechanism, its physical imperfection abstract for during functional fault and traditional static RAM SRAM or dynamic RAM DRAM fault be not quite similar.Therefore, the test of NORFlash is different from common special IC, and in memory test field, NORFlash also has testing mechanism and the method for the uniqueness of oneself.
NOR Flash memory is divided into NORFlash and NANDFlash according to the difference of its inner structure, compared to NANDFlash, NORFlash has that reading speed is fast, low in energy consumption, chip address wire pin is independent, the power down not characteristic such as execution technique (XIP) in obliterated data, chip, and NOR Flash memory obtains widespread use at space field in recent years.
High energy charged particles in space environment can bring out NORFlash device generation single particle effect or total dose effect, make it to produce logic error and parafunctional phenomenon, to spacecraft load in-orbit usefulness play and spacecraft in-orbit life cycle bring certain impact.Therefore, the anti-radiation performance of NORFlash has obtained the great attention of this field.The structure of NORFlash and operate all more complicated.NORFlash device is made up of the block of 64 ~ 128KB, and most of action need first carries out erase operation.The erase operation of NORFlash is undertaken by block, so the storage space of each erase operation is 64 ~ 128KB.
Based on the characteristic of NORFlash and it is in the importance ensureing spacecraft flight reappearance in-orbit, the anti-radiation performance of NORFlash device is more and more by the concern of aerospace design teacher.It is general NORFlash test macro that the test macro of the anti-radiation performance parameter of existing NORFlash mainly contains two kinds: the first, and second is special NORFlash test macro.
General NORFlash test macro, because the storage unit made a mistake in irradiation test has randomness, experiment substantially all need to carry out full sheet cover type carry out and the time of erase operation long, make accurately to judge and detect that the difficulty of test of device generation single particle effect and total dose effect is larger, in addition, irradiation all can have an impact with off working state in working order to NORFlash, and the cost of existing general NORFlash test macro is higher.In addition, test experiments will carry out in simulation radiation environment, and irradiation also has impact to electronic test equipment, and test macro is exposed to except in radiation environment except NORFlash to be measured, and other subtest electronic equipments also must carry out Flouride-resistani acid phesphatase shielding.Consider and not easily accomplish the irradiation shielding of existing general large scale system, existing universal test system has been difficult to NORFlash anti-radiation performance test experiments.
Special NORFlash test macro, mainly according to the test environment of irradiation and the test macro of testing requirement exploitation, comprise host computer and slave computer, host computer is for generating steering order and logging test results, slave computer adopts common MCU main control chip, for serial devices, for generation of fixing resolution chart, the chip-count of each test is only a slice, and transfer bus many employings usb bus between host computer and slave computer or RS232 bus, the transmission bandwidth of RS232 is about 20K, transmission range about 15 meters, USB maximum bandwidth is 5G, but transmission range only has 5 meters.Because test is what to carry out under the simulation radiation environment that cost is higher, need test process short as much as possible, the transfer rate of RS232 is difficult to the speed of mating NORFlash operation rate at a high speed and PC simultaneously, and existing special NORFlash test macro is difficult to because testing efficiency is low realize; Due to the close together between host computer and slave computer, in test process, host computer and tester can be subject to the threat of slave computer end irradiation.
Summary of the invention
In order to overcome the defect that above-mentioned prior art exists, the present invention proposes a kind of NORFlash anti-radiation performance test macro based on FPGA, for solving low and because the technical matters of poor stability that closely causes of distance between host computer and slave computer of existing test system and test efficiency.
For achieving the above object, the technical scheme that the present invention takes is:
Based on the NORFlash anti-radiation performance test macro of FPGA, comprise host computer 1 and slave computer 2; Connected by gigabit Ethernet between host computer 1 and slave computer 2; Host computer 1 is for sending operational order, statistical test result data and display test job state; Slave computer 2 comprises gigabit Ethernet chip 21, FPGA control module 22, crystal oscillator 23 and application configuration port 24; Wherein,
Gigabit Ethernet chip 21, for realizing the physical layer data transmitting-receiving of gigabit Ethernet communication between host computer 1 and slave computer 2;
FPGA control module 22 comprises ethernet communication module 221, command analysis module 222, chip selection signal module 223, address bus driver module 224, control bus driver module 225, read data cache module 226 and connectivity port 227; Described ethernet communication module 221 is for completing the procotol of gigabit Ethernet; Command analysis module 222 is for resolving the host computer instruction received by gigabit Ethernet; Chip selection signal module 223 is for generating the chip enable signal of NORFlash to be measured; Address bus driver module 224 is for generating the address signal of the NORFlash to be measured selected; Control bus driver module 225 is for generating the control signal of the NORFlash to be measured selected; Read data cache module 226 is for carrying out buffer memory to the data of the NORFlash to be measured selected read; Connectivity port 227, for realizing the connection of FPGA control module 22 and varying number NORFlash to be measured;
Crystal oscillator 23, for the clock signal providing FPGA control module 22 to work;
Application configuration port 24, for carrying out application configuration to FPGA control module 22.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, the operational order that host computer sends comprises the instruction of User Defined test pattern, this instruction sends to FPGA control module by user in host computer typing, generate the wiping time sequential routine to NORFlash to be measured, or write operation sequential, or read operation sequential, or operated by wiping, the different sequential of write operation, read operation combination in any.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, the instruction of User Defined test pattern comprises frame sign on and the second instruction, wherein, second instruction is made up of six bytes, comprises the ID of NORFlash to be measured, operational order type, instruction sequence, NORFlash block ID, test number (TN) and write data message.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, the default data of writing of write operation is 0x55H.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, comprises positioning instruction with self-defined test pattern instruction, and this positioning instruction is selected by the test quantity of chip enable signal module to NORFlash to be measured.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, test quantity can be a slice or multi-disc.
The above-mentioned NORFlash anti-radiation performance test macro based on FPGA, when test quantity is multi-disc, read operation carries out poll reading to the NORFlash read data cache module of varying number.
The present invention compared with prior art, has the following advantages:
1, the present invention is owing to adopting FPGA as the control module of slave computer, can survey a slice or multi-disc by single, compared with only testing a slice, effectively improve testing efficiency with prior art at every turn.
2, the present invention is due to the data transmission medium employing gigabit Ethernet between host computer and slave computer, and the optimum wideband of transmission reaches 1000M, and message transmission rate is fast, further increasing testing efficiency; Simultaneously, under the prerequisite ensureing data transmission accuracy, transmission range maximumly can reach tens kms based on different physical mediums, high speed and the accurately transmission of test instruction and test data between upper and lower computer can be realized, the distance of test macro host computer and slave computer can be zoomed out, ensure that host computer and tester do not affect by the irradiation of slave computer end, security is better.
3, the present invention is owing to have employed User Defined pattern, the test instruction that the testing requirement that user can be allowed to want according to oneself edits oneself is tested, serve the effect that user upgrades voluntarily, with prior art resolution chart Stationary liquid ratio, there is test pattern advantage flexibly.
Accompanying drawing explanation
Fig. 1 is system architecture schematic diagram of the present invention;
Fig. 2 is connectivity port of the present invention and NORFlash connected mode schematic diagram to be measured;
Fig. 3 is workflow diagram of the present invention;
Fig. 4 is the structural representation of PC control command frame of the present invention;
The structural representation of state acknowledgement frame when Fig. 5 is present system work;
Fig. 6 is the structural representations of present system work hours according to acknowledgement frame.
Embodiment
Below in conjunction with the drawings and specific embodiments, be described in further detail of the present invention:
With reference to Fig. 1, the present invention includes the host computer 1 and slave computer 2 that are connected by gigabit Ethernet; Host computer 1 comprises initialization system order button, elementary instruction button, test instruction button, system connection pilot lamp, test mode display lamp, for sending operational order, statistical test result data and display test job state; Slave computer 2 comprises gigabit Ethernet chip 21, FPGA control module 22, crystal oscillator 23 and application configuration port 24; Wherein,
Gigabit Ethernet chip 21 adopts the 88E1111 chip of Marvell company, is positioned at slave computer foremost, is connected by RJ45 interface with host computer, for realizing the physical layer data transmitting-receiving of gigabit Ethernet communication between host computer 1 and slave computer 2.
FPGA control module 22 adopts the Kintex-7XC7325T-2FFG900CFPGA of 500 pins of Xilinx company, control module comprises ethernet communication module 221, here be mainly connected with 88E1111 chip, jointly complete the Physical layer of gigabit Ethernet, data link layer, network layer and transport layer protocol, namely complete the transmitting-receiving to gigabit Ethernet Frame; Command analysis module 222 is connected with ethernet communication module 221, in order to complete the parsing of the instruction to the host computer received; Chip selection signal module 223 front end is connected with command analysis module 222, and rear end is connected with the chip selection signal input end of connectivity port 227, for producing the chip enable signal of NORFlash to be measured according to the analysis result of command analysis module 222; Address bus driver module 224 front end is connected with command analysis module 222, and rear end is connected with connectivity port 227 address signal input end, for producing the address signal of NORFlash to be measured according to the analysis result of command analysis module 222; Control bus driver module 225 front end is connected with command analysis module 222, and rear end is connected with the control signal input end of connectivity port 227, for producing the control signal of NORFlash to be measured according to the analysis result of command analysis module 222; Read data cache module 226 front end is connected with command analysis module 222 and ethernet communication module 221, rear end is connected with the reading data signal output terminal of connectivity port 227, for producing the read signal of NORFlash to be measured according to the analysis result of command analysis module 222 and sending to host computer reading after data result carries out buffer memory by ethernet communication module 221; Front end, connectivity port 227 is connected with chip selection signal module 223, address bus driver module 224, control bus driver module 225, read data cache module 226, facilitate the connection of FPGA control module 22 and NORFlash to be measured, this connectivity port 227 and NORFlash connected mode to be measured are as shown in Figure 2.
Crystal oscillator 23, is made up of jointly 25MHz crystal oscillator and clock chip ICS844021, and the clock signal input terminal pin through FPGA is connected, for the clock signal providing FPGA control module 22 to work.
Application configuration port 24, adopt jtag interface, clock input signal TCK, test data output signal TDO, test pattern select input signal TMS and serial test data input signal TDI pin to be connected with FPGA, for carrying out the configuration of JTAG model program to FPGA control module 22 after tested.
With reference to Fig. 2, the present invention adopts four identical connectivity ports, the transmission mode selection signal BYTE of the FPGA control module in each connectivity port, address output signal A0-A19, data export input signal DQ0-DQ15, write Enable Pin WE, condition indicative signal R/B and reset signal RESET successively with the transmission mode selection signal BYTE ' of NORFlash to be measured, address output signal A0 '-A19 ', data export input signal DQ0 '-DQ15 ', write Enable Pin WE ', condition indicative signal R/B ' and reset signal RESET ' is connected successively, the chip selection signal CE ' that the chip selection signal CE that FPGA control module generates according to host computer instruction is corresponding with NORFlash to be measured is connected.
The transmission mode selection signal BYTE of FPGA control module and NORFlash to be measured, address output signal A0-A19, data export input signal DQ0-DQ15, write Enable Pin WE, chip selection signal CE, condition indicative signal R/B and reset signal RESET are uni-directional signal interface, and it is bi-directional data interface that data export input signal DQ0-DQ15.
Host computer is divided into four parts: a part sends the concrete operations instruction to NORFlash test macro; Part II carries out real-time state monitoring display to the test process of NORFlash test macro; Part III is raw test experiments report automatically; Part IV is testing progress instruction and experimental result early warning instruction.
With reference to Fig. 3, workflow of the present invention, comprises the following steps:
Step one, connects host computer and slave computer, configures test macro program.NORFlash to be measured be installed to the connectivity port of test macro and whole system be placed in the laboratory that will occur to simulate irradiation.
Here, after upper and lower computer connects, open test macro power supply, JTAG configuration testing system operation programs.Described is that 4 NORFlash to be measured are received connectivity port simultaneously.
Step 2, host computer sends and connects slave computer instruction, if master system connects pilot lamp present blink states, whole system successful connection is described, can carries out next step normal running.
Step 3, opens radiation source and carries out irradiation to NORFlash to be measured.
Step 4, host computer carries out test pattern selection according to testing requirement, and sends corresponding test pattern instruction to slave computer.
Here, concrete test pattern and its command frame structure are with reference to Fig. 4.
Step 5, slave computer receives host computer instruction by gigabit Ethernet, resolves instruction, and performs corresponding operation, in real time duty and test result is fed back to host computer.
Here concrete operations comprise: carry out operating sheet choosing by the NORFlashID in instruction to chip to be measured, according to the number of times of test number (TN) setting test loop, according to the initial address of corresponding Sector value generating run chip, finally address bus driver block and data bus is coordinated to generate the drive singal of corresponding NORFlash to be measured according to instruction type and instruction sequence by chip selection signal module, control bus driver module.
Duty feedback comprises: if not read operation, feedback information is state acknowledgement frame, and this state acknowledgement frame structure is with reference to Fig. 5, and feedback information comprises ID, the operation commencing signal of test NORFlash, operation end signal; If read operation, its feedback, except the state acknowledgement frame comprising read operation, also comprises data answering frame, data answering frame structure with reference to Fig. 6, feedack comprise read NORFlash ID, read commencing signal, the data read.
Step 6, host computer is resolved according to the feedback signal of slave computer and test result data, carries out state, progress, mistake early warning instruction and laboratory report generation according to resolving content.
Here comprise: the light on and off driving corresponding operating status indicator lamp according to the operation commencing signal in feedback signal and operation end signal, if the return data read, tempo instructions is carried out according to the data address returned, indicate according to the early warning that misdata proportion carries out in various degree, laboratory report file is set up according to the ID of NORFlash, after read data starts, file starts to deposit the data value of reading and its specific address in NORFlash, if it is identical with write data to read data, then think correct data, otherwise be misdata, and be numbered for misdata, after experiment terminates, the data count that file statistics reads, correct data number, misdata number and misdata ratio.
Step 7, judges current test, if desired continues test, returns step 4.Otherwise, enter step 8.
Step 8, closes radiation source, whole off-test.
With reference to Fig. 4, in the structure of PC control command frame, 0xFF is instruction frame head, NORFlashID is for pointing out which sheet the NORFlash that will test is, " instruction type ", " instruction sequence " test operating procedure that composition is concrete jointly, " address " carries out operating block selection to a slice NORFlash, and occurrence gives " Sector ", and input default value is not full wafer NORFlash." experiment number " text box input value is to " experiment number " in instruction, and input default value is not for once to test." write data " text box input value is to " the writing data " in instruction, and input default value is not 0x55H.
With reference to Fig. 5, in the structure of slave computer state acknowledgement frame, 0xFF is preamble sequence, and NORFlashID is for pointing out which sheet the NORFlash that will test is, " instruction type " represents current operation status.
With reference to Fig. 6, in the structure of slave computer data answering frame, 0xXX is preamble sequence, X is NORFlashID value, " start address " represents the NORFlash memory address state in this Frame corresponding to data field first byte, " data " represent data payload in this Frame, are that the NORFlash read stores content.
The present invention includes but be not limited to above embodiment, every any equivalent replacement of carrying out under the principle of spirit of the present invention or local improvement, all will be considered as within protection scope of the present invention.
Claims (7)
1. the NORFlash anti-radiation performance test macro based on FPGA, comprise host computer (1) and slave computer (2), it is characterized in that: connected by gigabit Ethernet between described host computer (1) and slave computer (2); Described host computer (1) is for sending operational order, statistical test result data and display test job state; Described slave computer (2) comprises gigabit Ethernet chip (21), FPGA control module (22), crystal oscillator (23) and application configuration port (24); Wherein,
Gigabit Ethernet chip (21), for realizing the physical layer data transmitting-receiving of gigabit Ethernet communication between host computer (1) and slave computer (2);
FPGA control module (22) comprises ethernet communication module (221), command analysis module (222), chip selection signal module (223), address bus driver module (224), control bus driver module (225), read data cache module (226) and connectivity port (227); Described ethernet communication module (221) is for completing the procotol of gigabit Ethernet; Described command analysis module (222) is for resolving the host computer instruction received by gigabit Ethernet; Described chip selection signal module (223) is for providing the chip enable signal of NORFlash to be measured; Described address bus driver module (224) is for generating the address signal of the NORFlash to be measured selected; Described control bus driver module (225) is for generating the control signal of the NORFlash to be measured selected; Described read data cache module (226) is for carrying out buffer memory to the data of the NORFlash to be measured selected read; Connectivity port (227), for realizing the connection of FPGA control module (22) and varying number NORFlash to be measured;
Crystal oscillator (23), for providing the FPGA control module clock signal that (22) work;
Application configuration port (24), for carrying out application configuration to FPGA control module (22).
2. the NORFlash anti-radiation performance test macro based on FPGA according to claim 1, it is characterized in that, described operational order comprises the instruction of User Defined test pattern, this instruction sends to FPGA control module (22) by user in host computer typing, generate the wiping time sequential routine to NORFlash to be measured, or write operation sequential, or read operation sequential, or operated by wiping, the different sequential of write operation, read operation combination in any.
3. the NORFlash anti-radiation performance test macro based on FPGA according to claim 2, it is characterized in that, the instruction of described User Defined test pattern comprises frame sign on and the second instruction, wherein, second instruction is made up of six bytes, comprises the ID of NORFlash to be measured, operational order type, instruction sequence, Flash block ID, test number (TN) and write data message.
4. the NORFlash anti-radiation performance test macro based on FPGA according to claim 2, is characterized in that, the default data of writing in described write operation sequential is 0x55H.
5. the NORFlash anti-radiation performance test macro based on FPGA according to claim 2, it is characterized in that, the instruction of described User Defined test pattern comprises positioning instruction, and this positioning instruction is selected by the test quantity of chip selection signal module (223) to NORFlash to be measured.
6. the NORFlash anti-radiation performance test macro based on FPGA according to claim 5, is characterized in that, described test quantity can be a slice or multi-disc.
7. the NORFlash anti-radiation performance test macro based on FPGA according to claim 6, it is characterized in that, when described test quantity is multi-disc, read operation is that the read data cache module (226) corresponding to the NORFlash to be measured chosen by chip selection signal module (223) carries out poll reading.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771984A (en) * | 2017-02-20 | 2017-05-31 | 华东师范大学 | A kind of high speed circuit board intelligent test device |
| CN107478925A (en) * | 2017-07-12 | 2017-12-15 | 芯海科技（深圳）股份有限公司 | A kind of touch key-press test system and method based on ATMEL |
| CN112198862A (en) * | 2020-09-18 | 2021-01-08 | 中国辐射防护研究院 | On-line experimental test system for total dose effect of extensible microcontroller |
| CN112582015A (en) * | 2020-12-30 | 2021-03-30 | 普冉半导体(上海)股份有限公司 | Method and system for NOR Flash reliability test |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030237032A1 (en) * | 2002-03-22 | 2003-12-25 | Frank Adler | Method for electronically testing memory modules |
| CN102332311A (en) * | 2011-10-18 | 2012-01-25 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
| CN204330921U (en) * | 2014-12-19 | 2015-05-13 | 中国电子科技集团公司第四十七研究所 | Steric effect breadboard and pilot system |
-
2015
- 2015-11-17 CN CN201510788950.XA patent/CN105280243A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030237032A1 (en) * | 2002-03-22 | 2003-12-25 | Frank Adler | Method for electronically testing memory modules |
| CN102332311A (en) * | 2011-10-18 | 2012-01-25 | 中国航天科技集团公司第五研究院第五一〇研究所 | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device |
| CN204330921U (en) * | 2014-12-19 | 2015-05-13 | 中国电子科技集团公司第四十七研究所 | Steric effect breadboard and pilot system |
Non-Patent Citations (1)
| Title |
|---|
| 盛江坤等: "NAND Flash存储器总剂量效应测试技术研究", 《中国核科学技术进展报告》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771984A (en) * | 2017-02-20 | 2017-05-31 | 华东师范大学 | A kind of high speed circuit board intelligent test device |
| CN107478925A (en) * | 2017-07-12 | 2017-12-15 | 芯海科技（深圳）股份有限公司 | A kind of touch key-press test system and method based on ATMEL |
| CN112198862A (en) * | 2020-09-18 | 2021-01-08 | 中国辐射防护研究院 | On-line experimental test system for total dose effect of extensible microcontroller |
| CN112198862B (en) * | 2020-09-18 | 2022-01-18 | 中国辐射防护研究院 | On-line experimental test system for total dose effect of extensible microcontroller |
| CN112582015A (en) * | 2020-12-30 | 2021-03-30 | 普冉半导体(上海)股份有限公司 | Method and system for NOR Flash reliability test |
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