CN204330921U - Steric effect breadboard and pilot system - Google Patents
Steric effect breadboard and pilot system Download PDFInfo
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- CN204330921U CN204330921U CN201420821510.0U CN201420821510U CN204330921U CN 204330921 U CN204330921 U CN 204330921U CN 201420821510 U CN201420821510 U CN 201420821510U CN 204330921 U CN204330921 U CN 204330921U
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Abstract
The application provides a kind of steric effect breadboard and pilot system, steric effect breadboard, comprise processor, with the control module of described relational processor, the detection module associated with described control module, and the adapter for carrying Flash type FPGA device to associate with described control module with described detection module, processor sends corresponding test signal according to the instruction of main control unit to described control module, control module is according to the Flash type FPGA device of this test signal excitation adapter carrying, and control output current information/logic coding that detection module obtains the Flash type FPGA device of adapter carrying, current information/the logic coding got is transferred to processor by detection module, and feed back to main control unit after treated device process.In addition, disclosed herein as well is a kind of steric effect pilot system.It can record tested Flash type FPGA device exactly and when there occurs single event latch-up or single-particle inversion.Testing crew can be helped effectively to assess the performance of tested Flash type FPGA device.
Description
Technical field
The utility model relates to semiconductor applications, particularly a kind of steric effect breadboard and pilot system.
Background technology
FPGA (field programmable gate array) is the important tool extensively adopted in modern communication technology, electronic technology, computer technology, automatic technology, in space flight integrated circuit, occupy critical role, it is mainly divided into three kinds, anti-fuse type, SRAM type and Flash type.The programmable unit of Flash type FPGA is Flash storage unit, utilizes the floating boom in transistor to store programming information.Without the need to additional PROM when Flash type FPGA uses, power-on time is also very short, and Flash is not easy to occur single-particle inversion compared to SRAM in addition, and therefore Flash type FPGA is well suited for AEROSPACE APPLICATION.
Flash type FPGA before for space system, don't fail to carry out sufficient steric effect test assessment to it.At present, the method that the output that the test of device level steric effect is typically employed in irradiation device and non-irradiation device under same test signal is compared, judges single particle effect by the difference comparing Output rusults.Relatively means adopt outside monitoring or manual operations usually, namely under steric effect environment on breadboard the mode of external logic analyser, oscillograph and reometer, irradiation device and non-irradiation device are observed, when irradiation device generation single event latch-up, single-particle inversion, record output current information and logic coding, and manually cut off the electricity supply.But conventional test methods is adopted to Flash type FPGA, utilizes oscillograph can only observe the logic of peripheral interface, limited to the observing capacity of internal element upset, effectively cannot evaluate the number of times of single-particle inversion, realize complicated and not easily debug.Therefore Flash type FPGA is in classic method test, and irradiation device and non-irradiation device can not be adopted to export the method for comparison.
Utility model content
In view of problems of the prior art, the utility model provides a kind of steric effect breadboard, can be connected with main control unit, comprise processor, with the control module of described relational processor, the detection module associated with described control module, and the adapter for carrying Flash type FPGA device to associate with described control module with described detection module, wherein, described processor sends corresponding test signal according to the instruction of described main control unit to described control module, the Flash type FPGA device that described control module encourages described adapter to carry according to this test signal, and control output current information/logic coding that described detection module obtains the Flash type FPGA device of described adapter carrying, current information/the logic coding got is transferred to described processor by described detection module, and described main control unit is fed back to after described processor process.
Interrelated between the module of the steric effect breadboard that the utility model provides, the external main control computer of network can be passed through, thus detection logic coding is stored, analyzes contrast and show in real time, overcome the logic that can only observe peripheral interface in routine techniques, limited to the observing capacity of internal element upset, effectively cannot evaluate the number of times of single-particle inversion, realize the complicated and not easily defect such as debugging.
In embodiments more of the present utility model, comprise and being arranged between described processor and described main control unit for the communication module of signal/transmission and the power module for each module for power supply.
In embodiments more of the present utility model, described adapter is arranged at the centre position of the first half of described breadboard.
In embodiments more of the present utility model, described processor is arranged at the centre position of the latter half of described breadboard.
In embodiments more of the present utility model, described processor is ARM.
The utility model additionally provides a kind of steric effect pilot system, comprise main control unit, the comparing unit associated with described main control unit, with two breadboards, wherein, first breadboard is positioned at radiation environment, second breadboard is positioned at outside radiation environment, described main control unit receives the second output current information/logic coding of the first output current information/logic coding of the processor feedback of described first breadboard and the processor feedback of described second breadboard, and sends it to described comparing unit and compare process.
Utilize system of the present utility model, can test Flash type FPGA device space effect, this method of testing such as comprises: tested Flash type FPGA device is positioned over the first breadboard by a., is positioned over the second breadboard with reference to Flash type FPGA device; B. main control unit sends instruction to the first breadboard and the second breadboard, and described first breadboard and described second breadboard are started working simultaneously; C. single particle radiation is carried out to described first breadboard, send it back described main control unit by the first output current information/logic coding of tested Flash type FPGA device with reference to the second output current information/logic coding of Flash type FPGA device, described main control unit is to described first output current information/logic coding and described second output current information/logic coding real-time storage and send to described comparing unit to be analyzed; D. when described first output current information exceed described second output current information there is transition time, described comparing unit judges that single event latch-up appears in described tested Flash type FPGA device, when described first output logic coding is encoded inconsistent with described second output logic, described comparing unit judges described tested Flash type FPGA device generation single-particle inversion.
Utilize above-mentioned method of testing, can monitor and contrast the output current information/logic coding of two breadboards in real time, record tested Flash type FPGA device exactly and when there occurs single event latch-up or single-particle inversion.Testing crew can be helped effectively to assess the performance of tested Flash type FPGA device.
In addition, this method of testing also can comprise the step a1 between described step a and b: described main control unit sends instruction by arm processor to the first breadboard, and the output current information/logic coding recording tested Flash type FPGA device is the output current information/logic coding that prestores; And in described steps d, described comparing unit is utilized to be contrasted with described second output current information, the current information that prestores respectively by described first output current information, when described first output current information exceeds described second output current information and the current information that prestores occurs transition, described comparing unit judges that single event latch-up appears in described tested Flash type FPGA device; Described comparing unit is utilized to be contrasted with described second output logic coding, the logic coding that prestores respectively by described first output logic coding, when described first output logic coding and described second output logic encode and prestores logic coding all inconsistent time, the described tested Flash type FPGA device generation single-particle inversion of described comparing unit judgement.For avoiding occurring abnormal with reference to Flash type FPGA devices function in steric effect process of the test, output current information/the logic coding of tested Flash type FPGA device is prestored in main control unit, and the output current information/logic coding of the tested Flash type FPGA device under irradiation behaviour in process of the test is contrasted with reference to the output current information/logic coding of Flash type FPGA device and the current information/logic coding that prestores, thus judge whether it there occurs single-particle inversion or single event latch-up, add the reliability of test.
Advantageously, this method of testing also comprises the step between described step b and c: utilize described comparing unit the output current information/logic coding of Flash type FPGA device tested on described first breadboard and the described output current information/logic coding that prestores to be contrasted, judge output current information/logic coding whether in allowed band, when in allowed band, enter step c, when exceeding allowed band, return step a1.
In order to avoid the tested Flash type FPGA device output current information/logic coding prestored exists mistake, therefore proving program is devised, when tested Flash type FPGA device output current information/logic coding actual before finding steric effect test has relatively large deviation with the tested Flash type FPGA device output current information/logic coding prestored, automatically data are carried out storage and cover.
Accompanying drawing explanation
Fig. 1 is the breadboard of the utility model one embodiment and the scheme of installation of main control computer and programmable power supply;
Fig. 2 is each parts annexation schematic diagram of the breadboard of the utility model one embodiment;
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described, should be appreciated that specific embodiment described herein only for understanding the utility model, and be not used in restriction the utility model.
As shown in Figure 1, when utilizing steric effect breadboard of the present utility model to carry out irradiation test, need two breadboards to be placed in respectively in radiation environment with outside radiation environment.And be connected with main control computer and programmable power supply respectively.Wherein, two pieces of breadboards are all connected main control computer by router with programmable power supply, and main control computer controls programmable power supply and provides operating voltage or power-off to breadboard.Router composition data transmission channel, realizes the communication of main control computer and breadboard by ICP/IP protocol, and the high-speed transfer of data.
As shown in Figure 2, the breadboard in the utility model one embodiment comprises power module, arm processor, communication module, control module, detection module, Flash type FPGA adapter.
Wherein, power module is connected with programmable power supply, for module each on breadboard provides operating voltage, and receives control module instruction, powers to the device being fixed on the carrying of Flash type FPGA adapter.
Communication module is for supporting the communication of arm processor and main control computer.Arm processor obtains steering order deliver to control module by communication block from main control computer, also can send by communication module the detection data that detection module obtains to main control computer simultaneously.
The address code that control module inputs to it according to the arm processor received, order code carry out decoding, tested Flash type FPGA device to the carrying of Flash type FPGA adapter exports test signal, and controls the output current information/logic coding of detection module to tested Flash type FPGA device and detect.
Output current information/the logic coding of detection module to tested Flash type FPGA device detects, and sends arm processor to detecting data.
Flash type FPGA adapter can carry tested Flash type FPGA device easily.
Lower mask body introduces the course of work of the utility model steric effect test platform.
(1) main control computer provides power supply to the first breadboard and the second breadboard by controlling programmable power supply simultaneously, completes and powers on.First breadboard carries tested Flash type FPGA device, the second breadboard carries with reference to Flash type FPGA device.
(2), after powering on, on two pieces of breadboards, each module all enters duty, and arm processor completes program initialization, and with main control computer set up network linking by communication module.Main control computer can access arm processor by network, to arm processor sending controling instruction, also can receive the data that arm processor is beamed back by the high speed data transfer passage set up.
(3) the tested Flash type FPGA device that the high speed communication passage that main control computer passes through to have set up is fixed on two pieces of breadboards and reference Flash type FPGA device send identical instruction, detection module detects the output current information/logic coding with reference to Flash type FPGA device, and the detection of gained current information/logic coding is sent to main control computer via communication module and arm processor, the detection of gained current information/logic coding and the conventional output current information/logic coding with reference to Flash type FPGA device prestored contrast by main control computer, check that whether output current information/logic coding is correct.
Simultaneously, detection module detects the output current information/logic coding of tested Flash type FPGA device, and obtained detection current information/logic volume is sent to main control computer via communication module and arm processor, conventional output current information/the logic coding of the detection of gained current information/logic coding with the tested Flash type FPGA device prestored contrasts by main control computer, checks that whether output current information/logic coding is correct.
If two numerical value are all correct, then enter next step.If through repeatedly testing, output current information/the logic coding of tested Flash type FPGA device does not still meet its conventional output current information/logic coding prestored, then utilize this current information/logic coding to replace the tested Flash type FPGA device current information/logic coding prestored.Equally, if through repeatedly testing, its conventional output current information/logic coding prestored still is not met, then the reference Flash type FPGA device output current information/logic coding utilizing output current information/logic coding replacement to prestore with reference to Flash type FPGA device output current information/logic coding.
(4) carry out single particle radiation to the first breadboard, main control computer sends same instructions by the high speed communication passage set up to two pieces of breadboards, and the first breadboard and the second breadboard are started working simultaneously.
(5) detection module detects the output current information/logic coding of tested Flash type FPGA device in irradiation process, and feeds back to main control computer by the communication channel set up, and main control computer shows in real time after receiving data and records deposit; Detection module detects the output current information/logic coding with reference to Flash type FPGA device simultaneously, and feeds back to main control computer by the communication channel set up, and main control computer shows in real time after receiving data and records deposit.
(6) the two contrasts by main control computer, when the big current phenomenon of transition appears in the output current information of tested Flash type FPGA device compared with the output current information with reference to Flash type FPGA device, can determine that now single event latch-up appears in tested Flash type FPGA device.When the output logic coding of tested Flash type FPGA device is encoded inconsistent with the output logic with reference to Flash type FPGA device, can determine that now single-particle inversion appears in this Flash type FPGA device.
In this step, a kind of preferred judge tested Flash type FPGA device whether occur the scheme of single event latch-up as:
The output current information (CC0) that the output current information (CC1) of the reference Flash type FPGA device detected by detection module prestores with it contrasts, to confirm to be in normal operating conditions with reference to Flash type FPGA device;
The output current information (CC1) with reference to Flash type FPGA device that the output current information (TC0) that the output current information (TC1) of the tested Flash type FPGA device detected by detection module prestores with it and above-mentioned detection module detect contrasts respectively, when there is the big current phenomenon of transition, can determine that now single event latch-up appears in tested Flash type FPGA device.
A kind of preferred judge tested Flash type FPGA device whether occur the scheme of single-particle inversion as:
Output logic coding (CD0) that output logic coding (CD1) of the reference Flash type FPGA device detected by detection module prestores with it contrasts, to confirm to be in normal operating conditions with reference to Flash type FPGA device;
Output logic coding (TD0) that output logic coding (TD1) of the tested Flash type FPGA device detected by detection module prestores with it and the output logic with reference to Flash type FPGA device that above-mentioned detection module detects encode (CD1) when carrying out respectively contrasting all inconsistent, can determine that now single-particle inversion appears in tested Flash type FPGA device.
(7) when there is single event latch-up and/or single-particle inversion, main control computer controls the power supply of programmable power supply cut-out to breadboard, terminates test.
In addition, this steric effect breadboard adopts four laminate designs.Carry out large area paving copper at breadboard top layer and bottom, and paving copper is connected to ground together.So not only can shield the interference of high-frequency signal, also make breadboard operationally can dispel the heat quickly.
Tested Flash type FPGA adapter is placed on the center of steric effect breadboard the first half, because need to be subject to single particle radiation and away from other devices and module.Arm processor is the control core of whole steric effect breadboard, therefore arm processor is placed on the center of breadboard the latter half, and the line between other functional units is radiation substantially, decreases the situation that line is interlaced.VDD-to-VSS wiring live width is set to 35mil, and other wire live widths are set to 12mil.Spacing is all greater than 10mil, all adopts hand layouts, ensures live width, line-spacing and cloth admittance line.
The utility model realizes the control to steric effect breadboard by main control computer, can detect the breadboard be placed in radiation environment and the breadboard be placed in outside radiation environment simultaneously, and testing result is carried out analyzing and processing, storage and comparison.Breadboard interface is complete, and position of components is rationally distributed, has the advantages such as easy to use, dependable performance, meets Flash type FPGA steric effect test demand to greatest extent.
Above various embodiment of the present utility model is described in detail.It will be understood by those skilled in the art that and when not departing from the utility model scope (being limited by the accompanying claims), various amendment, change and change can be carried out to embodiment.Should explain from entirety the explanation of right and meet and consistent most wide region is described, being not limited to example or the enforcement example in describing in detail.
Claims (6)
1. a steric effect breadboard, can be connected with main control unit, it is characterized in that, comprise:
Processor;
With the control module of described relational processor;
The detection module associated with described control module; And
The adapter for carrying Flash type FPGA device associated with described control module with described detection module;
Wherein, described processor sends corresponding test signal according to the instruction of described main control unit to described control module, the Flash type FPGA device that described control module encourages described adapter to carry according to this test signal, and control output current information/logic coding that described detection module obtains the Flash type FPGA device of described adapter carrying, current information/the logic coding got is transferred to described processor by described detection module, and feeds back to described main control unit after described processor process.
2. steric effect breadboard according to claim 1, is characterized in that, comprising:
To be arranged between described processor and described main control unit for the communication module of signal/data transmission and;
For the power module of each module for power supply.
3. steric effect breadboard according to claim 1, is characterized in that, described adapter is arranged at the centre position of the first half of described breadboard.
4. steric effect breadboard according to claim 3, is characterized in that, described processor is arranged at the centre position of the latter half of described breadboard.
5. steric effect breadboard according to claim 1, is characterized in that, described processor is ARM.
6. a steric effect pilot system, comprises
Main control unit;
The comparing unit associated with described main control unit; With
Two breadboards according to any one of claim 1-5,
Wherein, first breadboard is positioned at radiation environment, second breadboard is positioned at outside radiation environment, described main control unit receives the second output current information/logic coding of the first output current information/logic coding of the processor feedback of described first breadboard and the processor feedback of described second breadboard, and sends it to described comparing unit and compare process.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420821510.0U CN204330921U (en) | 2014-12-19 | 2014-12-19 | Steric effect breadboard and pilot system |
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| CN201420821510.0U CN204330921U (en) | 2014-12-19 | 2014-12-19 | Steric effect breadboard and pilot system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483574A (en) * | 2014-12-19 | 2015-04-01 | 中国电子科技集团公司第四十七研究所 | Space effect test board, test system and method for testing device space effect |
| CN105280243A (en) * | 2015-11-17 | 2016-01-27 | 西安电子科技大学 | FPGA-based NOR Flash anti-radiation performance test system |
-
2014
- 2014-12-19 CN CN201420821510.0U patent/CN204330921U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483574A (en) * | 2014-12-19 | 2015-04-01 | 中国电子科技集团公司第四十七研究所 | Space effect test board, test system and method for testing device space effect |
| CN104483574B (en) * | 2014-12-19 | 2017-06-06 | 中国电子科技集团公司第四十七研究所 | The method of three-dimensional effect pilot system and test device three-dimensional effect |
| CN105280243A (en) * | 2015-11-17 | 2016-01-27 | 西安电子科技大学 | FPGA-based NOR Flash anti-radiation performance test system |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20150513 Effective date of abandoning: 20170606 |
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| AV01 | Patent right actively abandoned |