CN106919748B - Device and method for improving FPGA prototype verification efficiency - Google Patents
Device and method for improving FPGA prototype verification efficiency Download PDFInfo
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- CN106919748B CN106919748B CN201710103775.5A CN201710103775A CN106919748B CN 106919748 B CN106919748 B CN 106919748B CN 201710103775 A CN201710103775 A CN 201710103775A CN 106919748 B CN106919748 B CN 106919748B
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- 238000012795 verification Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000002159 abnormal effect Effects 0.000 claims abstract description 47
- 230000005540 biological transmission Effects 0.000 claims abstract description 44
- 238000012544 monitoring process Methods 0.000 claims abstract description 15
- 238000013461 design Methods 0.000 abstract description 12
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The invention relates to the technical field of chip prototype verification, in particular to a device and a method for improving the FPGA prototype verification efficiency. The invention discloses a device for improving the verification efficiency of an FPGA prototype, which comprises: a monitoring unit, the monitoring unit further comprising: the device comprises a monitored message storage unit, a transmission message receiving unit, a triggering judgment unit and an abnormal result sending unit, wherein: the monitored message storage unit is used for storing the content of the monitored message; the transmission message receiving unit is used for receiving and reading a transmission message from the NC chip; and the triggering judgment unit is used for comparing whether the content of the transmission message is consistent with the content of the monitored message. The invention also discloses a method for improving the verification efficiency of the FPGA prototype. The invention can help chip design departments to quickly analyze and locate problems, and greatly improves the verification efficiency of the FPGA prototype platform.
Description
Technical Field
The invention relates to the technical field of chip prototype verification, in particular to a device and a method for improving the FPGA prototype verification efficiency.
Background
A large amount of professional verification work is needed from chip design to chip production, once verification is incomplete, problems may exist in the chip, and the problems cannot be compensated after chip production. In order to better verify the design of a chip, an FPGA prototype platform is usually constructed for verification, and by verifying the correctness of the chip function of a Node Controller (NC) in a real environment, the defect that soft simulation cannot be completely and quickly verified can be overcome. The validity verification is carried out on the system design, on one hand, the usability and the realizability of a multi-channel computer are verified, and the design and debugging, the mechanical structure and the heat dissipation validity verification of the high-speed interface hardware PCB are verified; on the other hand, Firmware (Firmware) and operating system software are developed and debugged early. Meanwhile, the system performance is evaluated, the performance bottleneck is found, the hardware structure planning, the NC logic design and the system software performance are guided to be optimized, and the system performance is predicted and analyzed to a certain degree. However, the complexity of chip design is often high, the problems involved in the verification process are complex and wide, and positioning is difficult when problems occur. Therefore, the method for positioning problems in the debugging process is particularly important.
Disclosure of Invention
Aiming at the technical problems, the invention aims to provide a device and a method for improving the verification efficiency of an FPGA prototype, which can help a chip design department to quickly analyze and locate the problems and greatly improve the verification efficiency of the FPGA prototype platform.
In order to achieve the purpose, the invention is realized by the following technical scheme:
the invention provides a device for improving the verification efficiency of an FPGA prototype, which comprises: a monitoring unit, the monitoring unit further comprising: the device comprises a monitored message storage unit, a transmission message receiving unit, a triggering judgment unit and an abnormal result sending unit, wherein:
the monitored message storage unit is used for storing the content of the monitored message;
the transmission message receiving unit is used for receiving and reading a transmission message from the NC chip;
the trigger judging unit is used for comparing whether the content of the transmission message is consistent with the content of the monitored message, if so, the NC chip is abnormal, the trigger judging unit enters a pause state and sends the information of the abnormal chip to the abnormal result sending unit, and the abnormal result sending unit sends the abnormal result to the external analysis equipment; if not, the NC chip is normal, and the transmission message receiving unit returns to continue receiving and reading the transmission message from the NC chip.
Further, the system also comprises a result analysis unit which is used for analyzing the abnormal NC chip through an external analysis device.
Further, the transmission message receiving unit is located between the monitored message storage unit and the trigger judgment unit.
Further, the trigger judgment unit is located between the transmission message receiving unit and the abnormal result sending unit.
The invention also provides a method for improving the verification efficiency of the FPGA prototype based on the device for improving the verification efficiency of the FPGA prototype, which comprises the following steps:
step 1: adding a monitoring unit in the FPGA prototype verification platform, wherein the monitoring unit further comprises: the device comprises a monitored message storage unit, a transmission message receiving unit, a trigger judging unit and an abnormal result sending unit;
step 2: storing the content of the monitored message to a monitored message storage unit;
and step 3: a transmission message receiving unit receives and reads a transmission message from an NC chip;
and 4, step 4: the trigger judging unit compares whether the content of the transmission message is consistent with the content of the monitored message, if so, the NC chip is abnormal, the trigger judging unit enters a pause state and sends the information of the abnormal chip to the abnormal result sending unit, and the abnormal result sending unit sends the abnormal result to the external analysis equipment; if not, the NC chip is normal, and the step 3 is returned to continue receiving and reading the transmission message from the NC chip.
Further, after the step 4, the method further comprises the following steps: and analyzing the abnormal NC chip by an external analysis device.
Compared with the prior art, the device for improving the verification efficiency of the FPGA prototype has the following beneficial effects: the invention adds the monitoring unit in the FPGA prototype verification platform, judges whether the NC chip is normal or not by comparing and analyzing whether the content of the transmission message is consistent with the content of the monitored message or not, and sends the abnormal result to the external analysis equipment for analysis, thereby helping a chip design department to quickly analyze and locate the problem and greatly improving the verification efficiency of the FPGA prototype platform;
the beneficial effects of the method for improving the verification efficiency of the FPGA prototype are similar to those of the device for improving the verification efficiency of the FPGA prototype, and are not described herein again.
Drawings
Fig. 1 is a schematic structural diagram of the apparatus for improving the verification efficiency of the FPGA prototype according to the present invention.
Fig. 2 is a schematic flow chart of the method for improving the verification efficiency of the FPGA prototype according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms and concepts appearing in the following examples are explained below:
FPGA: the English is called Field-Programmable Gate Array, i.e. Field Programmable Gate Array, which is a product developed further on the basis of Programmable devices such as PAL, GAL, CPLD, etc. The internal part comprises three parts of a configurable Logic module CLB (configurable Logic Block), an input Output module IOB (input Output Block) and an internal connection (Interconnect).
Verifying an FPGA prototype: the design is directly burned into a chip, the chip is placed in a test system or application system development environment, the correctness of the chip design can be verified through actual test and application, and errors can be diagnosed.
The following describes a device and a method for improving the verification efficiency of an FPGA prototype in conjunction with the accompanying drawings and the following embodiments:
example 1
Referring to fig. 1, an apparatus for improving the verification efficiency of an FPGA prototype includes: a monitoring unit, the monitoring unit further comprising: a monitored message storage unit 101, a transmission message receiving unit 102, a trigger judging unit 103 and an abnormal result sending unit 104, wherein:
the monitored message storage unit 101 is configured to store the content of the monitored message;
the transmission message receiving unit 102 is configured to receive and read a transmission message from an NC chip;
the trigger judging unit 103 is configured to compare whether the content of the transmission packet is consistent with the content of the monitored packet, if so, the NC chip is abnormal, the trigger judging unit 103 enters a suspended state, and sends information of an abnormal chip to the abnormal result sending unit 104, and the abnormal result sending unit 104 sends an abnormal result to an external analysis device; if not, the NC chip is normal, and the return transmission message receiving unit 102 continues to receive and read the transmission message from the NC chip.
The apparatus further includes a result analyzing unit 105 for analyzing the abnormal NC chip by an external analyzing device.
The transmission message receiving unit 102 is located between the monitored message storage unit 101 and the trigger judgment unit 103. The trigger judgment unit 103 is located between the transmission message receiving unit 102 and the abnormal result sending unit 104.
The external analysis device is a computer or an oscilloscope.
Example 2
Referring to fig. 2, a method for improving the verification efficiency of an FPGA prototype includes the following steps:
step 201: adding a monitoring unit in an FPGA prototype verification platform, wherein the monitoring unit comprises: the device comprises a monitored message storage unit, a transmission message receiving unit, a trigger judging unit and an abnormal result sending unit;
step 202: storing the content of the monitored message to a monitored message storage unit;
step 203: a transmission message receiving unit receives and reads a transmission message from an NC chip;
step 204: the trigger judging unit compares whether the content of the transmission message is consistent with the content of the monitored message, if so, the NC chip is abnormal, the trigger judging unit enters a pause state and sends the information of the abnormal chip to the abnormal result sending unit, and the abnormal result sending unit sends the abnormal result to the external analysis equipment; if not, the NC chip is normal, and the step 3 is returned to continue receiving and reading the transmission message from the NC chip;
step 205: and analyzing the abnormal NC chip by an external analysis device.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above description is only an exemplary embodiment of the present invention, and should not be taken as limiting the scope of the present invention, and any equivalent changes and modifications made by those skilled in the art without departing from the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. An apparatus for improving the efficiency of prototype verification of an FPGA, the apparatus comprising: a monitoring unit, the monitoring unit further comprising: the device comprises a monitored message storage unit, a transmission message receiving unit, a triggering judgment unit and an abnormal result sending unit, wherein:
the monitored message storage unit is used for storing the content of the monitored message;
the transmission message receiving unit is used for receiving and reading a transmission message from the NC chip;
the trigger judging unit is used for comparing whether the content of the transmission message is consistent with the content of the monitored message, if so, the NC chip is abnormal, the trigger judging unit enters a pause state and sends the information of the abnormal chip to the abnormal result sending unit, and the abnormal result sending unit sends the abnormal result to the external analysis equipment; if not, the NC chip is normal, and the transmission message receiving unit is returned to continue receiving and reading the transmission message from the NC chip;
and the result analysis unit is used for analyzing the abnormal NC chip through external analysis equipment.
2. The apparatus according to claim 1, wherein the transmission message receiving unit is located between the monitored message storage unit and the trigger determining unit.
3. The apparatus according to claim 1, wherein the trigger determining unit is located between the transmission message receiving unit and the abnormal result sending unit.
4. The method for improving the prototype verification efficiency of the FPGA based on the device for improving the prototype verification efficiency of the FPGA according to any one of claims 1 to 3, comprising the following steps:
step 1: adding a monitoring unit in an FPGA prototype verification platform, wherein the monitoring unit comprises: the device comprises a monitored message storage unit, a transmission message receiving unit, a trigger judging unit and an abnormal result sending unit;
step 2: storing the content of the monitored message to a monitored message storage unit;
and step 3: a transmission message receiving unit receives and reads a transmission message from an NC chip;
and 4, step 4: the trigger judging unit compares whether the content of the transmission message is consistent with the content of the monitored message, if so, the NC chip is abnormal, the trigger judging unit enters a pause state and sends the information of the abnormal chip to the abnormal result sending unit, and the abnormal result sending unit sends the abnormal result to the external analysis equipment; if not, the NC chip is normal, and the step 3 is returned to continue receiving and reading the transmission message from the NC chip;
and 5: and analyzing the abnormal NC chip by an external analysis device.
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| CN114553663B (en) * | 2022-02-25 | 2024-02-02 | 中国农业银行股份有限公司 | Abnormality detection method, abnormality detection device, abnormality detection equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103514134A (en) * | 2013-10-22 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Random transmission method for chip prototype verification messages |
| CN104363141A (en) * | 2014-11-25 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | FPGA verification method and system based on processor system |
| CN104767658A (en) * | 2015-04-17 | 2015-07-08 | 浪潮电子信息产业股份有限公司 | Method and device for online detecting message transmission errors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103514134A (en) * | 2013-10-22 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Random transmission method for chip prototype verification messages |
| CN104363141A (en) * | 2014-11-25 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | FPGA verification method and system based on processor system |
| CN104767658A (en) * | 2015-04-17 | 2015-07-08 | 浪潮电子信息产业股份有限公司 | Method and device for online detecting message transmission errors |
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