CN106919748A - Improve the device and method of FPGA prototype verification efficiency - Google Patents
Improve the device and method of FPGA prototype verification efficiency Download PDFInfo
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- CN106919748A CN106919748A CN201710103775.5A CN201710103775A CN106919748A CN 106919748 A CN106919748 A CN 106919748A CN 201710103775 A CN201710103775 A CN 201710103775A CN 106919748 A CN106919748 A CN 106919748A
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- 238000012795 verification Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 17
- 230000002159 abnormal effect Effects 0.000 claims abstract description 41
- 238000012544 monitoring process Methods 0.000 claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 10
- 230000006870 function Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 235000013399 edible fruits Nutrition 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000010200 validation analysis Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010835 comparative analysis Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The present invention relates to chip prototype verification technical field, more particularly to a kind of device and method for improving FPGA prototype verification efficiency.The invention discloses a kind of device for improving FPGA prototype verification efficiency, the device includes：Monitoring unit, the monitoring unit is further included：Monitored packet storage unit, transmitting message receiving unit triggers judging unit and abnormal results transmitting element, wherein：The monitored packet storage unit, the content for storing monitored message；The transmitting message receiving unit, for receiving and reads the transmitting message from NC chips；Whether the triggering judging unit, the content for contrasting transmitting message is consistent with the content of monitored message.The invention also discloses a kind of method for improving FPGA prototype verification efficiency.The present invention can help chip design department rapidly analyzing and positioning problem, greatly improve the verification efficiency of FPGA Prototyping Platforms.
Description
Technical field
The present invention relates to chip prototype verification technical field, more particularly to a kind of device for improving FPGA prototype verification efficiency
And method.
Background technology
Chip needs to carry out the checking work of substantial amounts of specialty from flow is designed into, once checking is incomplete, might have
Problem is present in chip, cannot be made up after flow.For the design of more preferable proofing chip, it will usually build structure FPGA prototypes
Platform is verified, by verifying Node Controller under true environment（Node Controller, abbreviation NC）Chip functions
Correctness, can make up soft simulation cannot comprehensively, the defect of fast verification.Validation verification, a side are carried out for system design
Verify multichannel computer availability and realizability, checking high-speed interface hardware PCB design and debugging, mechanical structure and radiating in face
Validation verification；On the other hand firmware is carried out（Firmware）, operating system software early development and commissioning examination.Simultaneously to system
Performance is estimated, and finds performance bottleneck, and guide hardware configuration to plan, the performance of NC logical designs and systems soft ware carry out it is excellent
Change, and have an a certain degree of prediction and analysis to the performance of system.But because the complexity of chip design is often than larger,
The more complicated problem being related to of the process of checking is wider, and being positioned when going wrong can be relatively difficult.Therefore debugging process
In the method for orientation problem just seem especially important.
The content of the invention
For above technical problem, it is an object of the invention to provide a kind of device for improving FPGA prototype verification efficiency and side
Method, can help chip design department rapidly analyzing and positioning problem, greatly improve the verification efficiency of FPGA Prototyping Platforms.
To reach above-mentioned purpose, the present invention is achieved through the following technical solutions：
The present invention provides a kind of device for improving FPGA prototype verification efficiency, and the device includes：Monitoring unit, the monitoring unit
Further include：Monitored packet storage unit, transmitting message receiving unit, triggering judging unit and abnormal results send single
Unit, wherein：
The monitored packet storage unit, the content for storing monitored message；
The transmitting message receiving unit, for receiving and reads the transmitting message from NC chips；
Whether the triggering judging unit, the content for contrasting transmitting message is consistent with the content of monitored message, if unanimously,
Then the NC chip exceptions, trigger judging unit and enter halted state, and the information of abnormal chips is sent into abnormal results sending
Abnormal results is sent to external analysis equipment by unit, the abnormal results transmitting element；If inconsistent, the NC chips are just
Often, transmitting message receiving unit is returned to continue to and read the transmitting message from NC chips.
Further, also include, interpretation of result unit, for being divided abnormal NC chips by external analysis equipment
Analysis.
Further, the transmitting message receiving unit be located at monitored packet storage unit and triggering judging unit it
Between.
Further, the triggering judging unit is located between transmitting message receiving unit and abnormal results transmitting element.
Present invention also offers the raising FPGA prototype verification efficiency based on the device for improving FPGA prototype verification efficiency
Method, comprises the following steps：
Step 1：Monitoring unit is added in FPGA prototype verification platform, the monitoring unit is further included：Monitored message
Memory cell, transmitting message receiving unit, triggering judging unit and abnormal results transmitting element；
Step 2：The content of monitored message is stored to monitored packet storage unit；
Step 3：Transmitting message receiving unit is received and reads the transmitting message from NC chips；
Step 4：Whether the content of triggering judging unit contrast transmitting message is consistent with the content of monitored message, if unanimously,
The NC chip exceptions, triggering judging unit enters halted state, and it is single that the information of abnormal chips is sent into abnormal results transmission
Abnormal results is sent to external analysis equipment by unit, the abnormal results transmitting element；If inconsistent, the NC chips are normal,
Return to step 3 is continued to and reads the transmitting message from NC chips.
Further, after step 4, also include：Abnormal NC chips are analyzed by external analysis equipment.
Compared with prior art, the present invention improves having the beneficial effect that for the device of FPGA prototype verification efficiency：The present invention
Monitoring unit is added in FPGA prototype verification platform, by the content of the content of comparative analysis transmitting message and monitored message
It is whether consistent, whether normally judge NC chips, and abnormal results be sent into external analysis equipment to be analyzed, core can be helped
Piece design department rapidly analyzing and positioning problem, greatly improves the verification efficiency of FPGA Prototyping Platforms；
The beneficial effect of the beneficial effect for improving the method for FPGA prototype verification efficiency and the device for improving FPGA prototype verification efficiency
Fruit seemingly, will not be repeated here.
Brief description of the drawings
Fig. 1 is the structural representation of the device that the present invention improves FPGA prototype verification efficiency.
Fig. 2 is the schematic flow sheet of the method that the present invention improves FPGA prototype verification efficiency.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
A part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The noun and concept that occur in the following example are explained below：
FPGA：English full name Field-Programmable Gate Array, i.e. field programmable gate array, it be PAL,
The product further developed on the basis of the programming devices such as GAL, CPLD.Inside includes configurable logic blocks CLB
（Configurable Logic Block）, input/output module IOB（Input Output Block）And interconnector
（Interconnect）Three parts.
FPGA prototype verification：Be will the direct burned chip of design, and this chip is placed in test system or application system is opened
In hair ring border, the correctness that can be just designed with proofing chip by actual test and application, diagnosis is made mistake and.
With reference to the accompanying drawings and detailed description to a kind of device for improving FPGA prototype verification efficiency of the invention and side
Method is further described：
Embodiment 1
Fig. 1 is refer to, a kind of device of raising FPGA prototype verification efficiency, the device includes：Monitoring unit, the monitoring unit
Further include：Monitored packet storage unit 101, transmitting message receiving unit 102, triggering judging unit 103 and abnormal knot
Fruit transmitting element 104, wherein：
The monitored packet storage unit 101, the content for storing monitored message；
The transmitting message receiving unit 102, for receiving and reads the transmitting message from NC chips；
Whether the triggering judging unit 103, the content for contrasting transmitting message is consistent with the content of monitored message, if one
Cause, then the NC chip exceptions, triggering judging unit 103 enters halted state, and the information of abnormal chips is sent into abnormal knot
Abnormal results is sent to external analysis equipment by fruit transmitting element 104, the abnormal results transmitting element 104；If inconsistent,
The NC chips are normal, return to transmitting message receiving unit 102 and continue to and read the transmitting message from NC chips.
Said apparatus also include interpretation of result unit 105, for being divided abnormal NC chips by external analysis equipment
Analysis.
Above-mentioned transmitting message receiving unit 102 be located at monitored packet storage unit 101 and triggering judging unit 103 it
Between.Above-mentioned triggering judging unit 103 is located between transmitting message receiving unit 102 and abnormal results transmitting element 104.
Said external analytical equipment is computer or oscillograph.
Embodiment 2
Fig. 2 is refer to, a kind of method of raising FPGA prototype verification efficiency is comprised the following steps：
Step 201：Monitoring unit is added in FPGA prototype verification platform, the monitoring unit includes：Monitored packet storage
Unit, transmitting message receiving unit, triggering judging unit and abnormal results transmitting element；
Step 202：The content of monitored message is stored to monitored packet storage unit；
Step 203：Transmitting message receiving unit is received and reads the transmitting message from NC chips；
Step 204：Whether the content of triggering judging unit contrast transmitting message is consistent with the content of monitored message, if unanimously,
Then the NC chip exceptions, trigger judging unit and enter halted state, and the information of abnormal chips is sent into abnormal results sending
Abnormal results is sent to external analysis equipment by unit, the abnormal results transmitting element；If inconsistent, the NC chips are just
Often, return to step 3 is continued to and reads the transmitting message from NC chips；
Step 205：Abnormal NC chips are analyzed by external analysis equipment.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, generally describes the composition and step of each example according to function in the above description.And this
A little functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.Specially
Industry technical staff can realize described function to each specific application using distinct methods, but this realization is not
It is considered as beyond the scope of this invention.
Schematical specific embodiment of the invention is the foregoing is only, the scope of the present invention is not limited to, it is any
The equivalent variations that those skilled in the art is made on the premise of present inventive concept and principle is not departed from and modification, all should belong to
In the scope of protection of the invention.
Claims (6)
1. it is a kind of improve FPGA prototype verification efficiency device, it is characterised in that the device includes：Monitoring unit, the monitoring
Unit is further included：Monitored packet storage unit, transmitting message receiving unit, triggering judging unit and abnormal results send
Unit, wherein：
The monitored packet storage unit, the content for storing monitored message；
The transmitting message receiving unit, for receiving and reads the transmitting message from NC chips；
Whether the triggering judging unit, the content for contrasting transmitting message is consistent with the content of monitored message, if unanimously,
Then the NC chip exceptions, trigger judging unit and enter halted state, and the information of abnormal chips is sent into abnormal results sending
Abnormal results is sent to external analysis equipment by unit, the abnormal results transmitting element；If inconsistent, the NC chips are just
Often, transmitting message receiving unit is returned to continue to and read the transmitting message from NC chips.
2. it is according to claim 1 improve FPGA prototype verification efficiency device, it is characterised in that also include, as a result divide
Analysis unit, for being analyzed to abnormal NC chips by external analysis equipment.
3. it is according to claim 1 improve FPGA prototype verification efficiency device, it is characterised in that the transmitting message connects
Unit is received to be located between monitored packet storage unit and triggering judging unit.
4. the device for improving FPGA prototype verification efficiency according to claim 1, it is characterised in that the triggering judges single
Unit is located between transmitting message receiving unit and abnormal results transmitting element.
5. the raising FPGA prototypes of the device based on the raising FPGA prototype verification efficiency any one of claim 1 ~ 4 are tested
The method for demonstrate,proving efficiency, it is characterised in that comprise the following steps：
Step 1：Monitoring unit is added in FPGA prototype verification platform, the monitoring unit includes：Monitored packet storage list
Unit, transmitting message receiving unit, triggering judging unit and abnormal results transmitting element；
Step 2：The content of monitored message is stored to monitored packet storage unit；
Step 3：Transmitting message receiving unit is received and reads the transmitting message from NC chips；
Step 4：Whether the content of triggering judging unit contrast transmitting message is consistent with the content of monitored message, if unanimously,
The NC chip exceptions, triggering judging unit enters halted state, and it is single that the information of abnormal chips is sent into abnormal results transmission
Abnormal results is sent to external analysis equipment by unit, the abnormal results transmitting element；If inconsistent, the NC chips are normal,
Return to step 3 is continued to and reads the transmitting message from NC chips.
6. it is according to claim 5 improve FPGA prototype verification efficiency method, it is characterised in that after step 4, also
Including：Abnormal NC chips are analyzed by external analysis equipment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710103775.5A CN106919748B (en) | 2017-02-24 | 2017-02-24 | Device and method for improving FPGA prototype verification efficiency |
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| CN201710103775.5A CN106919748B (en) | 2017-02-24 | 2017-02-24 | Device and method for improving FPGA prototype verification efficiency |
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| CN106919748A true CN106919748A (en) | 2017-07-04 |
| CN106919748B CN106919748B (en) | 2021-01-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112651199A (en) * | 2020-12-24 | 2021-04-13 | 山东高云半导体科技有限公司 | Quality verification platform and quality verification method |
| CN114553663A (en) * | 2022-02-25 | 2022-05-27 | 中国农业银行股份有限公司 | Abnormity detection method, device, equipment and storage medium |
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| CN103514134A (en) * | 2013-10-22 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Random transmission method for chip prototype verification messages |
| CN104363141A (en) * | 2014-11-25 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | FPGA verification method and system based on processor system |
| CN104767658A (en) * | 2015-04-17 | 2015-07-08 | 浪潮电子信息产业股份有限公司 | Method and device for online detecting message transmission errors |
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2017
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103514134A (en) * | 2013-10-22 | 2014-01-15 | 浪潮电子信息产业股份有限公司 | Random transmission method for chip prototype verification messages |
| CN104363141A (en) * | 2014-11-25 | 2015-02-18 | 浪潮(北京)电子信息产业有限公司 | FPGA verification method and system based on processor system |
| CN104767658A (en) * | 2015-04-17 | 2015-07-08 | 浪潮电子信息产业股份有限公司 | Method and device for online detecting message transmission errors |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112651199A (en) * | 2020-12-24 | 2021-04-13 | 山东高云半导体科技有限公司 | Quality verification platform and quality verification method |
| CN112651199B (en) * | 2020-12-24 | 2023-08-29 | 山东高云半导体科技有限公司 | Quality Verification Platform and Quality Verification Method |
| CN114553663A (en) * | 2022-02-25 | 2022-05-27 | 中国农业银行股份有限公司 | Abnormity detection method, device, equipment and storage medium |
| CN114553663B (en) * | 2022-02-25 | 2024-02-02 | 中国农业银行股份有限公司 | Abnormality detection method, abnormality detection device, abnormality detection equipment and storage medium |
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| CN106919748B (en) | 2021-01-22 |
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Effective date of registration: 20201202 Address after: 215000 Building 9, No.1, guanpu Road, Guoxiang street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 450000 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY Co.,Ltd. |
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