CN114363145A - BIT fault injection and detection time sequence control method for airborne electronic system - Google Patents
BIT fault injection and detection time sequence control method for airborne electronic system Download PDFInfo
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Abstract
The invention belongs to the technical field of testability verification of airborne electronic technology, and particularly relates to a BIT fault injection and detection time sequence control method of an airborne electronic system. The method of the invention combines the function BIT and the performance BIT according to three types of power-on BIT, period BIT and maintenance BIT, and sets BIT test constraint conditions by controlling the product power-on time, task starting time, fault injection time or maintenance instruction sending time, thereby avoiding crosstalk of different types of BIT. The method effectively realizes that the test action of the fault injection system is introduced into different BITs of the tested object, avoids mutual overlapping of fault simulation processes of the different BITs, can accurately carry out test implementation work, and has higher practical application value.
Description
Technical Field
The invention belongs to the technical field of testability verification of airborne electronic technology, and particularly relates to a BIT fault injection and detection time sequence control method of an airborne electronic system.
Background
The testability is a design characteristic that equipment can timely and accurately determine the working state of the equipment and effectively isolate internal faults of the equipment. The testability design is mainly realized through the design of BIT (built-in test), the main BIT in the current electronic system comprises three types, namely power-on BIT, periodic BIT and maintenance BIT, and the BIT can be divided into functional BIT and performance BIT.
The testability design level is verified and evaluated in the laboratory mainly by means of fault injection tests. Similarly, the fault injection facing the testability test is mainly fault injection facing different BITs.
The basic architecture of testability verification is shown in fig. 1 and comprises a tested object, a fault injection system and a tested object detection system. Because the tested object and the fault injection system are mutually independent systems, how to introduce the test action of the fault injection system into different BITs of the tested object becomes the key of successful test. At present, no standard operation of coordination between fault injection and BIT exists in the industry, so that fault simulation processes of different BITs are mutually overlapped, and test implementation work cannot be accurately carried out.
Disclosure of Invention
The purpose of the invention is as follows: the time sequence control method can effectively coordinate airborne fault injection and BIT test and avoid mutual overlapping interference of different BIT fault simulation processes.
The technical scheme of the invention is as follows: according to the method, the BIT test constraint conditions are set by controlling the product electrifying time, the task starting time, the fault injection time or the maintenance instruction sending time according to three types of electrifying BIT, periodic BIT and maintenance BIT and combining the functional BIT and the performance BIT, so that the crosstalk of different types of BIT is avoided, and the BIT fault injection time is staggered.
When the periodic BIT test is oriented, the fault injection and detection process of the functional BIT is as follows:
step 2.1.1: electrifying the tested object and entering an electrifying working state;
step 2.1.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.1.3: starting a task by the object to be tested, and entering a task execution state;
step 2.1.4: performing fault injection;
step 2.1.5: the tested object executes the period BIT and reports the fault detection result;
step 2.1.6: and (5) ending fault injection and canceling the fault.
When the periodic BIT test is oriented, the fault injection and detection process of the performance BIT is as follows:
step 2.2.1: electrifying the tested object and entering an electrifying working state;
step 2.2.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.2.3: starting a task by the object to be tested, and entering a task execution state;
step 2.2.4: performing a first fault injection;
step 2.2.5: the tested object executes the period BIT and reports the fault detection result;
step 2.2.6: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 2.2.7: the tested object executes the period BIT and reports the fault detection result;
step 2.2.8: judging whether fault injection is successful, if so, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
step 2.2.9: and (5) ending fault injection and canceling the fault.
When the power-on BIT test is oriented, the fault injection and detection process of the functional BIT is as follows:
step 3.1.1: performing fault injection on the tested object;
step 3.1.2: electrifying the tested object and entering an electrifying working state;
step 3.1.3: the tested object executes power-up BIT and reports a fault detection result;
step 3.1.4: the fault injection is ended, the fault is cancelled,
in step 3.1.2, if the product does not need to be prepared for starting time or the starting time is short, the tested object can directly enter a task state after being electrified.
When the power-on BIT test is performed, the product does not need to prepare the start time, or the start time is very short, and at this time, the fault injection and detection timing sequence is shown in fig. 4b, and the specific execution steps are as follows:
step 3.2.1: performing fault injection on the tested object;
step 3.2.2: electrifying the tested object and entering a task state;
step 3.2.3: the tested object executes one-time periodic BIT and reports a fault detection result;
step 3.2.4: and (5) ending fault injection and canceling the fault.
When the power-on BIT test is oriented, the fault injection and detection control process for the performance BIT is as follows:
step 3.3.1: performing fault injection on the tested object;
step 3.3.2: electrifying the tested object and entering an electrifying working state;
step 3.3.3: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.4: and powering off the tested object.
Step 3.3.5: adjusting fault injection stress, and executing ith (i is 2,3, … …) th fault injection;
step 3.3.6: electrifying the tested object and entering an electrifying working state;
step 3.3.7: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.8: and powering off the tested object.
Step 3.3.9: judging whether fault injection is successful, if so, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and canceling the fault.
When the maintenance BIT test is oriented, the fault injection and detection process of the functional BIT is as follows:
step 4.1.1: performing fault injection on the tested object;
step 4.1.2: electrifying the tested object and entering an electrifying working state;
step 4.1.3: clearing the power-on BIT information;
step 4.1.4: adjusting the object to be measured to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.1.7: and (5) ending fault injection and canceling the fault.
When the maintenance BIT test is oriented, the fault injection and detection process of the performance BIT is as follows:
step 4.2.1: electrifying the tested object and entering an electrifying working state;
step 4.2.2: performing fault injection on the tested object;
step 4.2.3: clearing the BIT information once (usually periodic BIT);
step 4.2.4: adjusting the object to be measured to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.2.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.7: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 4.2.8: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.2.9: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.10: judging whether fault injection is successful or not, if so, executing the step 4.2.11, otherwise, repeatedly executing the step 4.2.7, the step 4.2.8, the step 4.2.9 and the step 4.2.10;
step 4.2.11: and (5) ending fault injection and canceling the fault.
The invention has the beneficial effects that: according to the method for controlling the BIT fault injection and detection time sequence of the airborne electronic system, the BIT test constraint conditions are set by controlling the product electrifying time, the task starting time, the fault injection time or the maintenance instruction sending time according to different BIT types, so that the test action of the fault injection system is effectively introduced into different BITs of the tested object, the mutual overlapping of fault simulation processes of different BITs is avoided, the test implementation work can be accurately carried out, and the method has a high practical application value.
Drawings
FIG. 1 is a diagram of a testability test basic architecture;
FIG. 2 is a schematic diagram of the verification of the present invention;
FIG. 3 is a periodic BIT fault injection timing diagram;
FIG. 4 is a timing diagram of a power-up BIT fault injection timing versus functional BIT;
FIG. 5 is a power-up BIT fault injection timing diagram versus performance BIT timing diagram;
FIG. 6 is a maintenance BIT fault injection timing diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention selects the transmission fault of a transceiver of a certain radio station, and carries out verification based on the invention. Verification schematic as shown in fig. 2, basic information at fault injection is as follows.
| Serial number | Item | Content providing method and apparatus | Remarks for note | |
| 1 | Failure | Transmitting fault | ||
| 2 | Fault detection method | Power-up BIT, periodic BIT, maintenance BIT | ||
| 3 | Fault injection method | Short-circuit two ends of resistor R48 of gain control circuit of |
||
| 4 | BIT reading mode | Radio station detector | ||
| 5 | Anticipating reporting of faults | Transmitting fault |
According to the above, the verification steps under each BIT are designed as follows:
1) periodic BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing the test object according to the fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and the power supply is turned off, and the operation of the transceiver is stopped. (Note: the steps 1 and 2 are one-time function check and protection before the test Evidence that the test subject is normal)。
And step 3: the channel cell gain control circuit resistor R48 is extended by a short-circuit switch. The switch is open and in the "off" state.
And 4, step 4: and electrifying again to start the test object.
And 5: the short-circuit switch is closed and is in an "on" state.
Step 6: observing and reading the fault detection condition of the transceiver through a radio station detector, filling a data record table, and if the reported result is 'transmission fault', successfully detecting the fault; otherwise, performing problem analysis.
And 7: and stopping the operation of the test object, disconnecting the short-circuit switch, recovering the product state, detecting the functional performance of the product, and filling a 'functional performance detection table'. If the abnormity is found, processing according to a fault processing program; if the product is normal, the test is finished.
If the 'transmission fault' is read, the method proves that the periodic BIT design is correct, and if the 'transmission fault' is not read, the method proves that the periodic BIT design fails.
1) Power-on BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing the test object according to the fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and the power supply is turned off, and the operation of the transceiver is stopped. (Note: the steps 1 and 2 are one-time function check and protection before the test Evidence that the test subject is normal)。
And step 3: the channel cell gain control circuit resistor R48 is extended by a short-circuit switch. The switch is closed and in the "on" state.
And 4, step 4: and powering on again, starting the test object and loading a low-power transmission task.
And 5: observing and reading the fault detection condition of the transceiver once through a radio station detector, filling a data record table, and if the reported result is 'transmission fault', successfully detecting the fault; otherwise, performing problem analysis.
Step 6: and stopping the operation of the test object, disconnecting the short-circuit switch, recovering the product state, detecting the functional performance of the product, and filling a 'functional performance detection table'. If the abnormity is found, processing according to a fault processing program; if the product is normal, the test is finished.
If the 'transmission fault' is read, the power-on BIT design is proved to be correct through the method, and if the 'transmission fault' is not read, the power-on BIT design is proved to be failed through the method.
2) Maintaining BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing the test object according to the fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and the power supply is turned off, and the operation of the transceiver is stopped. (Note: the steps 1 and 2 are one-time function check and protection before the test Evidence that the test subject is normal)。
And step 3: the channel cell gain control circuit resistor R48 is extended by a short-circuit switch. The switch is closed and in the "on" state.
And 4, step 4: and electrifying again to start the test object.
And 5: and sending a fault clearing instruction to clear all fault information.
Step 6: and adjusting the transceiver to enter a maintenance mode, sending a maintenance self-checking instruction, and starting maintenance self-checking.
And 7: observing and reading the fault detection condition of the transceiver through a radio station detector, filling a data record table, and if the reported result is 'transmission fault', successfully detecting the fault; otherwise, performing problem analysis.
And 8: and stopping the operation of the test object, disconnecting the short-circuit switch, recovering the product state, detecting the functional performance of the product, and filling a 'functional performance detection table'. If the abnormity is found, processing according to a fault processing program; if the product is normal, the test is finished.
If the transmission fault is read, the method proves that the maintenance BIT design is correct and exists, and if the transmission fault is not read, the method proves that the maintenance BIT design fails.
In the following, with reference to specific embodiments, the description is made with respect to the timing of fault injection and detection for three BITs, the timing of fault injection and detection for supporting periodic BIT, power-up BIT, and maintenance BIT, and the timing of fault injection and detection for functional BIT and performance BIT in the testability test of the present invention.
Example 1:
the main nodes of the timing sequence for fault injection and detection facing to period BIT in the testability test comprise product power-on time, task starting time and fault injection time. The fault injection and detection timing for functional BIT is shown in fig. 3 a. The specific execution steps are as follows:
step 2.1.1: electrifying the tested object and entering an electrifying working state;
step 2.1.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.1.3: starting a task by the object to be tested, and entering a task execution state;
step 2.1.4: performing fault injection;
the node executes fault injection operation to avoid interference of power-on BIT to cycle BIT, and the cycle BIT after starting a task is the most accurate expression in the system.
Step 2.1.5: the tested object executes the period BIT and reports the fault detection result;
step 2.1.6: and (5) ending fault injection and canceling the fault.
The uniqueness fault injection verification of the function cycle BIT can be realized through the operation time sequence.
Example 2:
the fault injection and detection timing sequence for the performance BIT is shown in fig. 3b, and the specific implementation steps are as follows:
step 2.2.1: electrifying the tested object and entering an electrifying working state;
step 2.2.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.2.3: starting a task by the object to be tested, and entering a task execution state;
step 2.2.4: performing a first fault injection;
initial verification parameters for performance period BIT verification can be determined by operation of the node.
Step 2.2.5: the tested object executes the period BIT and reports the fault detection result;
step 2.2.6: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
through the operation of the node, the variable quantity of the parameters between verification of the BIT verification in the performance period can be determined in an experimental mode, and the termination parameters are searched and searched.
Step 2.2.7: the tested object executes the period BIT and reports the fault detection result;
step 2.2.8: judging whether fault injection is successful, if so, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
step 2.2.9: and (5) ending fault injection and canceling the fault.
The uniqueness fault injection verification of the performance cycle BIT can be realized through the operation time sequence.
Example 3: the main nodes of the fault injection and detection time sequence facing to the power-on BIT in the testability test comprise product power-on time, task starting time and fault injection time. The fault injection and detection timing for functional BIT is shown in fig. 4 a. The specific execution steps are as follows:
step 3.1.1: performing fault injection on the tested object;
step 3.1.2: electrifying the tested object and entering an electrifying working state;
step 3.1.3: the tested object executes power-up BIT and reports a fault detection result;
the node executes the fault injection operation, so that the power-on BIT information can be read in time before the cycle BIT works, and the coverage of the power-on BIT result after the cycle BIT occurs is avoided.
Step 3.1.4: and (5) ending fault injection and canceling the fault.
The uniqueness fault injection verification of the functional power-on BIT can be realized through the operation time sequence.
Example 4:
in practical engineering application, some products do not need to prepare starting time, or the starting time is short, the products can quickly enter a working state after being electrified, and the cycle BIT read for the first time can be approximately regarded as a power-on BIT detection result. The timing of fault injection and detection is shown in fig. 4 b. The specific execution steps are as follows:
step 3.2.1: performing fault injection on the tested object;
the node performs the fault injection operation, so that the problem that the fault injection operation cannot be performed due to the fact that the interval between the power-on time and the task starting time is too short (generally less than 1 second) can be solved.
Step 3.2.2: electrifying the tested object and entering a task state;
step 3.2.3: the tested object executes one-time periodic BIT and reports a fault detection result;
step 3.2.4: and (5) ending fault injection and canceling the fault.
The engineering optimal approximate fault injection verification of the functional power-up BIT can be realized through the operation time sequence.
Example 5:
the fault injection and detection timing for performance BIT is shown in fig. 5. The specific execution steps are as follows:
step 3.3.1: performing fault injection on the tested object;
the node executes the fault injection operation, can read the power-on BIT information in time before the cycle BIT works, avoids covering the power-on BIT result after the cycle BIT occurs, and simultaneously determines the initial verification parameters of the performance power-on BIT verification.
Step 3.3.2: electrifying the tested object and entering an electrifying working state;
step 3.3.3: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.4: and powering off the tested object. The purpose of the node powering down is to reacquire the power-on BIT information in subsequent operations, and if not powered down, the periodic BIT overwrites the power-on BIT information.
Step 3.3.5: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 3.3.6: electrifying the tested object and entering an electrifying working state;
step 3.3.7: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.8: and powering off the tested object.
Step 3.3.9: judging whether fault injection is successful, if so, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and canceling the fault.
The operation time sequence is completed in a mode of multiple times of power-on and power-off, and engineering optimal approximate fault injection verification of the functional power-on BIT can be achieved.
Example 6:
towards the fault injection and the detection time sequence of maintaining BIT among the testability test, its characterized in that: the main nodes comprise product power-on time, task starting time, fault injection time and maintenance instruction sending time. The fault injection and detection timing for functional BIT is shown in fig. 6 a. The specific execution steps are as follows:
step 4.1.1: performing fault injection on the tested object;
the node is used for safety of engineering operation, fault injection is carried out before power-on, the influence on a test object is reduced to the maximum extent, and otherwise, damage is easily caused after the fault injection after the power-on.
Step 4.1.2: electrifying the tested object and entering an electrifying working state;
step 4.1.3: clearing one time BIT information (typically a power-up BIT);
the power-up BIT is performed in the same process, and the power-up BIT detection result is generated at the time, so that the power-up BIT is cleared in time in order to prevent the power-up BIT from interfering with the maintenance BIT.
Step 4.1.4: adjusting the object to be measured to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.1.7: and (5) ending fault injection and canceling the fault.
The engineering safest and accurate fault injection verification of the function maintenance BIT can be realized through the operation time sequence.
Example 7:
the fault injection and detection timing for performance BIT is shown in fig. 6 b.
The specific execution steps are as follows:
step 4.2.1: electrifying the tested object and entering an electrifying working state;
step 4.2.2: performing fault injection on the tested object;
the node is used for safety of engineering operation, fault injection is carried out before power-on, the influence on a test object is reduced to the maximum extent, and otherwise, damage is easily caused after the fault injection after the power-on.
Step 4.2.3: clearing the BIT information once (usually periodic BIT);
the power-up BIT is the same in the process, and the power-up BIT detection result is generated at the time, so that the power-up BIT is cleared in time, the purpose is to prevent the power-up BIT from interfering the maintenance BIT, and meanwhile, the initial verification parameters of the performance maintenance BIT verification are determined.
Step 4.2.4: adjusting the object to be measured to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
the information acquired after issuing the maintenance instruction is the most accurate expression for maintaining the BIT.
Step 4.2.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.7: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 4.2.8: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
the information acquired after issuing the maintenance instruction is the most accurate expression for maintaining the BIT.
Step 4.2.9: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.10: judging whether fault injection is successful or not, if so, executing the step 4.2.11, otherwise, repeatedly executing the step 4.2.7, the step 4.2.8, the step 4.2.9 and the step 4.2.10;
step 4.2.11: and (5) ending fault injection and canceling the fault.
The safest and accurate fault injection verification of the engineering of the performance maintenance BIT can be realized through the operation time sequence.
In summary, according to the three types of power-on BIT, periodic BIT and maintenance BIT, the invention combines functional BIT and performance BIT, sets BIT test constraint conditions by controlling the product power-on time, task starting time, fault injection time or maintenance instruction sending time, avoids crosstalk of different types of BIT, realizes staggered BIT fault injection time, and avoids the problem of incorrect verification caused by mutual coverage of different BITs in conventional verification.
The foregoing is merely a detailed description of the embodiments of the present invention, and some of the conventional techniques are not detailed. The scope of the present invention is not limited thereto, and any changes or substitutions that can be easily made by those skilled in the art within the technical scope of the present invention will be covered by the scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. The method is characterized in that the BIT test constraint conditions are set by controlling the product electrifying time, the task starting time, the fault injection time or the maintenance instruction sending time according to three types of electrifying BIT, periodic BIT and maintenance BIT and combining the functional BIT and the performance BIT, so that the crosstalk of different types of BIT is avoided, and the BIT fault injection time is staggered.
2. The BIT fault injection and detection timing control method for an on-board electronic system according to claim 1, wherein for periodic BIT testing, the fault injection and detection process of functional BIT is as follows:
step 2.1.1: electrifying the tested object and entering an electrifying working state;
step 2.1.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.1.3: starting a task by the object to be tested, and entering a task execution state;
step 2.1.4: performing fault injection;
step 2.1.5: the tested object executes the period BIT and reports the fault detection result;
step 2.1.6: and (5) ending fault injection and canceling the fault.
3. The BIT fault injection and detection timing control method for the onboard electronic system according to claim 1, wherein the fault injection and detection process of the performance BIT in the periodic BIT test is as follows:
step 2.2.1: electrifying the tested object and entering an electrifying working state;
step 2.2.2: the tested object executes power-up BIT and reports a fault detection result;
step 2.2.3: starting a task by the object to be tested, and entering a task execution state;
step 2.2.4: performing a first fault injection;
step 2.2.5: the tested object executes the period BIT and reports the fault detection result;
step 2.2.6: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 2.2.7: the tested object executes the period BIT and reports the fault detection result;
step 2.2.8: judging whether fault injection is successful, if so, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
step 2.2.9: and (5) ending fault injection and canceling the fault.
4. The BIT fault injection and detection timing control method for an on-board electronic system according to claim 1, wherein when the power-on BIT test is performed, the fault injection and detection process of the functional BIT is as follows:
step 3.1.1: performing fault injection on the tested object;
step 3.1.2: electrifying the tested object and entering an electrifying working state;
step 3.1.3: the tested object executes power-up BIT and reports a fault detection result;
step 3.1.4: the fault injection is ended, the fault is cancelled,
in step 3.1.2, if the product does not need to be prepared for starting time or the starting time is short, the tested object can directly enter a task state after being electrified.
5. The method for controlling BIT fault injection and detection timing of an on-board electronic system according to claim 1, wherein when conducting a power-on BIT test, a product does not need to prepare a start-up time or the start-up time is short, and the fault injection and detection timing is shown in fig. 4b, and the following steps are executed:
step 3.2.1: performing fault injection on the tested object;
step 3.2.2: electrifying the tested object and entering a task state;
step 3.2.3: the tested object executes one-time periodic BIT and reports a fault detection result;
step 3.2.4: and (5) ending fault injection and canceling the fault.
6. The BIT fault injection and detection timing control method for an on-board electronic system according to claim 1, wherein when performing a power-up BIT test, the control procedure for the performance BIT fault injection and detection is as follows:
step 3.3.1: performing fault injection on the tested object;
step 3.3.2: electrifying the tested object and entering an electrifying working state;
step 3.3.3: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.4: and powering off the tested object.
Step 3.3.5: adjusting fault injection stress, and executing ith (i is 2,3, … …) th fault injection;
step 3.3.6: electrifying the tested object and entering an electrifying working state;
step 3.3.7: the tested object executes power-up BIT and reports a fault detection result;
step 3.3.8: and powering off the tested object.
Step 3.3.9: judging whether fault injection is successful, if so, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and canceling the fault.
7. The BIT fault injection and detection timing control method for the onboard electronic system according to claim 1, wherein when the BIT test is performed for maintenance, the fault injection and detection process of the functional BIT is as follows:
step 4.1.1: performing fault injection on the tested object;
step 4.1.2: electrifying the tested object and entering an electrifying working state;
step 4.1.3: clearing the power-on BIT information;
step 4.1.4: adjusting the object to be measured to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.1.7: and (5) ending fault injection and canceling the fault.
8. The BIT fault injection and detection timing control method for the onboard electronic system according to claim 1, wherein when testing the BIT for maintenance, the fault injection and detection process for the performance BIT is as follows:
step 4.2.1: electrifying the tested object and entering an electrifying working state;
step 4.2.2: performing fault injection on the tested object;
step 4.2.3: clearing the BIT information once (usually periodic BIT);
step 4.2.4: adjusting the object to be measured to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.2.6: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.7: adjusting fault injection stress, and executing i (i is 2,3, … …) th fault injection;
step 4.2.8: issuing a maintenance instruction to the object to be tested, and executing maintenance BIT;
step 4.2.9: the tested object executes maintenance BIT and reports a fault detection result;
step 4.2.10: judging whether fault injection is successful or not, if so, executing the step 4.2.11, otherwise, repeatedly executing the step 4.2.7, the step 4.2.8, the step 4.2.9 and the step 4.2.10;
step 4.2.11: and (5) ending fault injection and canceling the fault.
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