CN113409873B - System, method and executing device for testing erasing interference - Google Patents
System, method and executing device for testing erasing interference Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3422—Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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Abstract
The application provides an erasing interference test system, an erasing interference test method and an execution device, and the technical scheme is as follows: comprising the following steps: the device comprises a main control module, an FPGA module connected with the main control module and a chip to be tested connected with the FPGA module; the main control module is used for sending an operation instruction and receiving a level signal sent by the FPGA module; the FPGA module receives an operation instruction sent by the main control module and forwards the operation instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation, the FPGA module compares the result of the reading operation and generates a level signal to be transmitted to the main control module, and the main control module judges whether erasure interference exists or not according to the level signal. The erasing interference test system, the erasing interference test method and the executing device have the advantage of high test efficiency.
Description
Technical Field
The application relates to the technical field of chip testing, in particular to a system, a method and an execution device for testing erasing interference.
Background
The flash memory chip widely used in the market at present is composed of a floating gate structure (floating gate), electrons are moved in and out under the action of an electric field to respectively correspond to programming (program) and erasing (erase), the quantity of electrons stored in the floating gate can change the conducting voltage of a field effect, namely a threshold voltage (Vth), the threshold voltage is used for distinguishing between 0 and 1, a higher Vth is identified as "0" for writing, and a lower Vth is identified as "1" for erasing. For Nor flash, the write and erase correspond to hot electron injection and F-N tunneling principles, respectively, where the programming operation is with the gate and drain connected to voltages of 8.4V and 3.9V, respectively, the substrate and source grounded, and the erase operation is with the substrate and source both connected to voltages of 7-10V, with the gate voltage of-9V.
In order to optimize the area, flash memory chips with floating gate structures prepared by a process below 65nm in the market are placed in a concentrated manner on a physical structure to form a plurality of memory matrixes, each memory matrix is logically divided into a plurality of array blocks based on the floating gate technology, different array blocks are positioned on the same substrate, and when one array block in one physical memory array is subjected to erasing operation, the array block selected to be operated and the rest array blocks in the memory array are connected with each other by virtue of a drain electrode, a source electrode and the substrate, so that the array blocks can be interfered by the voltage of the drain electrode.
In summary, the anti-erasure interference strength is one of important reference indexes for evaluating the quality of a flash chip, so that the accurate and efficient flash chip erasure interference detection device and method become particularly important.
In the traditional scheme for testing whether the erasing and writing interference exists, the flash is directly tested by the MCU, if the erasing and writing interference test is required to be completed once and the result is read, the MCU is required to carry out the erasing-programming cycle operation on one sector, and the data reading operation is carried out on the other sector in the gap of the erasing-programming cycle operation, namely the erasing-reading-programming-reading, and then the result can be known after the data read from the flash is compared in the MCU. The MCU can only operate one flash chip at a time, but with the wide application of chips, the number of chips increases suddenly, and the erase-write interference test before the application market is an important evaluation method for the quality of chips, so the traditional inefficient test method is not suitable for large-scale application-level chip tests such as flash. In addition, the conventional test of erasing interference of the flash chip is serial, for example, after only one erasing/writing instruction is sent to one sector, then a read instruction can be sent to the other sector to check whether erasing interference is generated or not, or a plurality of erasing/writing instructions are sent to one sector, then a read instruction is sent to the other sector to check whether erasing interference is generated or not, and the test cannot simulate a scene that a client uses the flash chip, namely, the erasing/writing operation is performed to the one sector and the reading operation is performed to the other sector.
In view of the above, improvements are needed.
Disclosure of Invention
The embodiment of the application aims to provide a system, a method and an execution device for testing erasing interference, which have the advantage of high test efficiency.
In a first aspect, an embodiment of the present application provides an erasure interference testing system, which has the following technical scheme:
comprising the following steps: the device comprises a main control module, an FPGA module connected with the main control module and a chip to be tested connected with the FPGA module;
the main control module is used for sending an operation instruction and receiving a level signal sent by the FPGA module;
the FPGA module receives an operation instruction sent by the main control module and forwards the operation instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation, the FPGA module compares the result of the reading operation and generates a level signal to be transmitted to the main control module, and the main control module judges whether erasure interference exists or not according to the level signal.
Further, in the embodiment of the present application, the FPGA module includes at least a CTRL unit and a SLOT unit;
the CTRL unit analyzes the operation instruction and then transmits the operation instruction to the SLOT unit;
the SLOT unit receives the analyzed instruction from the CTRL unit and sends the instruction of the corresponding operation to the chip to be tested, so that the chip to be tested executes the erasing operation or the programming operation or the reading operation, and the SLOT unit receives and registers the result information of the chip to be tested executing the reading operation.
Further, in this embodiment of the present application, the electronic device further includes a digital potentiometer module, where the digital potentiometer module receives an operation instruction sent by the main control module, and supplies power to the FPGA module and the chip to be tested according to the operation instruction.
Further, in this embodiment of the present application, the device further includes an analog-to-digital conversion module, where the analog-to-digital conversion module collects voltage information of the FPGA module and the chip to be tested, and transmits the voltage information to the main control module through the FPGA module, and the main control module controls the digital potentiometer module to adjust the voltage according to the voltage information.
In a second aspect, the present application further provides an erasing interference testing method, which is used for performing an erasing interference test by an FPGA module, where one end of the FPGA module is connected with a main control module, and the other end of the FPGA module is connected with a chip to be tested, and the method includes:
acquiring an operation instruction of a main control module to a chip to be tested;
analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;
and comparing the result of the reading operation to generate a level signal.
Further, in an embodiment of the present application, the method further includes:
acquiring voltage information on the chip to be tested;
and sending the voltage information to the main control module, so that the main control module adjusts the voltage.
In a third aspect, the present application further provides another method for testing erasing interference, which is used for a main control module to perform erasing interference test, where the main control module is connected with a chip to be tested through an FPGA module, and includes:
sending an operation instruction to the chip to be tested to the FPGA module, so that the FPGA module sends the analyzed operation instruction to the chip to be tested, and further the chip to be tested performs an erasing operation or a programming operation or a reading operation;
acquiring a level signal generated by comparing a reading operation result after the FPGA module executes the reading operation on the chip to be tested;
judging whether erasure interference exists or not according to the level signal.
Further, in an embodiment of the present application, the method further includes:
acquiring voltage information of the FPGA module and the chip to be tested;
and adjusting the power supply of the FPGA module and the chip to be tested according to the voltage information.
In a fourth aspect, the present application further provides an execution apparatus, including:
The first acquisition module is used for acquiring an operation instruction of the main control module to the chip to be tested;
the first processing module is used for analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;
and the second processing module is used for comparing the result of the reading operation to generate a level signal.
In a fifth aspect, the present invention provides an execution apparatus, comprising:
the third processing module is used for sending an operation instruction of the chip to be tested to the FPGA module, so that the FPGA module sends the relevant operation instruction to the chip to be tested, and the chip to be tested is further enabled to execute an erasing operation or a programming operation or a reading operation;
the second acquisition module is used for acquiring a level signal generated by comparing the reading operation result after the FPGA module executes the reading operation on the chip to be tested;
and the fourth processing module is used for judging whether the erasing interference exists or not according to the level signal.
As can be seen from the above, the erasure interference test system, method and execution device provided in the embodiments of the present application can test a large number of chips to be tested simultaneously by setting the FPGA module, compared with the conventional single MCU which is used for correspondingly testing one chip to be tested, the system and method have obvious efficiency improvement, and meanwhile, after the chip to be tested sends a reading operation instruction, the chip to be tested performs a reading operation, the read result can be compared in the FPGA module, then a high level or a low level is generated according to the comparison result, if the comparison is inconsistent, this means that erasure interference occurs, if the comparison is consistent if the comparison is low, this means that erasure interference does not occur, by this setting, the master control module does not need to generate a reading action, and only needs to generate a reading action after the high level, but the erasure interference occurs relatively less, so the master control module does not need to frequently generate a reading action, and the scheme of the present application has the advantage of high test efficiency compared with the prior art.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
Fig. 1 is a schematic diagram of an erasing interference test system according to an embodiment of the present application.
Fig. 2 is a flowchart of an erasing interference testing method according to an embodiment of the present application.
Fig. 3 is a flowchart of an erasing interference testing method according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an execution device according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an execution device according to an embodiment of the present application.
In the figure: 100. a main control module; 200. an FPGA module; 300. a digital potentiometer module; 400. an analog-to-digital conversion module; 210. a CTRL unit; 220. a SLOT unit; 510. a first acquisition module; 520. a first processing module; 530. a second processing module; 610. a third processing module; 620. a second acquisition module; 630. and a fourth processing module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1 to 5, an erasing interference testing system specifically includes:
the main control module 100, the main control module 100 is used for sending an operation instruction; the main control module 100 may be an MCU.
The FPGA module 200 receives an operation instruction sent by the main control module 100 and forwards the operation instruction to a chip to be tested connected to the FPGA module 200, so that the chip to be tested executes erasing operation or programming operation or reading operation, the FPGA module 200 compares the result of the reading operation and generates a level signal to be transmitted to the main control module 100, and whether erasure interference exists or not is judged according to the level signal. The FPGA module 200 may refer to an FPGA chip, the chip to be tested may refer to a flash chip, or may be another chip that needs to be tested, and an error_flag pin is disposed on the FPGA module 200 and connected to the main control module, and is used for transmitting a level signal.
Through the above technical scheme, a large number of chips to be tested can be tested simultaneously by arranging the FPGA module 200, specifically, 28 chips to be tested can be tested simultaneously in some embodiments, the number of tests is influenced by factors such as pins, logic resources, speed and the like of the development board of the FPGA module 200, compared with the traditional single MCU which correspondingly tests one chip to be tested, the method has obvious efficiency improvement, meanwhile, after the chip to be tested sends a reading operation instruction, the chip to be tested performs reading operation, the result of the reading operation can be compared in the FPGA module 200, a comparator or a comparison circuit can be arranged in the FPGA module 200, read data can be preset in the FPGA module 200, the read result of the chip to be tested after the read operation is completely compared with the preset read data, then a high level or a low level is generated according to the comparison result, if the comparison is inconsistent, the situation of erasure interference appears, if the comparison is consistent is illustrated by the low level, the situation of no erasure interference appears, by the method, the master control module 100 does not need to generate additional reading operation, the result of the reading operation can be compared in the FPGA module 200, the situation that the master control module only needs to read the high level and the reading operation is required to generate the overall, the reading operation is not frequently generated, and the overall situation of the master control module 100 needs to read, and the reading operation is not needs to be frequently read, and the result is greatly improved.
Furthermore, by adopting the technical scheme of the application, the parallel execution characteristic of the FPGA module 200 can be utilized, and the read operation of one sector and the read operation of the other sector can be realized at the same time of erasing and writing the sector.
Further, in still other embodiments, the FPGA module 200 includes at least a CTRL unit 210 and a SLOT unit 220;
the CTRL unit 210 parses the operation instruction and transmits the parsed operation instruction to the SLOT unit 220;
the SLOT unit 220 receives the instruction after the analysis from the CTRL unit 210 and sends the instruction of the corresponding operation to the chip to be tested, so that the chip to be tested executes the erasing operation or the programming operation or the reading operation, and the SLOT unit 220 receives and registers the result information of the chip to be tested executing the reading operation.
The CTRL unit 210 communicates with the main control module 100 through an SPI interface protocol, and the CTRL unit 210 communicates with the SLOT unit 220 through an APB bus and a common direct connection.
The SLOT units 220 are provided in plurality, and each SLOT unit 220 is connected with one chip to be tested through the SPI.
Through the above technical solution, the CTRL unit 210 is mainly responsible for analyzing and registering the operation instruction sent by the main control module 100 based on the SPI protocol, and sending the corresponding operation instruction registered in the register to the SLOT unit 220 through the APB bus and the normal direct connection line, and in addition, the CTRL unit 210 may set the start indication bit register ctrl_flash_en in the SLOT unit 220 through the APB bus, so as to start the ctrl_flash operation.
The SLOT unit 220 obtains a corresponding instruction for operating the chip to be tested through a register direct connection line in the CTRL unit 210, and sends the instruction for operating the chip to be tested to the chip to be tested through the SPI after the instruction bit register ctrl_flash_en is set through an internal state machine, if the instruction is sent to enable the chip to be tested to execute the reading operation, the SLOT unit 220 also receives and registers the reading result output by the chip to be tested in the corresponding register, and when the main control module 100 sends the instruction for reading the reading result of the chip to be tested, the reading result in the register reads the CTRL unit 210 through the APB bus, and sends the information read by the APB bus to the SPI interface of the main control module 100 through the handshake protocol.
The APB bus is used as a communication bridge between the CTRL unit 210 and the SLOT unit 220, and is mainly responsible for transmitting the read result of the chip to be tested registered by the SLOT unit 220 to the CTRL unit 210, besides the above-mentioned enable signal for setting the chip to be tested, where the read rate may reach 4 bytes/each time.
Further, in some embodiments, the device further includes a digital potentiometer module 300, and the digital potentiometer module 300 receives an operation command sent by the main control module 100 and supplies power to the FPGA module 200 and the chip to be tested according to the operation command.
The digital potentiometer module 300 communicates with the main control module 100 through the SPI interface protocol, and the digital potentiometer module 300 may refer to a digital potentiometer, and in some embodiments, the digital potentiometer AD5160 may be used.
Through the above technical solution, the digital potentiometer module 300 supplies power to the FPGA module 200 and the chip to be tested under the control of the main control module 100, and the digital potentiometer module 300 functions as a varistor, changes the resistance value according to the input configuration information, and finally outputs different voltages, because the voltages of the chip to be tested for performing the erase operation, the program operation and the read operation are different when the chip to be tested is tested, so that different voltages are required, and the corresponding power supply configuration information is mainly received by the operation command sent by the main control module 100 based on the SPI protocol.
Further, in some embodiments, the system further includes an analog-to-digital conversion module 400, where the analog-to-digital conversion module 400 collects voltage information of the FPGA module 200 and the chip to be tested, and transmits the voltage information to the main control module 100 through the FPGA module 200, and the main control module 100 controls the digital potentiometer module 300 to adjust the voltage according to the voltage information.
Wherein the analog-to-digital conversion module 400 communicates with the FPGA module 200 through the SPI protocol, the analog-to-digital conversion module 400 may refer to an analog-to-digital conversion chip, and in some embodiments, the analog-to-digital conversion chip ADC108s may be used.
Through the above technical solution, the analog-to-digital conversion module 400 is configured to monitor the voltage output from the digital potentiometer module 300 to the SLOT unit 220 of the FPGA module 200 for mounting the chip to be tested, and then return the voltage to the main control module 100, and adjust the voltage through the digital potentiometer module 300 according to the returned result until reaching the predetermined voltage range.
It should be noted that, in the scheme of the present application, when the chip to be tested is tested, an operation of cyclically erasing-programming-erasing-programming is performed on one sector of the chip to be tested, then a read operation is performed on another sector, and the read operation is between the erase operation and the program operation, that is, during the test, the chip to be tested needs to perform an operation of erasing-reading-programming-reading-erasing.
In a second aspect, the present application further provides an erasing interference testing method, which is used for performing an erasing interference test on the FPGA module 200, where one end of the FPGA module 200 is connected with the main control module 100, and the other end is connected with a chip to be tested, and includes:
S1, acquiring an operation instruction of a main control module 100 to a chip to be tested; the main control module 100 may be an MCU.
S2, analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;
s3, comparing the result of the reading operation to generate a level signal;
according to the technical scheme, firstly, the operation instruction of the chip to be tested is obtained, the operation instruction comprises an instruction for enabling the chip to be tested to execute the erase operation, an instruction for executing the programming operation and an instruction for executing the reading operation, then the operation instruction is analyzed and then forwarded to the chip to be tested, the chip to be tested is enabled to execute the erase operation or execute the programming operation or execute the reading operation, after the chip to be tested executes the reading operation, the reading result is compared, a high-level signal or a low-level signal is generated according to the comparison result, the high-level signal means that the comparison result is inconsistent, the low-level signal means that the comparison result is consistent, and whether the chip to be tested has the erasing interference or not can be judged according to the level signal.
Compared with the traditional means of testing one chip by one MCU, the load of the MCU can be greatly reduced by using the testing method, the main control module 100 can know whether the erasing interference exists or not only according to the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested every time, and the overall testing efficiency is effectively improved.
Further, in still other embodiments, the method further comprises:
if erasure interference occurs, receiving an operation instruction of the main control module 100;
according to the operation instruction of the main control module 100, the read result output by the chip to be tested is registered in the corresponding register and is sent to the main control module 100.
Through the above technical scheme, compared with the prior art, the MCU needs to read the read result of the chip to be tested every time, and then compares the read result with the data of the original read sector of the chip to be tested, when the high level occurs, the main control module 100 only needs to send the operation instruction for reading the read result of the chip to be tested, and the probability of erasure interference is relatively low, so that the main control module 100 does not need to perform the operation most of the time, thereby greatly reducing the burden of the main control module 100 and effectively improving the overall test efficiency.
Further, in still other embodiments, the method further comprises:
acquiring voltage information on a chip to be tested;
the voltage information is sent to the main control module 100, so that the main control module 100 adjusts the voltage.
According to the technical scheme, since the chip to be tested needs to execute the erasing operation, the programming operation and the reading operation, and the operations correspond to different working voltages respectively, the voltage information on the chip to be tested needs to be monitored, the monitored voltage information is sent to the main control module 100, and the main control module 100 correspondingly adjusts the voltage applied to the chip to be tested according to the operation instruction sent to the chip to be tested, so that the chip to be tested can normally execute the operation according to the operation instruction. In addition, by monitoring the voltage on the chip to be tested, whether the chip is in a normal working state can be judged.
Specifically, in some embodiments, the voltage information on the chip to be tested is obtained through the analog-to-digital converter, the main control module 100 generates an operation instruction after receiving the voltage information, and then sends the generated operation instruction to the digital potentiometer, so that the digital potentiometer outputs different voltage values, and further supplies power to the chip to be tested.
Further, in some embodiments, the step of comparing the results of the read operation to generate the level signal includes:
presetting comparison data which are the same as the reading sector of the chip to be tested;
comparing the read result with the comparison data;
and generating a level signal according to the comparison result.
According to the technical scheme, comparison is performed with the read result through preset comparison data, wherein the data identical to the comparison data is required to be written in advance on the chip to be detected, the written data is fixedly read when the chip to be detected executes the read operation, if the comparison results are identical, a low-level signal is generated, and if the comparison results are not identical, a high-level signal is generated.
Specifically, in some embodiments, the first sector on the chip to be tested writes the same data as the comparison data, the main control module 100 sends an erase operation instruction, the chip to be tested performs the erase operation on the second sector, the main control module 100 sends a program operation instruction, the chip to be tested performs the program operation on the second sector, the main control module 100 sends a read operation instruction, the chip to be tested performs the read operation on the first sector, then compares the read result with the comparison data, if the comparison result is the same, the situation that no erase interference occurs is indicated, a low level is generated, if the comparison result is different, the situation that the erase interference occurs is indicated, and a high level is generated.
Further, in some other embodiments, the step of comparing the results of the read operation to generate the level signal includes:
storing programming data which enable the chip to be tested to execute programming operation as comparison data;
comparing the read result with the comparison data;
and generating a level signal according to the comparison result.
Through the technical scheme, when the chip to be tested is controlled to execute the programming operation, the chip to be tested needs to program appointed data in the sectors, the data is programming data, such as 010, and when the chip to be tested circularly executes the programming operation, the programming data is identical, so the programming data can be stored as comparison data, when the chip to be tested executes the first round of programming operation, the same programming data can be programmed in two sectors at the same time, one sector is used as the sector when executing the reading operation, thus the sector can be compared without writing the data in advance, the test can be directly carried out on any two sectors of the chip to be tested, and then the level signal can be generated according to the comparison result.
Specifically, in some embodiments, when the chip to be tested performs a programming operation, the same data is programmed into the second sector in the first sector, and the programming data is stored as comparison data, the main control module 100 sends an erase operation instruction, the chip to be tested performs an erase operation in the first sector, the main control module 100 sends a second and subsequent programming operation instruction, the chip to be tested performs a programming operation in the first sector, the main control module 100 sends a read operation instruction, the chip to be tested performs a read operation in the second sector, and then compares the read result with the comparison data, if the comparison result is the same, it is indicated that no erase interference occurs, a low level is generated, if the comparison result is different, it is indicated that the erase interference occurs, and a high level is generated.
In a third aspect, the present application further provides another method for testing erasing interference, which is used for the main control module 100 to perform erasing interference test, where the main control module 100 is connected with a chip to be tested through the FPGA module 200, and includes:
s10, sending an operation instruction of the chip to be tested to the FPGA module 200, so that the FPGA module 200 sends the analyzed operation instruction to the chip to be tested, and further the chip to be tested performs an erasing operation or a programming operation or a reading operation; wherein the FPGA module 200 may refer to an FPGA chip.
S20, acquiring a level signal generated by comparing a read operation result after the FPGA module 200 executes the read operation on the chip to be tested;
s30, judging whether erasure interference exists according to the level signal.
Through the above technical solution, an operation instruction of the chip to be tested is sent to the FPGA module 200, where the operation instruction includes an instruction for enabling the chip to be tested to perform an erase operation, an instruction for performing a program operation, and an instruction for performing a read operation, the FPGA module 200 analyzes the instructions, and then forwards the analyzed instructions to the chip to be tested to enable the chip to be tested to perform the erase operation or perform the program operation or perform the read operation, after the chip to be tested performs the read operation, the FPGA module 200 registers the read result, and compares the read result, and generates a level signal according to the compared result, and then obtains the level signal and can determine whether the chip to be tested has an erasure interference according to the level of the level signal, if the level signal is high, the compared result is inconsistent, that is, the erasure interference occurs, if the level signal is low, the compared result is consistent, that is, and no erasure interference occurs.
Compared with the means of testing a chip by an MCU in the existing scheme, the test method can know whether the erasing interference exists only according to the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested every time, and then the result is compared according to the reading result so as to judge whether the erasing interference exists, and the overall test efficiency is effectively improved by using the scheme.
Further, in still other embodiments, the method further comprises:
acquiring voltage information of the FPGA module 200 and a chip to be tested;
and adjusting the power supply of the FPGA module 200 and the chip to be tested according to the voltage information.
According to the technical scheme, since the chip to be tested needs to execute the erasing operation, the programming operation and the reading operation, and the operations correspond to different working voltages respectively, the voltage information on the chip to be tested needs to be monitored, the monitored voltage information is sent to the main control module 100, and the main control module 100 correspondingly adjusts the voltage applied to the chip to be tested according to the operation instruction sent to the chip to be tested, so that the chip to be tested can normally execute the operation according to the operation instruction. In addition, by monitoring the voltage on the chip to be tested, whether the chip is in a normal working state can be judged.
Specifically, in some embodiments, the voltage information on the chip to be tested is obtained through the analog-to-digital converter, the main control module 100 generates an operation instruction after receiving the voltage information, and then sends the generated operation instruction to the digital potentiometer, so that the digital potentiometer outputs different voltage values, and further supplies power to the chip to be tested.
Specifically, in some embodiments of the present application, components mainly related to the solution provided in the present application include: MCU, FPGA chip, digital potentiometer, analog-to-digital conversion chip, and chip to be tested.
In this embodiment, the MCU is used as the main control module 100, and communicates with the FPGA chip and the digital potentiometer on the development board through the SPI protocol. The MCU sends operation instructions to the FPGA chip, the operation instructions are analyzed and registered by the FPGA chip and then forwarded to the chip to be tested through an internal state machine to execute corresponding operations, such as erasing operation, programming operation and reading operation.
In this embodiment, the FPGA chip is used as a communication link between the MCU and the chip to be tested, and is mainly divided into two units: a CTRL unit 210 and a SLOT unit 220. The CTRL unit 210 is mainly responsible for analyzing and registering the operation information sent by the MCU based on the SPI protocol, and sending configuration information to the analog-to-digital conversion chip through the SPI protocol, and sending corresponding operation instructions registered in the register to the SLOT unit 220 through the APB bus and the normal direct connection, respectively. The SLOT unit 220 is set by the CTRL unit 210 through the APB bus to set an internal start indication bit register ctrl_flash_en, so as to start ctrl_flash operation, obtain a corresponding instruction for operating the chip to be tested through a direct connection line with a register in the CTRL unit 210, send the instruction to the chip to be tested through the SPI after setting the indication bit register ctrl_flash_en through an internal state machine, if the sent instruction for enabling the chip to be tested to execute a read operation, receive and register data of a read result output by the chip to be tested in a corresponding register, and when the MCU sends the instruction for reading the read result of the chip to be tested, the data in the registers are read to the CTRL unit 210 through the APB bus, and send information read by the APB bus to the SPI interface at the MCU through a handshake protocol.
In this embodiment, the APB bus is used as a communication bridge between the CTRL unit 210 and the SLOT unit 220, and is mainly responsible for transmitting the result of the read result output by the chip under test registered by the SLOT unit 220 to the CTRL unit 210, in addition to the above-mentioned enable signal for setting the chip under test, where the read rate is 4 byte/time.
In this embodiment, the digital potentiometer is mainly responsible for supplying power to the FPGA chip and the chip to be tested on the development board under the control of the MCU, its function is equivalent to a varistor, the resistance value is changed according to the input configuration information, and different voltage values are finally output, and the corresponding power supply configuration information is mainly based on the information sent by the MCU end and received by the SPI protocol.
In this embodiment, the analog-to-digital conversion chip is mainly responsible for collecting voltages of the chip to be tested and the banks of the FPGA chip, and after receiving address information sent by the CTRL unit 210 through the SPI protocol, outputs a corresponding value, and the FPGA chip of the value is sent to the SPI interface of the MCU through the handshake protocol, and the specific voltage value can be obtained through formula conversion. The address information is used for indicating which chip to be tested or the Bank of the FPGA chip, the MCU can further operate the digital potentiometer according to the analog-to-digital conversion chip to supply power to the FPGA chip on the development board and the chip to be tested, and accordingly the analog-to-digital conversion chip and the digital potentiometer can accurately adjust the voltage to be set for the FPGA chip on the development board and the chip to be tested.
In this embodiment, all communications between the MCU and the chip to be tested are based on: the MCU sends an instruction to the FPGA chip, the instruction is forwarded to the chip to be tested through the FPGA chip, and data output by the chip to be tested is also forwarded to the MCU by the FPGA chip.
Specifically, the MCU sends an erase or program command first, after the erase operation, all program operations send a read command to another sector to confirm whether the last erase/program operation interferes with other areas of the memory array block, if the previous "0" is read to be changed into "1", this indicates that the erase/program operation has no influence on the read sector, if the erase/program operation has no change in any bit, a high level is generated and is detected by the MCU, if the erase/program operation further wants to know more interfered information, the MCU sends a command to the FPGA chip to read the read result of the chip to be tested, if the generated level signal is always at a low level, the MCU knows that no interference influence has occurred.
As is obvious from the above description, the MCU confirms whether the erasing interference occurs or not without sending the redundant operation to the FPGA chip, and only if the MCU wants to know more interference information, it will send the instruction for reading the reading result of the chip to be tested to the FPGA chip again.
According to the testing method, the level signals are compared in the FPGA chip and generated, specifically, the level signals generated in the FPGA chip are connected to the pin of the error_flag of interaction between the MCU and the FPGA chip, and whether the erasing interference occurs or not can be known by the MCU without sending an operation instruction, so that the task amount of the MCU is greatly reduced, and finally, more efficient acquisition of information whether the erasing interference occurs or not of the chip to be tested is realized.
In a fourth aspect, the present application further provides an execution apparatus, including:
the first obtaining module 510 is configured to obtain an operation instruction of the main control module 100 for a chip to be tested;
the first processing module 520 is configured to parse the operation instruction and send the parsed instruction to the chip to be tested, so that the chip to be tested performs an erasing operation or a programming operation or a reading operation;
a second processing module 530, configured to compare the result of the read operation to generate a level signal;
through the above technical solution, the first obtaining module 510 firstly obtains the operation instruction of the chip to be tested, where the operation instruction includes an instruction for enabling the chip to be tested to perform the erase operation, an instruction for performing the program operation, and an instruction for performing the read operation, and then the first processing module 520 parses the operation instruction and forwards the operation instruction to the chip to be tested, so that the chip to be tested performs the erase operation or performs the program operation or performs the read operation, after the chip to be tested performs the read operation, the read result is compared, and the second processing module 530 generates a high level signal or a low level signal according to the compared result, where the high level signal means that the compared result is inconsistent, and the low level signal means that the compared result is consistent.
Compared with the traditional means of testing a chip by one MCU, the load of the MCU can be greatly reduced by using the technical means, the main control module 100 can know whether the condition of erasing interference exists only according to the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested every time, and the overall test efficiency is effectively improved.
In a fifth aspect, the present invention provides an execution apparatus, comprising:
the third processing module 610 is configured to send an operation instruction of the chip to be tested to the FPGA module 200, so that the FPGA module 200 sends an operation related instruction to the chip to be tested, and further the chip to be tested performs an erasing operation or a programming operation or a reading operation;
the second obtaining module 620 is configured to obtain a level signal generated by comparing the result of the reading operation after the FPGA module 200 performs the reading operation on the chip to be tested;
the fourth processing module 630 is configured to determine whether there is a erasure disturbance according to the level signal.
Through the above technical solution, the third processing module 610 sends an operation instruction of the chip to be tested to the FPGA module 200, where the operation instruction includes an instruction for enabling the chip to be tested to perform an erase operation, an instruction for performing a program operation, and an instruction for performing a read operation, the FPGA module 200 analyzes the instructions, and then forwards the analyzed instructions to the chip to be tested, so that the chip to be tested performs the erase operation or performs the program operation or performs the read operation, after the chip to be tested performs the read operation, the FPGA module 200 registers the read result, and compares the read result, and generates a level signal according to the comparison result, and then the second obtaining module 620 obtains the level signal, and the fifth processing module 630 can determine whether the chip to be tested has an erasure interference condition according to the level signal, if the level signal is high, it indicates that the comparison result is inconsistent, that an erasure interference condition occurs, and if the level signal is low, it indicates that the comparison result is consistent, that no erasure interference occurs.
Compared with the means of testing a chip by an MCU in the existing scheme, the test method can know whether the erasing interference exists only according to the level signal, the MCU in the existing scheme is not required to read the reading result of the chip to be tested every time, and then the result is compared according to the reading result so as to judge whether the erasing interference exists, and the overall test efficiency is effectively improved by using the scheme.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A system for testing erase and write disturbances, comprising: the device comprises a main control module, an FPGA module connected with the main control module and a chip to be tested connected with the FPGA module; read data are preset in the FPGA module;
the main control module is used for sending an operation instruction and receiving a level signal sent by the FPGA module;
The FPGA module receives an operation instruction sent by the main control module and forwards the operation instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation, the FPGA module compares the result of the reading operation and generates a level signal to be transmitted to the main control module, a high level or a low level is generated according to the comparison result, and the main control module judges whether erasing interference exists or not according to the level signal; when the comparison result is high level, the comparison is inconsistent, the erasing interference is judged to occur, the main control module generates an instruction for reading the reading result of the chip to be tested, the data which is the same as the comparison data is written in advance on the chip to be tested, the reading result of the chip to be tested after the reading operation is executed is compared with the preset reading data, when the comparison result is low level, the comparison is consistent, and the erasing interference is judged not to occur.
2. The system according to claim 1, wherein the FPGA module comprises at least CTRL units and SLOT units;
the CTRL unit analyzes the operation instruction and then transmits the operation instruction to the SLOT unit;
the SLOT unit receives the analyzed instruction from the CTRL unit and sends the instruction of the corresponding operation to the chip to be tested, so that the chip to be tested executes the erasing operation or the programming operation or the reading operation, and the SLOT unit receives and registers the result information of the chip to be tested executing the reading operation.
3. The erasing interference test system according to claim 1, further comprising a digital potentiometer module, wherein the digital potentiometer module receives an operation command sent by the main control module and supplies power to the FPGA module and the chip to be tested according to the operation command.
4. The erasing interference test system according to claim 3, further comprising an analog-to-digital conversion module, wherein the analog-to-digital conversion module collects voltage information of the FPGA module and the chip to be tested, and transmits the voltage information to the main control module through the FPGA module, and the main control module controls the digital potentiometer module to adjust voltage according to the voltage information.
5. The erasing interference test method is used for an FPGA module to carry out erasing interference test, one end of the FPGA module is connected with a main control module, the other end of the FPGA module is connected with a chip to be tested, and read data are preset in the FPGA module, and is characterized by comprising the following steps:
acquiring an operation instruction of a main control module to a chip to be tested;
analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;
And comparing the result of the reading operation to generate a level signal, namely generating a high level or a low level according to the comparison result, so that the main control module judges whether erasure interference exists according to the level signal, particularly, when the comparison result is the high level, the comparison is inconsistent, the occurrence of the erasure interference is judged, the main control module generates an instruction for reading the reading result of the chip to be tested, the same data as the comparison data is written in advance on the chip to be tested, the reading result of the chip to be tested after the reading operation is executed is compared with the preset reading data, when the comparison result is the low level, the comparison is consistent, and the absence of the erasure interference is judged.
6. The method of claim 5, further comprising:
acquiring voltage information on the chip to be tested;
and sending the voltage information to the main control module, so that the main control module adjusts the voltage.
7. The erasing interference test method is used for a main control module to carry out erasing interference test, the main control module is connected with a chip to be tested through an FPGA module, and read data is preset in the FPGA module, and the erasing interference test method is characterized by comprising the following steps:
Sending an operation instruction to the chip to be tested to the FPGA module, so that the FPGA module sends the analyzed operation instruction to the chip to be tested, and further the chip to be tested performs an erasing operation or a programming operation or a reading operation;
acquiring a level signal generated by comparing a read operation result after the FPGA module performs the read operation on the chip to be tested, and particularly generating a high level or a low level according to the comparison result;
judging whether erasure interference exists according to the level signal, specifically, if the comparison result is high level, the comparison is inconsistent, the erasure interference is judged to occur, the main control module generates an instruction for reading the reading result of the chip to be tested, the same data as the comparison data is written in advance on the chip to be tested, the reading result of the chip to be tested after the reading operation is performed is compared with the preset reading data, if the comparison result is low level, the comparison is consistent, and the erasure interference is judged not to occur.
8. The method of claim 7, further comprising:
acquiring voltage information of the FPGA module and the chip to be tested;
And adjusting the power supply of the FPGA module and the chip to be tested according to the voltage information.
9. An execution device for the FPGA module carries out the interference test that erases, FPGA module one end is connected with main control module, and the other end is connected with the chip that awaits measuring, preset the reading data in the FPGA module, its characterized in that includes:
the first acquisition module is used for acquiring an operation instruction of the main control module to the chip to be tested;
the first processing module is used for analyzing the operation instruction and sending the analyzed instruction to the chip to be tested, so that the chip to be tested executes erasing operation or programming operation or reading operation;
the second processing module is used for comparing the result of the reading operation to generate a level signal, specifically, generating a high level or a low level according to the comparison result, so that the main control module judges whether erasure interference exists according to the level signal, specifically, when the comparison result is the high level, the comparison is inconsistent, the erasure interference is judged to occur, the main control module generates an instruction for reading the reading result of the chip to be tested, the same data as the comparison data is written in advance on the chip to be tested, the reading result of the chip to be tested after the reading operation is performed is compared with the preset reading data, and when the comparison result is the low level, the comparison is consistent, and the erasure interference is judged not to occur.
10. An execution device for main control module carries out erasure interference test, main control module passes through the FPGA module and is connected with the chip that awaits measuring, preset read data in the FPGA module, its characterized in that includes:
the third processing module is used for sending an operation instruction of the chip to be tested to the FPGA module, so that the FPGA module sends the relevant operation instruction to the chip to be tested, and the chip to be tested is further enabled to execute an erasing operation or a programming operation or a reading operation;
the second acquisition module is used for acquiring a level signal generated by comparing the reading operation result after the FPGA module executes the reading operation on the chip to be detected, and particularly generating a high level or a low level according to the comparison result;
the fourth processing module is configured to determine whether there is erasure interference according to the level signal, specifically, if the comparison result is a high level, the comparison is inconsistent, it is determined that erasure interference occurs, the main control module generates an instruction for reading the read result of the chip to be tested, data identical to the comparison data is written in advance on the chip to be tested, the read result of the chip to be tested after the read operation is performed is compared with the preset read data, if the comparison result is a low level, the comparison is consistent, and it is determined that erasure interference does not occur.
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