CN112530513A - High-precision flash erasing and writing time acquisition device based on FPGA - Google Patents
High-precision flash erasing and writing time acquisition device based on FPGA Download PDFInfo
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- CN112530513A CN112530513A CN202011632921.1A CN202011632921A CN112530513A CN 112530513 A CN112530513 A CN 112530513A CN 202011632921 A CN202011632921 A CN 202011632921A CN 112530513 A CN112530513 A CN 112530513A
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Abstract
The invention discloses a high-precision flash erasing and writing time acquisition device based on an FPGA (field programmable gate array). in an operation test, after an expansion unit sends operation information to a flash to be tested, the expansion unit starts counting, and each system clock counts once; and simultaneously, the expansion unit sends a status register reading instruction to the flash to be tested, counting is stopped until the expansion unit detects that the status register WIP =0 of the flash to be tested, the counting is multiplied by the clock period of the FPGA chip to obtain the erasing and writing time of the flash to be tested, the period of the FPGA clock is in the magnitude of 10ns, compared with the MCU in the magnitude of us, the FPGA is used for testing the erasing and writing time of the flash to be tested, and the testing precision is greatly improved.
Description
Technical Field
The invention relates to flash test equipment, in particular to a high-precision flash erasing and writing time acquisition device based on an FPGA (field programmable gate array).
Background
NOR FLASH with high reliability, rapid reading and executable codes, also called code type memory chip, is widely applied under the promotion of emerging technologies such as big data, artificial intelligence, Internet of things, cloud computing and the like. With the increasing market share of flash and the increasing demand for data security, the performance of flash chips, especially the service life, is also more demanding, wherein an important evaluation index of the service life is the erasing and writing time of Nor flash.
The erasing time can be used for evaluating the service life of the Nor flash. If the erasing time is stable and is near the typical value in 10 ten thousand erasing operations, the performance of the chip is good in 10 ten thousand erasing life, but if the erasing time is unstable or the deviation typical value is too large, the service life of the chip does not reach the standard, and meanwhile, the real erasing life condition of the tested chip can be known according to what the erasing time is unstable. Therefore, accurate flash erasing and writing time acquisition has a significant influence on improvement and flash service life evaluation.
In the conventional testing device for directly mounting a flash through an MCU (microprogrammed control Unit) to test, the counting statistical clock precision of the erasing time is us magnitude, in erase or program, information is sent to an interface spi of the flash to receive the information, a certain delay exists between pulling high of a chip selection signal, and some delays can even reach half to one clock period, and the situation has great influence on the accurate acquisition of the erasing time, especially when the program time is obtained, under the condition that an erase falling region is 4Kbyte at the minimum, the program needs to be operated 16 times to be completely written, a 64Kbyte block needs to be programmed 256 times, the corresponding delay errors respectively occur 16 times and 256 times, namely, the error reaches 10us to 0.2ms, sometimes, the problem of missing records also occurs, and the erasing time obtained by the testing method is 10ms magnitude, so in the conventional method for directly detecting the erasing time through the MCU, the error of acquiring the erasing and writing time is very large, so the method is not suitable for the design of a high-precision and complex flash life testing system any more.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a high-precision flash erasing and writing time acquisition device based on an FPGA (field programmable gate array), and aims to solve the problems that in the existing test mode of directly detecting flash erasing and writing time through an MCU (microprogrammed control unit), the acquired erasing and writing time has large error and is not suitable for high-precision and complex flash life test.
The technical scheme of the invention is as follows: a high accuracy flash erasing and writing time acquisition device based on FPGA, wherein, includes:
the main control unit sends an instruction to the expansion unit and receives test information of the flash to be tested, which is fed back by the expansion unit;
the expansion unit is used for receiving and analyzing the command sent by the control unit, sending the voltage configuration command to the digital potentiometer, sending a command of corresponding operation to the flash to be tested according to the analyzed command, and reading back a corresponding operation result including erasing and writing time;
the digital potentiometer regulates the voltage to be in a voltage state suitable for the working of the expansion unit;
the flash chip module to be tested is inserted with a flash to be tested;
in the operation test, after the expansion unit sends the operation information to the flash to be tested, the expansion unit starts counting, and each system clock counts once; and simultaneously, the expansion unit sends a status register reading instruction to the flash to be tested, counting is stopped until the expansion unit detects that the WIP bit of the status register of the flash to be tested is 0, the counting is fed back to the main control unit, and the main control unit obtains the operation time of the flash to be tested according to the counting.
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the main control unit adopts an MCU.
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the main control unit adopts an STM32 single chip microcomputer.
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the expansion unit adopts an FPGA chip.
The high-precision flash erasing and writing time obtaining device based on the FPGA comprises an expansion unit, a storage unit and a storage unit, wherein the expansion unit comprises:
the CTRL module receives and analyzes the command sent by the control unit and then sends the command to the SLOT module, and the voltage configuration command is sent to the digital potentiometer;
the SLOT module receives the instruction sent by the CTRL module and sends the instruction of the corresponding operation to the flash to be tested according to the analyzed instruction;
the CTRL module is connected with the main control unit, the CTRL module is connected with the SLOT module, the SLOT module is connected with the flash chip module to be tested, and the CTRL module is connected with the digital potentiometer: in the erasing and programming test operation, after the SLOT module sends the operation information to the flash to be tested, a counter in the SLOT module starts counting, and each system clock counts once; and simultaneously, the SLOT module sends a status register reading instruction to the flash to be tested, counting is stopped until the SLOT module detects that the WIP bit of the status register of the flash to be tested is 0, and the operation time of the flash to be tested is obtained by multiplying the counting by the clock period.
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the main control unit is communicated with the CTRL module through a qspi interface.
The high-precision flash erasing time acquisition device based on the FPGA is characterized in that the CTRL module and the SLOT module are communicated by using an apb bus or a common interface.
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the CTRL module is in communication connection with the digital potentiometer through an spi interface.
The high-precision flash erasing and writing time acquisition device based on the FPGA is characterized in that the SLOT module is in communication connection with the flash chip module to be tested through an SPI (serial peripheral interface).
The high-precision flash erasing and writing time obtaining device based on the FPGA is characterized in that the type of the digital potentiometer is AD 5160.
The invention has the beneficial effects that: according to the high-precision flash erasing and writing time obtaining device based on the FPGA, in an operation test, after the expansion unit sends operation information to a flash to be tested, the expansion unit starts counting, and each system clock counts once; and simultaneously, the expansion unit sends a status register reading instruction to the flash to be tested, counting is stopped until the expansion unit detects that the status register WIP =0 of the flash to be tested, the counting is multiplied by the clock period of the FPGA chip to obtain the erasing and writing time of the flash to be tested, the period of the FPGA clock is in the magnitude of 10ns, compared with the MCU in the magnitude of us, the FPGA is used for testing the erasing and writing time of the flash to be tested, and the testing precision is greatly improved.
Drawings
FIG. 1 is a schematic diagram of an FPGA-based high-precision flash erase-write time acquisition device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a high-precision flash erase/write time obtaining apparatus based on FPGA includes:
the main control unit 1 is used for sending instructions to the expansion unit 2 and receiving test information of the flash 4 to be tested, which is fed back by the expansion unit 2;
the expansion unit 2 is used for receiving and analyzing the instruction sent by the control unit, sending the voltage configuration instruction to the digital potentiometer 3, sending the instruction of corresponding operation to the flash 4 to be tested according to the analyzed instruction, and reading back the corresponding operation result including erasing and writing time;
the digital potentiometer 3 regulates the voltage to be in a voltage state suitable for the working of the expansion unit 2;
the flash chip module to be tested is used for inserting the flash 4 to be tested into the chip module to be tested;
in the operation test, after the expansion unit 2 sends the operation information to the flash to be tested, the expansion unit 2 starts counting, and each system clock counts once; meanwhile, the expansion unit 2 sends a status register reading instruction to the flash 4 to be tested, counting is stopped until the expansion unit 2 detects that the status register WIP =0 of the flash to be tested (namely the WIP bit of the status register is 0), and the operation time of the flash 4 to be tested is obtained according to the counting.
Wherein the operations include program and erase operations.
In some embodiments, the main control unit 1 employs an MCU.
In some specific embodiments, the main control unit 1 adopts an STM32 single chip microcomputer, which mainly sends a corresponding instruction to the extension unit 2, and the STM32 single chip microcomputer communicates with the extension unit 2 through a qspi (Quad SPI, i.e. 4-wire SPI) interface; the instruction (the instruction is not an internal instruction of the flash) is formulated by the control unit 1 and the expansion unit 2 together, and comprises a test instruction, a voltage configuration instruction and other related configuration instructions of the flash 4 to be tested.
In some specific embodiments, the expansion unit 2 is an FPGA chip, and includes:
the CTRL module receives and analyzes the command sent by the control unit 1 and then sends the command to the SLOT module, and the voltage configuration command is sent to the digital potentiometer 3;
the SLOT module receives the instruction sent by the CTRL module and sends the instruction of the corresponding operation to the flash 4 to be tested according to the analyzed instruction;
the CTRL module is connected with the main control unit 1, the CTRL module is connected with the SLOT module, the SLOT module is connected with a flash chip module to be tested, and the CTRL module is connected with the digital potentiometer 3: the method comprises the following steps that a main control unit 1 firstly sends a configuration instruction to an expansion unit 2, a CTRL module in the expansion unit 2 is responsible for analyzing and judging the instruction, firstly, a voltage configuration instruction is sent to a digital potentiometer 3 through spi to adjust voltage to a voltage state suitable for the expansion unit 2 to work, and then information such as the instruction, the address and the transmission mode required in a test flow (the test flow specifically refers to any flow operation of erasing operation, erasing check, programming and programming check of a flash 4 to be tested) is sent to a SLOT module; then the main control unit 1 sends a starting instruction to the FPGA, the CTRL module receives and analyzes the instruction and then sets an indicating register in the SLOT module through an apb bus, so that the SLOT module starts to test the flash 4 to be tested, in the erasing and programming test operation, after the SLOT module sends operation information to the flash 4 to be tested, a counter in the SLOT module starts to count, and each system clock counts once; meanwhile, the SLOT module sends a status register reading instruction to the flash 4 to be tested, counting is stopped until the SLOT module detects that the status register WIP =0 of the flash to be tested (namely the WIP bit of the status register is 0), the counting is multiplied by the clock cycle of the FPGA chip to obtain the erasing and writing time of the flash 4 to be tested, the frequency of the FPGA clock is in the magnitude of 100MHz, namely the period of the clock is in the magnitude of 10ns, compared with the master control unit 1 in the magnitude of us, the FPGA is used for testing the erasing and writing time of the flash 4 to be tested, and the testing precision is greatly improved.
In some embodiments, the CTRL module and the SLOT module communicate with each other using an apb bus or a common interface (the common interface refers to a data interface that needs to be distinguished between the front side and the back side).
In the technical scheme, the apb bus is mainly used for setting an indication register in the SLOT module so as to start the test operation, and sending the result information of the flash 4 to be tested, which is cached in the SLOT module, to the main control unit 1 through the spi interface after the result information is read.
In some specific embodiments, the SLOT module is in communication connection with the flash chip module to be tested through the SPI interface, the test related information analyzed by the CTRL module is sent to the flash 4 to be tested, and the result information of the flash 4 to be tested operated by the SLOT module is read back.
In some embodiments, the digital potentiometer 3 is of the type AD5160, and mainly adjusts the voltage to a voltage state suitable for the FPGA to work.
In some embodiments, the chip module to be tested adopts a flash dedicated base (i.e. a SLOT for plugging a flash chip), a flash 4 to be tested is inserted in the base, and a pin of the base is connected with the SLOT module.
In the technical scheme, in the read-write operation test of the flash 4 to be tested, the condition that whether erasure overtime and programming overtime occur is obtained by comparing the erasing time of the flash 4 to be tested obtained by the system with the erasing time in the specification of the flash 4 to be tested; in the erase check and the program check operations, it is mainly checked whether an error occurs in the erase operation and the program operation, respectively. The testing operation results of all the flash 4 to be tested are read back by the SLOT module and then cached in the RAM inside the testing unit, then the CTRL module reads the cached content through the apb bus and then sends the content to the main control unit 1 through the spi interface, the main control unit 1 carries out bubbling processing (a bubbling algorithm is used for reserving the maximum numerical value) on the erasing time after receiving the result of each test, for example, in the erasing time of ten thousand times, the difference between the average time of each erasing and the maximum time is checked to be large, and if the difference is too large, the jitter is proved to exist), so that the maximum erasing time of the flash 4 to be tested after a series of testing operations can be finally obtained.
The use method provided by the embodiment is a testing method that a task of detecting flash erasing and writing time is transferred to the FPGA by the MCU to complete, and the accuracy of flash erasing and writing time detection is improved to 10ns magnitude from us, so that the service life of the flash chip can be better evaluated according to the high-accuracy erasing and writing time.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. The utility model provides a high accuracy flash erasing and writing time acquisition device based on FPGA which characterized in that includes:
the main control unit sends an instruction to the expansion unit and receives test information of the flash to be tested, which is fed back by the expansion unit;
the expansion unit is used for receiving and analyzing the command sent by the control unit, sending the voltage configuration command to the digital potentiometer, sending a command of corresponding operation to the flash to be tested according to the analyzed command, and reading back a corresponding operation result including erasing and writing time;
the digital potentiometer regulates the voltage to be in a voltage state suitable for the working of the expansion unit;
the flash chip module to be tested is inserted with a flash to be tested;
in the operation test, after the expansion unit sends the operation information to the flash to be tested, the expansion unit starts counting, and each system clock counts once; and simultaneously, the expansion unit sends a status register reading instruction to the flash to be tested, counting is stopped until the expansion unit detects that the WIP bit of the status register of the flash to be tested is 0, the counting is fed back to the main control unit, and the main control unit obtains the operation time of the flash to be tested according to the counting.
2. The FPGA-based high-precision flash erase-write time obtaining device of claim 1, wherein the main control unit adopts an MCU.
3. The FPGA-based high-precision flash erasing time obtaining device as claimed in any one of claims 1 or 2, wherein the main control unit adopts an STM32 single chip microcomputer.
4. The FPGA-based high-precision flash erasing time obtaining device as claimed in claim 1, wherein the expansion unit is an FPGA chip.
5. The FPGA-based high-precision flash erasing time obtaining device as claimed in claim 4, wherein the expansion unit comprises:
the CTRL module receives and analyzes the command sent by the control unit and then sends the command to the SLOT module, and the voltage configuration command is sent to the digital potentiometer;
the SLOT module receives the instruction sent by the CTRL module and sends the instruction of the corresponding operation to the flash to be tested according to the analyzed instruction;
the CTRL module is connected with the main control unit, the CTRL module is connected with the SLOT module, the SLOT module is connected with the flash chip module to be tested, and the CTRL module is connected with the digital potentiometer: in the erasing and programming test operation, after the SLOT module sends the operation information to the flash to be tested, a counter in the SLOT module starts counting, and each system clock counts once; and simultaneously, the SLOT module sends a status register reading instruction to the flash to be tested, counting is stopped until the SLOT module detects that the WIP bit of the status register of the flash to be tested is 0, and the operation time of the flash to be tested is obtained by multiplying the counting by the clock period.
6. The FPGA-based high-precision flash erasing and writing time obtaining device as claimed in claim 5, wherein the main control unit communicates with the CTRL module through a qspi interface.
7. The FPGA-based high-precision flash erasing and writing time obtaining device as claimed in claim 5, wherein the CTRL module and the SLOT module are communicated with each other by using an apb bus or a common interface.
8. The FPGA-based high-precision flash erasing and writing time obtaining device as claimed in claim 5, wherein the CTRL module is in communication connection with the digital potentiometer through a spi interface.
9. The FPGA-based high-precision flash erasing and writing time obtaining device as claimed in claim 5, wherein the SLOT module is in communication connection with the flash chip module to be tested through an SPI interface.
10. The FPGA-based high-precision flash erase-write time obtaining device as claimed in claim 1, wherein the type of the digital potentiometer is AD 5160.
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Address after: 518000 Room 101, building 10, Dayun software Town, 8288 Longgang Avenue, he'ao community, Yuanshan street, Longgang District, Shenzhen City, Guangdong Province Applicant after: XTX Technology Inc. Address before: 518000, Guangdong province Shenzhen Longgang District Henggang street Longgang road 8288, Dayun software town tenth, 1 floor Applicant before: Paragon Technology (Shenzhen) Ltd. |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |