CN111627491A - Flash memory testing module based on USB3.0 and testing method thereof - Google Patents
Flash memory testing module based on USB3.0 and testing method thereof Download PDFInfo
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Abstract
The invention discloses a Flash memory testing module based on USB3.0 and a testing method thereof. The Flash memory test module based on the USB3.0 comprises: the system comprises an FPGA minimum system used for connecting a Flash memory to be tested to test and an upper computer in communication connection with the FPGA minimum system through a USB3.0 interface module, wherein the USB3.0 interface module is used for realizing instruction and data transmission between the FPGA minimum system and the upper computer. The test module provided by the invention can realize Flash memory erasing, reading and writing operations under the control of the FPGA, the operation result is processed by the FPGA and then transmitted to an upper computer for display through a USB3.0, and a user can control the test of the memory through the upper computer and the like.
Description
Technical Field
The invention relates to the technical field of Flash memory test, in particular to a Flash memory test module based on USB3.0 and a test method thereof.
Background
In non-volatile storage media such as Flash, the non-volatile storage media can be divided into different types according to the technical architecture of a chip: nor type and Nand type Flash chips. The Nand Flash-based SSD has the characteristics of high speed, compactness, light weight, low power consumption and high reliability. Nand Flash has no separate address and data bus. It is also widely used in mass data storage.
Due to the manufacturing process of Nand Flash, the addresses of some blocks in the memory chip are not accessible during factory or use, and these blocks are called invalid blocks (i.e., bad blocks). When the chip leaves the factory, a certain number of bad blocks are allowed, the number is generally between 2% and 5%, and the bad blocks cannot be operated when Nand Flash erasing or writing operation is executed. Therefore, to address the problem of identifying bad blocks, manufacturers will mark bad blocks differently when the chips are shipped.
In order to mark bad blocks, a Flash memory needs to be tested, but the current testing means cannot meet the requirements better yet and needs to be further improved.
Disclosure of Invention
The invention aims to solve the problems, and provides a Flash memory testing module based on USB3.0 and a testing method thereof, which can test a large amount of memories, have universality and can be used for testing all similar memories.
The technical scheme adopted for realizing the purpose of the invention is as follows:
a Flash memory test module based on USB3.0 comprises:
the system comprises an FPGA minimum system used for connecting a Flash memory to be tested to test and an upper computer in communication connection with the FPGA minimum system through a USB3.0 interface module, wherein the USB3.0 interface module is used for realizing instruction and data transmission between the FPGA minimum system and the upper computer.
Furthermore, the FPGA minimum system comprises a USB3.0 communication module, an instruction identification module, a Flash control module and a serial communication module, wherein the serial communication module is in communication connection with the Flash memory to be tested through a control bus, an address bus and the total data number, so that the operation of reading and writing data in the Flash memory to be tested is realized.
Further, the upper computer is provided with an operation display interface, and a function menu is displayed on the operation display interface, wherein the function menu comprises starting monitoring, LED control and key monitoring;
after the upper computer is successfully in communication connection with the FPGA minimum system connected with the Flash memory to be tested, the start monitoring is pressed down, and then the test can be started;
the three keys under the control of the LED are respectively an erasing operation, a writing operation and a data reading operation;
and three LED indicating lamps are arranged under the key monitoring, namely waiting, successful operation and failed operation.
Preferably, the chip used in the FPGA minimum system is Xilinx Spartan 6 series FPGA, the model is XC6SLX16, and the FBGA package is 324 pins.
Preferably, the USB3.0 chip used in the USB3.0 interface module is CYUSB3014, and the internal controller EZ-USB FX3 is a USB3.0 peripheral controller developed in recent years by sepala.
The invention also aims to provide a testing method of a Flash memory testing module based on USB3.0, which comprises the following steps:
first, an erase operation test is performed: an erasing operation instruction is output through the upper computer and is transmitted to the FPGA minimum system, and the Flash memory is erased; after the erasure is finished, the FPGA minimum system reads out data in the Flash memory, judges the test result and sends the judgment result to the upper computer for display; if the read data is FFh, the operation is successful;
secondly, performing a write operation test, namely outputting a write operation instruction through the upper computer, transmitting the write operation instruction to the FPGA minimum system, and performing an erasing operation on the Flash memory; after data are written into the Flash memory, the FPGA minimum system executes reading operation, reads the data written into the Flash memory and then compares the data with the written data; if the two are the same, the operation is successful, otherwise, the operation is failed; the comparison result is sent to the upper computer for display.
The working process of the FPGA minimum system is as follows:
when the erasing instruction is executed, the FPGA minimum system sends an erasing control word to the Flash memory, the inside of the Flash memory executes erasing operation, after the erasing operation is finished, the FPGA minimum system sends a reading control word to the Flash memory, the data in the Flash memory is read, the read data is compared in the FPGA minimum system, and the comparison result is transmitted to the upper computer;
when the write instruction is executed, 255 numbers of 1 to 255 can be generated in the FPGA minimum system, and the 255 numbers are transmitted to the write FIFO under the control of the FPGA minimum system; when the internal space of the write FIFO is not empty, the internal data of the write FIFO is read to the FPGA minimum system bus and written into the Flash memory, and after the data is written, the FPGA minimum system sends a read command to read out the data in the Flash memory and compare the data with the number of 1 to 255; and the FPGA minimum system sends the comparison result to an upper computer to complete the test work.
The test module provided by the invention can realize Flash memory erasing, reading and writing operations under the control of the FPGA, the operation result is processed by the FPGA and then transmitted to an upper computer for display through a USB3.0, and a user can control the test of the memory through the upper computer and the like.
Drawings
FIG. 1 is a circuit diagram of a FPGA minimum system of a Flash memory test module based on USB 3.0;
FIG. 2 is an upper computer operation display interface of a Flash memory test module based on USB 3.0.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, the present invention is a minimum FPGA system for connecting a Flash memory to be tested to perform a test, and an upper computer in communication connection with the minimum FPGA system through a USB3.0 interface module, where the USB3.0 interface module is used to implement instruction and data transmission between the minimum FPGA system and the upper computer.
Furthermore, the FPGA minimum system comprises a USB3.0 communication module, an instruction identification module, a Flash control module and a serial communication module, wherein the serial communication module is in communication connection with the Flash memory to be tested through a control bus, an address bus and the total data number, so that the operation of reading and writing data in the Flash memory to be tested is realized.
In the invention, software of the upper computer controls a display interface, as shown in fig. 2, USB3.0 equipment is selected in a device information menu, namely, the upper computer is successfully connected with a test module. After the connection is successful, clicking a key/LED control menu, wherein the menu is divided into three parts: starting monitoring, LED control and key monitoring. And after the upper computer is successfully connected with the test module, pressing down to start monitoring, and then starting the test. The three keys under the control of the LED are respectively an erasing operation, a writing operation and a data reading operation. After the operation is pressed, the instruction can be transmitted to the FPGA through the USB3.0, and the process and the result of the test can be displayed through three LED lamps monitored by the keys.
If the upper computer is successfully connected and starts the monitored state, the LED representing the waiting state always flickers to indicate that the upper computer is ready, and the test can be executed. After the erasing operation or the writing operation is executed, if the operation is successful, the middle LED lamp representing the success flickers, otherwise, the LED lamp representing the failure flickers.
Preferably, the chip used in the FPGA minimum system is Xilinx Spartan 6 series FPGA, the model is XC6SLX16, and the FBGA package is 324 pins.
Preferably, the USB3.0 chip used in the USB3.0 interface module is CYUSB3014, and the internal controller EZ-USB FX3 is a USB3.0 peripheral controller developed in recent years by sepala.
The test module of the invention is divided into two steps for testing:
firstly, carrying out an erasing test, pressing an erasing operation key to start erasing operation, pressing a data reading key after erasing is finished, reading data in a Flash memory, and sending a judgment result to an upper computer after a test result is judged; after the selected Flash memory is erased, the internal data can be changed into FFh, so that if the read data is FFh, the operation is successful;
the process of the erasing operation is equivalent to testing the erasing and reading of the Flash memory.
Secondly, testing the data written in the Flash memory, pressing down and operating keys to enter data, pressing down a data reading key after the data is written in the Flash memory, executing reading operation, reading the written data, comparing the read data with the written data, if the read data is the same as the written data, indicating that the operation is successful, otherwise, failing; the result of the comparison is sent to the upper computer.
In the invention, the working process of the FPGA minimum system is as follows:
when the erasing instruction is executed, the FPGA sends an erasing control word to the Flash memory, the inside of the Flash memory can execute the erasing operation, after the erasing operation is finished, the FPGA sends a reading control word to the Flash memory again, the data in the Flash memory is read, the read data can be compared in the FPGA, and the comparison result can be transmitted to the upper computer through the USB 3.0; when a write instruction is executed, 255 numbers of 1 to 255 are generated inside the FPGA, and the 255 numbers are transmitted to the write FIFO under the control of the FPGA. When the internal space of the write FIFO is not empty, the data in the write FIFO can be read to the FPGA bus, the data can be written into the Flash memory, and after the data is written, the FPGA sends a read command to read the data from the Flash and then compares the data with the number of 1 to 255. And the FPGA sends the comparison result to an upper computer through a USB3.0 chip to complete the test work.
Compared with the prior art, the invention has at least the following advantages:
the test module has great advantages in test speed and reliability, and simultaneously, as the test module adopts USB3.0 large data transmission, various functions such as read-write speed test, read state, ID reading and the like can be expanded, and the application range is very wide.
The FPGA logic function module of the FPGA minimum system is mainly completed through a hardware description language Verilog HDL, and the whole system is divided into two parts: a USB3.0 module and a Flash control module.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A Flash memory test module based on USB3.0 is characterized by comprising:
the system comprises an FPGA minimum system used for connecting a Flash memory to be tested to test and an upper computer in communication connection with the FPGA minimum system through a USB3.0 interface module, wherein the USB3.0 interface module is used for realizing instruction and data transmission between the FPGA minimum system and the upper computer.
2. The Flash memory test module based on the USB3.0 of claim 1, wherein the FPGA minimum system comprises a USB3.0 communication module, an instruction identification module, a Flash control module and a serial communication module, and the serial communication module is in communication connection with the Flash memory to be tested through a control bus, an address bus and the total number of data, so as to realize the operation of reading and writing data in the Flash memory to be tested.
3. The Flash memory test module based on the USB3.0 according to claim 1, wherein the upper computer has an operation display interface, and a function menu is displayed on the operation display interface, wherein the function menu comprises a start monitor, an LED control and a key monitor;
after the upper computer is successfully in communication connection with the FPGA minimum system connected with the Flash memory to be tested, the start monitoring is pressed down, and then the test can be started;
the three keys under the control of the LED are respectively an erasing operation, a writing operation and a data reading operation;
and three LED indicating lamps are arranged under the key monitoring, namely waiting, successful operation and failed operation.
4. The USB 3.0-based Flash memory test module according to claim 1, wherein the chip used in the FPGA minimal system is a Xilinx Spartan 6 series FPGA, model XC6SLX16, 324-pin FBGA package.
5. The USB 3.0-based Flash memory test module of claim 1, wherein the USB3.0 chip used in the USB3.0 interface module is CYUSB3014, and the internal controller EZ-USB FX3 is a USB3.0 peripheral controller developed in recent years by sepala.
6. A testing method of a Flash memory testing module based on USB3.0 is characterized by comprising the following steps:
first, an erase operation test is performed: an erasing operation instruction is output through the upper computer and is transmitted to the FPGA minimum system, and the Flash memory is erased; after the erasure is finished, the FPGA minimum system reads out data in the Flash memory, judges the test result and sends the judgment result to the upper computer for display; if the read data is FFh, the operation is successful;
secondly, performing a write operation test, namely outputting a write operation instruction through the upper computer, transmitting the write operation instruction to the FPGA minimum system, and performing an erasing operation on the Flash memory; after data are written into the Flash memory, the FPGA minimum system executes reading operation, reads the data written into the Flash memory and then compares the data with the written data; if the two are the same, the operation is successful, otherwise, the operation is failed; the comparison result is sent to the upper computer for display.
7. The testing method of the Flash memory testing module based on the USB3.0 of the claim 6, characterized in that the working process of the FPGA minimum system is as follows:
when the erasing instruction is executed, the FPGA minimum system sends an erasing control word to the Flash memory, the inside of the Flash memory executes erasing operation, after the erasing operation is finished, the FPGA minimum system sends a reading control word to the Flash memory, the data in the Flash memory is read, the read data is compared in the FPGA minimum system, and the comparison result is transmitted to the upper computer;
when the write instruction is executed, 255 numbers of 1 to 255 can be generated in the FPGA minimum system, and the 255 numbers are transmitted to the write FIFO under the control of the FPGA minimum system; when the internal space of the write FIFO is not empty, the internal data of the write FIFO is read to the FPGA minimum system bus and written into the Flash memory, and after the data is written, the FPGA minimum system sends a read command to read out the data in the Flash memory and compare the data with the number of 1 to 255; and the FPGA minimum system sends the comparison result to an upper computer to complete the test work.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113409873A (en) * | 2021-06-30 | 2021-09-17 | 芯天下技术股份有限公司 | Erasing and writing interference test system and method and execution device |
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