CN114363145B - BIT fault injection and detection time sequence control method for airborne electronic system - Google Patents
BIT fault injection and detection time sequence control method for airborne electronic system Download PDFInfo
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Abstract
The invention belongs to the technical field of testing verification of an airborne electronic technology, and particularly relates to a BIT fault injection and detection time sequence control method of an airborne electronic system. According to the method, BIT test constraint conditions are set according to the types of three power-on BIT, periodic BIT and maintenance BIT, and by combining functional BIT and performance BIT, the power-on time, task starting time, fault injection time or maintenance instruction sending time of a product are controlled, so that crosstalk of different types of BIT is avoided. The method effectively introduces the test actions of the fault injection system into different BITs of the tested object, avoids the mutual overlapping of fault simulation processes of the different BITs, can accurately develop test implementation work, and has great practical application value.
Description
Technical Field
The invention belongs to the technical field of testing verification of an airborne electronic technology, and particularly relates to a BIT fault injection and detection time sequence control method of an airborne electronic system.
Background
The testability is a design characteristic of the equipment, which can timely and accurately determine the working state of the equipment and effectively isolate the internal faults of the equipment. The testability design is mainly realized through the design of BIT (built-in test), the main BIT in the current electronic system comprises three types, namely a power-on BIT, a period BIT and a maintenance BIT, and the BIT can be divided into a functional BIT and a performance BIT.
The design level of testability is verified and evaluated in the laboratory mainly by means of fault injection tests. Likewise, fault injection in the test oriented test is mainly fault injection for different BIT.
The basic framework of the testability verification is shown in figure 1, and consists of a tested object, a fault injection system and a tested object detection system. Because the tested object and the fault injection system are mutually independent systems, how to introduce the test action of the fault injection system into different BIT of the tested object becomes the key of test success. At present, no coordinated standard operation between fault injection and BIT exists in the industry, so that fault simulation processes of different BIT overlap each other, and test implementation work cannot be accurately carried out.
Disclosure of Invention
The purpose of the invention is that: the time sequence control method can effectively coordinate airborne fault injection and BIT test and avoid mutual overlapping interference of different BIT fault simulation processes.
The technical scheme of the invention is as follows: a BIT fault injection and detection time sequence control method of an airborne electronic system firstly combines the function BIT and the performance BIT according to the types of three power-on BIT, period BIT and maintenance BIT, sets BIT test constraint conditions by controlling the power-on time, the task starting time, the fault injection time or the maintenance instruction sending time of a product, avoids crosstalk of different types of BIT, and achieves BIT fault injection time staggering.
During period BIT oriented test, fault injection and detection processes of the functional BIT are as follows:
step 2.1.1: the tested object is electrified and enters an electrified working state;
Step 2.1.2: the tested object executes the power-on BIT and reports the fault detection result;
Step 2.1.3: the tested object starts a task and enters a task execution state;
step 2.1.4: performing fault injection;
step 2.1.5: executing a period BIT by the tested object and reporting a fault detection result;
Step 2.1.6: and (5) ending fault injection and withdrawing the fault.
During period BIT oriented test, fault injection and detection processes of the performance BIT are as follows:
Step 2.2.1: the tested object is electrified and enters an electrified working state;
Step 2.2.2: the tested object executes the power-on BIT and reports the fault detection result;
step 2.2.3: the tested object starts a task and enters a task execution state;
step 2.2.4: performing a first fault injection;
step 2.2.5: executing a period BIT by the tested object and reporting a fault detection result;
step 2.2.6: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 2.2.7: executing a period BIT by the tested object and reporting a fault detection result;
Step 2.2.8: judging whether fault injection is successful or not, if yes, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
Step 2.2.9: and (5) ending fault injection and withdrawing the fault.
When the BIT test is applied to power-on, the fault injection and detection processes of the functional BIT are as follows:
Step 3.1.1: performing fault injection on the measured object;
Step 3.1.2: the tested object is electrified and enters an electrified working state;
Step 3.1.3: the tested object executes the power-on BIT and reports the fault detection result;
step 3.1.4: the end of the fault injection, the fault is withdrawn,
In step 3.1.2, if the product does not need to be ready for starting time or the starting time is short, the tested object can directly enter the task state after being electrified.
When the BIT test is oriented to power up, the product does not need to prepare starting time, or the starting time is very short, at the moment, fault injection and detection time sequences are shown in fig. 4b, and the specific implementation steps are as follows:
Step 3.2.1: performing fault injection on the measured object;
Step 3.2.2: electrifying a tested object and entering a task state;
step 3.2.3: executing a BIT for one time by the tested object and reporting a fault detection result;
step 3.2.4: and (5) ending fault injection and withdrawing the fault.
When the BIT test is oriented to power-on, the fault injection and detection control process for the performance BIT is as follows:
Step 3.3.1: performing fault injection on the measured object;
Step 3.3.2: the tested object is electrified and enters an electrified working state;
Step 3.3.3: the tested object executes the power-on BIT and reports the fault detection result;
step 3.3.4: the tested object is powered off.
Step 3.3.5: adjusting fault injection stress, and executing the ith, i=2, 3, … …, and performing fault injection;
Step 3.3.6: the tested object is electrified and enters an electrified working state;
Step 3.3.7: the tested object executes the power-on BIT and reports the fault detection result;
Step 3.3.8: the tested object is powered off.
Step 3.3.9: judging whether fault injection is successful or not, if yes, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and withdrawing the fault.
When the BIT is tested for maintenance, the fault injection and detection process of the functional BIT is as follows:
step 4.1.1: performing fault injection on the measured object;
Step 4.1.2: the tested object is electrified and enters an electrified working state;
step 4.1.3: clearing the one-time power-on BIT information;
Step 4.1.4: adjusting the tested object to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.1.7: and (5) ending fault injection and withdrawing the fault.
During maintenance BIT oriented test, the fault injection and detection process of the performance BIT is as follows:
step 4.2.1: the tested object is electrified and enters an electrified working state;
Step 4.2.2: performing fault injection on the measured object;
Step 4.2.3: clear BIT information once (typically periodic BIT);
step 4.2.4: adjusting the tested object to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
Step 4.2.6: the tested object executes maintenance BIT and reports the fault detection result;
step 4.2.7: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 4.2.8: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
step 4.2.9: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.2.10: judging whether fault injection is successful or not, if yes, executing step 4.2.11, otherwise, repeatedly executing step 4.2.7, step 4.2.8, step 4.2.9 and step 4.2.10;
step 4.2.11: and (5) ending fault injection and withdrawing the fault.
The invention has the beneficial effects that: according to the BIT fault injection and detection time sequence control method of the airborne electronic system, BIT test constraint conditions are set by controlling the power-on time, the task starting time, the fault injection time or the maintenance instruction sending time of products according to different BIT types, so that the test actions of the fault injection system are effectively introduced into different BITs of a tested object, the fault simulation processes of the different BITs are prevented from overlapping with each other, test implementation work can be accurately carried out, and the method has a large practical application value.
Drawings
FIG. 1 is a diagram of a basic architecture for a test experiment;
FIG. 2 is a schematic diagram of the present invention;
FIG. 3 is a timing diagram of periodic BIT fault injection;
FIG. 4 is a power-on BIT fault injection timing-functional BIT timing diagram;
FIG. 5 is a power-on BIT fault injection timing-performance BIT timing diagram;
FIG. 6 is a timing diagram of maintenance BIT fault injection.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention selects the transmitting fault of a transceiver of a certain radio station, and performs verification based on the invention. The verification schematic is shown in fig. 2, and the basic information for fault injection is as follows.
| Sequence number | Project | Content | Remarks |
| 1 | Failure mode | Failure to transmit | |
| 2 | Fault detection method | Powering up BIT, periodic BIT, maintenance BIT | |
| 3 | Fault injection mode | Two ends of short-circuit channel unit gain control circuit resistor R48 | |
| 4 | BIT reading mode | Radio station detector | |
| 5 | Expected reporting failure | Failure to transmit |
According to the above, the verification steps for each BIT are designed as follows:
1) Periodic BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing according to a fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and (5) turning off the power supply and stopping the transceiver. (note: step 1, 2 is a functional check before the test, guarantee test subjects are normal).
Step 3: the channel element gain control circuit resistor R48 is connected in an expanded manner by a short-circuit switch. The switch is open and in an "off" state.
Step 4: the test subjects were started by re-energizing.
Step 5: the shorting switch is closed and in an "on" state.
Step 6: observing and reading the fault detection condition of the transceiver through a radio station detector, filling in a data record table, and if the reported result is 'transmitting fault', successfully detecting the fault; otherwise, carrying out problem analysis.
Step 7: stopping the operation of the test object, switching off the short-circuit switch, recovering the state of the product, detecting the functional performance of the product, and filling in a 'functional performance detection table'. If the abnormality is found, processing according to a fault processing program; if the product is normal, the test is ended.
If the 'emission fault' is read, the period BIT design is proved to be correct by the method, and if the 'emission fault' is not read, the period BIT design is proved to be failed by the method.
1) Power-on BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing according to a fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and (5) turning off the power supply and stopping the transceiver. (note: step 1, 2 is a functional check before the test, guarantee test subjects are normal).
Step 3: the channel element gain control circuit resistor R48 is connected in an expanded manner by a short-circuit switch. The switch is closed and in an "on" state.
Step 4: and electrifying again, starting the test object, and loading a low-power transmitting task at the same time.
Step 5: observing and reading the fault detection condition of the primary transceiver through a radio station detector, filling in a data record table, and if the reported result is 'transmitting fault', successfully detecting the fault; otherwise, carrying out problem analysis.
Step 6: stopping the operation of the test object, switching off the short-circuit switch, recovering the state of the product, detecting the functional performance of the product, and filling in a 'functional performance detection table'. If the abnormality is found, processing according to a fault processing program; if the product is normal, the test is ended.
If the 'emission fault' is read, the power-on BIT design is proved to be correct by the method, and if the 'emission fault' is not read, the power-on BIT design is proved to be failed by the method.
2) Maintenance BIT
Step 1: and powering on the transceiver, starting the test object, detecting the functional performance of the test object, processing according to a fault processing program if the functional performance is abnormal, and executing the next step if the functional performance is abnormal.
Step 2: and (5) turning off the power supply and stopping the transceiver. (note: step 1, 2 is a functional check before the test, guarantee test subjects are normal).
Step 3: the channel element gain control circuit resistor R48 is connected in an expanded manner by a short-circuit switch. The switch is closed and in an "on" state.
Step 4: the test subjects were started by re-energizing.
Step 5: and sending a fault clearing instruction to clear all fault information.
Step 6: and adjusting the transceiver to enter a maintenance mode, sending a maintenance self-checking instruction, and starting maintenance self-checking.
Step 7: observing and reading the fault detection condition of the transceiver through a radio station detector, filling in a data record table, and if the reported result is 'transmitting fault', successfully detecting the fault; otherwise, carrying out problem analysis.
Step 8: stopping the operation of the test object, switching off the short-circuit switch, recovering the state of the product, detecting the functional performance of the product, and filling in a 'functional performance detection table'. If the abnormality is found, processing according to a fault processing program; if the product is normal, the test is ended.
If the 'emission fault' is read, the instruction through the method proves that the maintenance BIT design is correct and exists, and if the 'emission fault' is not read, the instruction through the method proves that the maintenance BIT design fails.
In the following, in combination with a specific embodiment, the fault injection and detection timing sequence for three BIT in the testability test of the present invention, the fault injection and detection timing sequences for supporting period BIT, power-up BIT, and maintenance BIT, including the fault injection detection timing sequences for functional BIT and performance BIT, are described.
Example 1:
the main nodes of the fault injection and detection time sequence facing the period BIT in the testability test comprise product power-on time, task starting time and fault injection time. The fault injection and detection timing for a functional BIT is shown in fig. 3a. The specific implementation steps are as follows:
step 2.1.1: the tested object is electrified and enters an electrified working state;
Step 2.1.2: the tested object executes the power-on BIT and reports the fault detection result;
Step 2.1.3: the tested object starts a task and enters a task execution state;
step 2.1.4: performing fault injection;
The node executes fault injection operation, so that the interference of power-on BIT on periodic BIT, which is the most accurate expression in the system after the task is started, can be avoided.
Step 2.1.5: executing a period BIT by the tested object and reporting a fault detection result;
Step 2.1.6: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can realize the unique fault injection verification of the functional period BIT.
Example 2:
The fault injection and detection sequence for the performance BIT is shown in fig. 3b, and the specific implementation steps are as follows:
Step 2.2.1: the tested object is electrified and enters an electrified working state;
Step 2.2.2: the tested object executes the power-on BIT and reports the fault detection result;
step 2.2.3: the tested object starts a task and enters a task execution state;
step 2.2.4: performing a first fault injection;
the initial verification parameters of the performance cycle BIT verification can be determined through the operation of the node.
Step 2.2.5: executing a period BIT by the tested object and reporting a fault detection result;
step 2.2.6: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
the operation of the node can determine the inter-verification parameter variation of the performance period BIT verification in an experimental mode, and search and find the termination parameters.
Step 2.2.7: executing a period BIT by the tested object and reporting a fault detection result;
Step 2.2.8: judging whether fault injection is successful or not, if yes, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
Step 2.2.9: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can realize the unique fault injection verification of the performance cycle BIT.
Example 3: the main nodes of the fault injection and detection time sequence for the power-on BIT in the testability test comprise the power-on time of a product, the task starting time and the fault injection time. The fault injection and detection timing for a functional BIT is shown in fig. 4 a. The specific implementation steps are as follows:
Step 3.1.1: performing fault injection on the measured object;
Step 3.1.2: the tested object is electrified and enters an electrified working state;
Step 3.1.3: the tested object executes the power-on BIT and reports the fault detection result;
The node executes fault injection operation, so that the power-on BIT information can be read in time before the period BIT works, and the coverage of a power-on BIT result after the period BIT appears is avoided.
Step 3.1.4: and (5) ending fault injection and withdrawing the fault.
The unique fault injection verification of the function power-on BIT can be realized through the operation time sequence.
Example 4:
in practical engineering application, some products do not need to be ready for starting time, or the starting time is short, the products can quickly enter a working state after being electrified, and the period BIT read for the first time can be approximately regarded as an electrified BIT detection result. The fault injection and detection sequence is shown in fig. 4 b. The specific implementation steps are as follows:
Step 3.2.1: performing fault injection on the measured object;
the node performs the fault injection operation to solve the problem that the fault injection operation cannot be performed due to the too short interval (typically less than 1 second) between the power-on time and the task start-up time.
Step 3.2.2: electrifying a tested object and entering a task state;
step 3.2.3: executing a BIT for one time by the tested object and reporting a fault detection result;
step 3.2.4: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can realize the engineering optimal approximate fault injection verification of the function power-on BIT.
Example 5:
the fault injection and detection timing for performance BIT is shown in fig. 5. The specific implementation steps are as follows:
Step 3.3.1: performing fault injection on the measured object;
the node performs fault injection operation, can timely read power-on BIT information before periodic BIT work, avoids coverage of a power-on BIT result after the occurrence of periodic BIT, and determines initial verification parameters of performance power-on BIT verification.
Step 3.3.2: the tested object is electrified and enters an electrified working state;
Step 3.3.3: the tested object executes the power-on BIT and reports the fault detection result;
Step 3.3.4: the tested object is powered off. The purpose of the node power-down is to re-acquire the power-up BIT information in subsequent operations, and if the power is not off, the period BIT will cover the power-up BIT information.
Step 3.3.5: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 3.3.6: the tested object is electrified and enters an electrified working state;
Step 3.3.7: the tested object executes the power-on BIT and reports the fault detection result;
Step 3.3.8: the tested object is powered off.
Step 3.3.9: judging whether fault injection is successful or not, if yes, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can be completed in a mode of multiple power-on and power-off, so that the engineering optimal approximate fault injection verification of the function power-on BIT can be realized.
Example 6:
The fault injection and detection time sequence facing to maintenance BIT in the testability test is characterized in that: the main node comprises product power-on time, task starting time, fault injection time and maintenance instruction sending time. The fault injection and detection timing for a functional BIT is shown in fig. 6 a. The specific implementation steps are as follows:
step 4.1.1: performing fault injection on the measured object;
the node is used for engineering operation safety, fault injection is performed before power-on, the influence on a test object can be reduced to the greatest extent, otherwise, the node is easy to damage after power-on during fault injection.
Step 4.1.2: the tested object is electrified and enters an electrified working state;
step 4.1.3: clearing BIT information once (typically power-on BIT);
The process of powering up BIT is the same, and the result of detecting the powering up BIT is generated at this time, so that the BIT is cleared in time, so as to prevent the power up BIT from interfering with the maintenance BIT.
Step 4.1.4: adjusting the tested object to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.1.7: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can realize the engineering safest and accurate fault injection verification of the function maintenance BIT.
Example 7:
The fault injection and detection timing for performance BIT is shown in fig. 6 b.
The specific implementation steps are as follows:
step 4.2.1: the tested object is electrified and enters an electrified working state;
Step 4.2.2: performing fault injection on the measured object;
the node is used for engineering operation safety, fault injection is performed before power-on, the influence on a test object can be reduced to the greatest extent, otherwise, the node is easy to damage after power-on during fault injection.
Step 4.2.3: clear BIT information once (typically periodic BIT);
The process is the same as the process of powering up BIT, and a power-up BIT detection result is generated at the moment, so that the power-up BIT is cleared timely, the purpose is to prevent interference of the power-up BIT on maintenance BIT, and meanwhile, initial verification parameters of performance maintenance BIT verification are determined.
Step 4.2.4: adjusting the tested object to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
the information acquired after issuing the maintenance instruction is the most accurate expression of the maintenance BIT.
Step 4.2.6: the tested object executes maintenance BIT and reports the fault detection result;
step 4.2.7: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 4.2.8: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
the information acquired after issuing the maintenance instruction is the most accurate expression of the maintenance BIT.
Step 4.2.9: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.2.10: judging whether fault injection is successful or not, if yes, executing step 4.2.11, otherwise, repeatedly executing step 4.2.7, step 4.2.8, step 4.2.9 and step 4.2.10;
step 4.2.11: and (5) ending fault injection and withdrawing the fault.
The operation time sequence can realize the engineering safest and accurate fault injection verification of the performance maintenance BIT.
In summary, according to the three types of power-on BIT, period BIT and maintenance BIT, the invention combines functional BIT and performance BIT, and sets BIT test constraint conditions by controlling the power-on time, task starting time, fault injection time or maintenance instruction sending time of a product, thereby avoiding crosstalk of different types of BIT, realizing BIT fault injection time staggering, and avoiding incorrect verification caused by overlapping of different BIT in conventional verification.
The foregoing is merely a detailed description of the invention, which is not a matter of routine skill in the art. However, the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (3)
1. The BIT fault injection and detection time sequence control method for the airborne electronic system is characterized in that BIT test constraint conditions are set by controlling the power-on time, the task starting time, the fault injection time or the maintenance instruction sending time of a product according to the types of three power-on BITs, periodic BITs and maintenance BITs and combining the functional BITs and the performance BITs, crosstalk of different types of BITs is avoided, and BIT fault injection time staggering is realized;
when the BIT test is applied to power up, the product does not need to prepare starting time, or the starting time is very short, at the moment, fault injection and detection time sequences are executed, and the specific implementation steps are as follows:
Step 3.2.1: performing fault injection on the measured object;
Step 3.2.2: electrifying a tested object and entering a task state;
step 3.2.3: executing a BIT for one time by the tested object and reporting a fault detection result;
step 3.2.4: ending the fault injection and withdrawing the fault;
during period BIT oriented test, fault injection and detection processes of the functional BIT are as follows:
step 2.1.1: the tested object is electrified and enters an electrified working state;
Step 2.1.2: the tested object executes the power-on BIT and reports the fault detection result;
Step 2.1.3: the tested object starts a task and enters a task execution state;
step 2.1.4: performing fault injection;
step 2.1.5: executing a period BIT by the tested object and reporting a fault detection result;
step 2.1.6: ending the fault injection and withdrawing the fault;
during period BIT oriented test, fault injection and detection processes of the performance BIT are as follows:
Step 2.2.1: the tested object is electrified and enters an electrified working state;
Step 2.2.2: the tested object executes the power-on BIT and reports the fault detection result;
step 2.2.3: the tested object starts a task and enters a task execution state;
step 2.2.4: performing a first fault injection;
step 2.2.5: executing a period BIT by the tested object and reporting a fault detection result;
step 2.2.6: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 2.2.7: executing a period BIT by the tested object and reporting a fault detection result;
Step 2.2.8: judging whether fault injection is successful or not, if yes, executing step 2.2.9, otherwise, repeatedly executing step 2.2.6, step 2.2.7 and step 2.2.8;
step 2.2.9: ending the fault injection and withdrawing the fault;
when the BIT is tested for maintenance, the fault injection and detection process of the functional BIT is as follows:
step 4.1.1: performing fault injection on the measured object;
Step 4.1.2: the tested object is electrified and enters an electrified working state;
step 4.1.3: clearing the one-time power-on BIT information;
Step 4.1.4: adjusting the tested object to enter a maintenance mode;
step 4.1.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
step 4.1.6: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.1.7: ending the fault injection and withdrawing the fault;
During maintenance BIT oriented test, the fault injection and detection process of the performance BIT is as follows:
step 4.2.1: the tested object is electrified and enters an electrified working state;
Step 4.2.2: performing fault injection on the measured object;
Step 4.2.3: clear BIT information once (typically periodic BIT);
step 4.2.4: adjusting the tested object to enter a maintenance mode;
step 4.2.5: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
Step 4.2.6: the tested object executes maintenance BIT and reports the fault detection result;
step 4.2.7: adjusting fault injection stress, and executing the ith (i=2, 3, … …) th fault injection;
Step 4.2.8: issuing a maintenance instruction to the tested object, and executing maintenance BIT;
step 4.2.9: the tested object executes maintenance BIT and reports the fault detection result;
Step 4.2.10: judging whether fault injection is successful or not, if yes, executing step 4.2.11, otherwise, repeatedly executing step 4.2.7, step 4.2.8, step 4.2.9 and step 4.2.10;
step 4.2.11: and (5) ending fault injection and withdrawing the fault.
2. The method for BIT fault injection and detection timing control of an on-board electronic system according to claim 1, wherein during power-up BIT test, the fault injection and detection process of the functional BIT is as follows:
Step 3.1.1: performing fault injection on the measured object;
Step 3.1.2: the tested object is electrified and enters an electrified working state;
Step 3.1.3: the tested object executes the power-on BIT and reports the fault detection result;
step 3.1.4: the end of the fault injection, the fault is withdrawn,
In step 3.1.2, if the product does not need to be ready for starting time or the starting time is short, the tested object can directly enter the task state after being electrified.
3. The method for BIT fault injection and detection timing control of an on-board electronic system according to claim 1, wherein during power-up BIT test, the fault injection and detection control process for performance BIT is as follows:
Step 3.3.1: performing fault injection on the measured object;
Step 3.3.2: the tested object is electrified and enters an electrified working state;
Step 3.3.3: the tested object executes the power-on BIT and reports the fault detection result;
Step 3.3.4: powering off the tested object;
Step 3.3.5: adjusting fault injection stress, and executing the ith, i=2, 3, … …, and performing fault injection;
Step 3.3.6: the tested object is electrified and enters an electrified working state;
Step 3.3.7: the tested object executes the power-on BIT and reports the fault detection result;
step 3.3.8: powering off the tested object;
Step 3.3.9: judging whether fault injection is successful or not, if yes, executing step 3.3.10, otherwise, repeatedly executing step 3.3.5, step 3.3.6, step 3.3.7, step 3.3.8 and step 3.3.9;
step 3.3.10: and (5) ending fault injection and withdrawing the fault.
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