CN107478925A - A kind of touch key-press test system and method based on ATMEL - Google Patents
A kind of touch key-press test system and method based on ATMEL Download PDFInfo
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- CN107478925A CN107478925A CN201710565496.0A CN201710565496A CN107478925A CN 107478925 A CN107478925 A CN 107478925A CN 201710565496 A CN201710565496 A CN 201710565496A CN 107478925 A CN107478925 A CN 107478925A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
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Abstract
The invention discloses a kind of touch key-press test system and method based on ATMEL, the system includes embeded processor, programming device CPLD and programmable device FPGA, wherein, embeded processor is connected to the CPLD, CPLD is connected to FPGA again, and SI5338 clock chips are additionally provided between embeded processor and FPGA, to provide clock signal for the two；The embeded processor is also associated with DDR and FLASH.The present invention can greatly improve the comprehensive of chip MDIO interface testings, save the testing time, break away from the artificial influence of test result, reduce the requirement to tester's technical capability.
Description
Technical field
The invention belongs to touch key-press technical field, the side view system and method for more particularly to a kind of touch key-press.
Background technology
In recent years, with the raising that people are required quality of the life, as the touch-control skill that can most improve panel operation experience
Art has obtained the support of numerous manufacturers, such as mobile phone, tablet personal computer, notebook computer, white domestic appliances, Industry Control, elevator production
Manufacturer etc., and each requirement of application to touch key-press technology has different demands.It is similar with flat board and notebook, in hand
In machine application, touch controlled key is required to resist outside charger interference, it is also necessary to answers sensitivity caused by direct-to-ground capacitance deficiency
Reduction problem, and good fortune blackberry lily are disturbed；In white domestic appliances application, touch controlled key is required to resist electricity caused by motor rotation etc.
Magnetic disturbance, and the moment surge of machine startup；, it is necessary to resist high current electromagnetic induction interference in industrial control field application
Deng.
In recent years, with the raising that people are required quality of the life, as the touch-control skill that can most improve panel operation experience
Art has obtained the support of numerous manufacturers, such as mobile phone, tablet personal computer, notebook computer, white domestic appliances, Industry Control, elevator production
Manufacturer etc., and each requirement of application to touch key-press technology has different demands.It is similar with flat board and notebook, in hand
In machine application, touch controlled key is required to resist charger interference outer, it is also necessary to tackles sensitive caused by direct-to-ground capacitance deficiency
Reduction problem is spent, and good fortune blackberry lily is disturbed；In white domestic appliances application, touch controlled key is required to resist caused by motor rotation etc.
Electromagnetic distu, and the moment surge of machine startup；, it is necessary to resist high current electromagnetic induction interference in industrial control field application
Deng.
The content of the invention
Based on this, therefore the present invention primary mesh be to provide a kind of touch key-press test system based on ATMEL and side
Method, the system and method can support multi-mode to detect, and support a variety of inductive mode interval detections, analysis, measurement scheme is each
Kind complicated applications environment, the stability of prioritization scheme, enable more easily to be used in various application scenarios.
It is to provide a kind of touch key-press test system and method based on ATMEL, this is another mesh of the present invention
System and method can greatly improve the comprehensive of chip MDIO interface testings, save the testing time, and it is artificial to break away from test result
Influence, reduce the requirement to tester's technical capability.
To achieve the above object, the technical scheme is that：
A kind of touch key-press test system based on ATMEL, it is characterised in that the system includes embeded processor, can
Programming device CPLD and programmable device FPGA, wherein：
Embeded processor, it is integrated with serial port module, is the control core of whole system, and host computer is realized by serial ports
With the interaction of processor, order of the processor to host computer is simply decoded, and controls the operation of corresponding device.
Programming device CPLD, its prime responsibility are to carry out initial configuration to whole system, preserve FPGA configuration text
Part so that program will not lose after system power failure.
Programmable device FPGA, it is the executor of whole system, the order sum that FPGA reception processing devices send over
It is believed that breath, is handled information, information, then the letter that device is returned are sent to device under test with the rule that programmer is set
Breath feeds back to processor.
Wherein, embeded processor is connected to the CPLD, and CPLD is connected to FPGA, and embeded processor and FPGA again
Between be additionally provided with SI5338 clock chips, to provide clock signal for the two；The embeded processor be also associated with DDR and
FLASH。
Further, the embeded processor is connected with RS232 interface, FE and SFP interfaces.
FPGA described further is connected with SMA, and SMA connectors are that a kind of the coaxial of widely used small-sized threaded connection connects
Device is connect, is used for receiving external clock input signal by SMA and is output to outside to FPGA or by FPGA clock signal.
A kind of touch key-press method of testing based on ATMEL, this method comprise the following steps：
101st, start, system electrification, initialized；
102nd, judge side view main device still from device；
103rd, according to test request, tested to main device or from device.
In 103 step, when testing main device, comprise the following steps that：
10311st, the interface formed with TK selects test item；
10312nd, run, transmit control instruction and pattern data；
10313rd, processor is handled instruction and data, and FPGA receives pattern data；
10314th, judge whether output drive, otherwise continue the step, be then to carry out in next step；
10315th, DUT, which is received, encourages and responds；
10316th, FPGA monitoring response and data storage, processor read data and carry out preliminary treatment；
10317th, host computer judges and result is write EXCEL file；
10318th, judge whether test item is completed, completion then terminates, and otherwise returns to 10312 steps and completes other tests
.
In 103 step, test from device when, comprise the following steps that：
10321st, test item is selected；
10322nd, run, transmit control instruction and specific data；
10323rd, processor receives to instruct and make accordingly；
10324th, FPGA starts working, and waits main device action；
10325th, FPGA counts main device information and reports to processor；
10326th, processor reads FPGA feedacks；
10327th, host computer is judged data and writes EXCEL file；
10328th, judge whether test item is completed, completion then terminates, and otherwise returns to 10322 steps and completes other tests
.
Further, during system testing, corresponding test pattern storehouse first is editted in host computer, TCL scripts is then run, leads to
Cross serial ports and the content in pattern storehouse is sent to CPU, CPU is put into content in FPGA buffer by bus again, and FPGA is received
To CPU write command and detect buffer for sky, FPGA then to pattern parsing be reduced to actual clock and data-signal,
The tested device of driving carries out associative operation, while FPGA can capture the response situation from device, and relevant information is transferred to handle
Device passes to host computer and handled, and judged result is written in Microsoft Excel by TCL afterwards.
Further, the pattern data frame packet contains PRED, STRT, OP, PHY AD, REG AD, TA, DATA and IDLE,
Wherein, PRED is frame swynchronization code, in this state MAC MDIO can be driven to send out 32 continuous ' 1 ' to PHY devices, for device
Synchronous communication；STRT is start of frame delimiter, and MAC outputs " 01 " bit notification PHY represents that frame operation starts；OP is frame operation
Code, bit " 01 " represent that this frame is a write operation requests, and bit " 10 " represents that this frame is disposable read operation request；PHY AD
It is PHY address of devices, is 5bit bit wides, compared with each PHY devices are 5 bit in the address of oneself and this, if matching
Response operation below, ignores operation below if mismatching, and 5 bits determine can at most to support 32 PHY chips
Configuration；REG AD are PHY register address, are 5 bit bit wides, for selecting certain in 32 registers inside PHY chip
The address of individual register；TA is State Transferring domain, common 2bit, and if read operation, then the first bit sends out height by MDIO modules
Resistance state, the second bit put ' 0 ' by PHY chip to MDIO signals, and if write operation, then MDIO signals are carried out by MDIO modules
Control, it is continuous to export " 10 " two bits；DATA is the register data domain of frame, totally 16 bit, is then PHY if read operation
The serial data of MDIO modules is sent to, is then sent to PHY serial data for MDIO modules if write operation；After IDLE is frame end
Idle condition, now MDIO passive drives, locate high-impedance state, but be typically at high level with pull-up resistor.
The touch key-press test system and method based on ATMEL that the present invention is realized, the system and method can be significantly
The comprehensive of chip MDIO interface testings is improved, the testing time is saved, breaks away from the artificial influence of test result, reduce to tester
The requirement of member's technical capability.
Meanwhile the system and method can be used with complex function, by Programming with Pascal Language, be allowed to support a variety of sensings
Mode spacing detects, and analysis, measurement scheme is in various complicated applications environment, in face of the data exported during various noises, using more
Kind adaptive filter algorithm, the stability of prioritization scheme, enable more easily to be used in various application scenarios.
Brief description of the drawings
Fig. 1 is the schematic diagram of the transmission of a bit high level.
Fig. 2 is the system architecture diagram that the present invention is implemented.
Fig. 3 is the test job flow chart that the present invention is implemented.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In ATMEL touch key-press test, MDIO buses are actually related to when working to main device and corresponding
From device, in order to which to being tested from device PHY and main device MAC, instrument can be operated in both of which, when test PHY devices
During part, instrument simulates MAC main devices to being managed from device PHY, when testing MAC devices, instrument simulation PHY devices pair
MAC devices are responded, and are described so being divided into below from device and main device.
During as main device to being tested from device MDIO interfaces, in order to know PHY device MDIO interfaces in detail
Parameters, FPGA need to send corresponding time series data to from device, now just need to carry out pattern data configuration, no matter
It is clock or data, is the level of corresponding time corresponding to reality, Fig. 1 show the transmission of a bit high level.
It can be seen that one Bit of transmission data can essentially point three parts construct, each section is all corresponding
MDC, MDIO level and corresponding duration, each section can preserve data, highest using the register of one 32
Two preservation MDC and MDIO value, middle three can be used as extension bits, the last 25 preservation positions as the time.
Thus, the structured flowchart for the test system that the present invention is realized is as shown in Figure 2.Shown in figure, test system includes
Have：
Embeded processor, it is CPU, it is integrated with serial port module, is the control core of whole system, and host computer passes through string
Cause for gossip is existing and the interaction of processor, order of the processor to host computer are simply decoded, and controls the operation of corresponding device.
Programming device CPLD, its prime responsibility are to carry out initial configuration to whole system, preserve FPGA configuration text
Part so that program will not lose after system power failure.
Programmable device FPGA, it is the executor of whole system, the order sum that FPGA reception processing devices send over
It is believed that breath, is handled information, information, then the letter that device is returned are sent to device under test with the rule that programmer is set
Breath feeds back to processor.
CPU is connected to the CPLD, and CPLD is connected to FPGA again, and SI5338 clocks are additionally provided between CPU and FPGA
Chip, to provide clock signal for the two；The CPU is also associated with DDR and FLASH.
CPU is also associated with RS232 interface, FE and SFP interfaces, and FPGA is connected with SMA, and SMA connectors are that a kind of application is wide
The coaxial connector of general small-sized threaded connection, it is used for receiving external clock input signal to FPGA or by FPGA by SMA
Clock signal be output to outside.
With reference to described in Fig. 3, the present invention realizes the touch key-press method of testing based on ATMEL, comprises the following steps：
101st, start, system electrification, initialized；
102nd, judge side view main device still from device；
103rd, according to test request, tested to main device or from device.
In 103 step, when testing main device, comprise the following steps that：
10311st, the interface formed with TK selects test item；
10312nd, run, transmit control instruction and pattern data；
10313rd, processor is handled instruction and data, and FPGA receives pattern data；
10314th, judge whether output drive, otherwise continue the step, be then to carry out in next step；
10315th, DUT, which is received, encourages and responds；
10316th, FPGA monitoring response and data storage, processor read data and carry out preliminary treatment；
10317th, host computer judges and result is write EXCEL file；
10318th, judge whether test item is completed, completion then terminates, and otherwise returns to 10312 steps and completes other tests
.
In 103 step, test from device when, comprise the following steps that：
10321st, test item is selected；
10322nd, run, transmit control instruction and specific data；
10323rd, processor receives to instruct and make accordingly；
10324th, FPGA starts working, and waits main device action；
10325th, FPGA counts main device information and reports to processor；
10326th, processor reads FPGA feedacks；
10327th, host computer is judged data and writes EXCEL file；
10328th, judge whether test item is completed, completion then terminates, and otherwise returns to 10322 steps and completes other tests
.
During system testing, corresponding test pattern storehouse first is editted in host computer, then runs TCL scripts, TCL is a kind of
Command lanuage based on character string, it can the stable operation under windows platforms, the content in pattern storehouse is sent to by serial ports
CPU, CPU are put into content in FPGA buffer by bus again, and FPGA receives CPU write command and detects buffer not
For sky, FPGA is then reduced to actual clock and data-signal to pattern parsing, drives tested device to carry out associative operation,
FPGA can capture the response situation from device simultaneously, transfer to processor to pass to host computer relevant information and handled, sentenced afterwards
Disconnected result is written in Microsoft Excel by TCL.
As from device when, host computer need not edit send pattern data, after corresponding hardware environment is put up, operation
Script, processor and then notifies FPGA to carry out coherent detection work, is set by host computer, when FPGA can control the clock to arrive
When output data, simulation special circumstances such as master clock dragged down from device, related feedback information is obtained by FPGA again
And submit host computer to handle, so as to realize the interaction of an automation.
The data structure of pattern data is as follows:
Wherein：
1、PRED:Frame swynchronization code, in this state MAC MDIO can be driven to send out 32 continuous ' 1 ' to PHY devices, be used for
The synchronous communication of device.
2、STRT：Start of frame delimiter, MAC outputs " 01 " bit notification PHY represent that frame operation starts.
3、OP：Frame command code, bit " 01 " represent that this frame is a write operation requests, and bit " 10 " represents this frame for once
Property read operation request.
4、PHY AD：PHY address of devices, is 5bit bit wides, and each PHY devices enter 5 bit in the address of oneself and this
Row compares, and operation below is responded if matching, and operation below is ignored if mismatching, and 5 bits determine at most prop up
Hold the configuration of 32 PHY chips.
5、REG AD：PHY register address, it is 5 bit bit wides, for selecting in 32 registers inside PHY chip
Some register address.
6、TA:State Transferring domain, common 2bit, if read operation, then the first bit sends out high-impedance state by MDIO modules,
Second bit puts ' 0 ' by PHY chip to MDIO signals, and if write operation, then MDIO signals are controlled by MDIO modules, even
Continuous output " 10 " two bits.
7、DATA：The register data domain of frame, totally 16 bit, if read operation, is then sent to the serial of MDIO modules for PHY
Data, PHY serial data is then sent to for MDIO modules if write operation.
8、IDLE：Idle condition after frame end, now MDIO passive drives, locate high-impedance state, but general pull-up electricity
Resistance is at high level.
In a word, the present invention can greatly improve the comprehensive of chip MDIO interface testings, save the testing time, break away from test
As a result artificial influence, the requirement to tester's technical capability is reduced.
Meanwhile the system and method can be used with complex function, by Programming with Pascal Language, be allowed to support a variety of sensings
Mode spacing detects, and analysis, measurement scheme is in various complicated applications environment, in face of the data exported during various noises, using more
Kind adaptive filter algorithm, the stability of prioritization scheme, enable more easily to be used in various application scenarios.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (8)
1. a kind of touch key-press test system based on ATMEL, it is characterised in that the system includes embeded processor, can compiled
Journey device CPLD and programmable device FPGA,
Embeded processor, it is integrated with serial port module, is the control core of whole system, and host computer is realized and located by serial ports
The interaction of device is managed, order of the processor to host computer is simply decoded, and controls the operation of corresponding device.
Programming device CPLD, its prime responsibility are to carry out initial configuration to whole system, preserve FPGA configuration file, make
Program will not lose after obtaining system power failure；
Programmable device FPGA, it is the executor of whole system, the order sum that FPGA reception processing devices send over it is believed that
Breath, is handled information, and information is sent to device under test with the rule that programmer is set, then the information of device return is anti-
Feed processor.
Wherein, embeded processor is connected to the CPLD, and CPLD is connected to FPGA again, and between embeded processor and FPGA
SI5338 clock chips are additionally provided with, to provide clock signal for the two；The embeded processor be also associated with DDR and
FLASH。
2. the touch key-press test system based on ATMEL as claimed in claim 1, it is characterised in that the embeded processor
It is connected with RS232 interface, FE and SFP interfaces.
3. the touch key-press test system based on ATMEL as claimed in claim 1, it is characterised in that the FPGA is connected with
SMA。
4. a kind of touch key-press method of testing based on ATMEL, it is characterised in that this method comprises the following steps：
101st, start, system electrification, initialized；
102nd, judge side view main device still from device；
103rd, according to test request, tested to main device or from device.
5. the touch key-press method of testing based on ATMEL as claimed in claim 4, it is characterised in that in 103 step,
When testing main device, comprise the following steps that：
10311st, the interface formed with TK selects test item；
10312nd, run, transmit control instruction and pattern data；
10313rd, processor is handled instruction and data, and FPGA receives pattern data；
10314th, judge whether output drive, otherwise continue the step, be then to carry out in next step；
10315th, DUT, which is received, encourages and responds；
10316th, FPGA monitoring response and data storage, processor read data and carry out preliminary treatment；
10317th, host computer judges and result is write EXCEL file；
10318th, judge whether test item is completed, completion then terminates, and otherwise returns to 10312 steps and completes other test items.
6. the touch key-press method of testing based on ATMEL as claimed in claim 4, it is characterised in that in 103 step,
Test from device when, comprise the following steps that：
10321st, test item is selected；
10322nd, run, transmit control instruction and specific data；
10323rd, processor receives to instruct and make accordingly；
10324th, FPGA starts working, and waits main device action；
10325th, FPGA counts main device information and reports to processor；
10326th, processor reads FPGA feedacks；
10327th, host computer is judged data and writes EXCEL file；
10328th, judge whether test item is completed, completion then terminates, and otherwise returns to 10322 steps and completes other test items.
7. the touch key-press method of testing based on ATMEL as claimed in claim 4, it is characterised in that during system testing, first exist
Host computer edits corresponding test pattern storehouse, then runs TCL scripts, the content in pattern storehouse is sent to CPU by serial ports,
CPU is put into content in FPGA buffer by bus again, and FPGA, which receives CPU write command and detects buffer, is not
Sky, FPGA are then reduced to actual clock and data-signal to pattern parsing, drive tested device to carry out associative operation, together
When FPGA can capture response situation from device, transfer to processor to pass to host computer relevant information and handled, judged afterwards
As a result it is written to by TCL in Microsoft Excel.
8. the touch key-press method of testing based on ATMEL as claimed in claim 7, it is characterised in that the pattern data frame packet
Containing PRED, STRT, OP, PHY AD, REG AD, TA, DATA and IDLE, wherein, PRED is frame swynchronization code, in this state MAC
MDIO can be driven to send out 32 continuous ' 1 ', the synchronous communication for device to PHY devices；STRT is start of frame delimiter, MAC
Output " 01 " bit notification PHY represents that frame operation starts；OP is frame command code, and bit " 01 " represents that this frame please for a write operation
Ask, bit " 10 " represents that this frame is disposable read operation request；PHY AD are PHY address of devices, are 5bit bit wides, each PHY
Compared with device is all 5 bit in the address of oneself and this, operation below is responded if matching, after ignoring if mismatching
The operation in face；REG AD are PHY register address, are 5 bit bit wides, for selecting in 32 registers inside PHY chip
Some register address；TA is State Transferring domain, common 2bit, and if read operation, then the first bit is sent by MDIO modules
Go out high-impedance state, the second bit puts ' 0 ' by PHY chip to MDIO signals, if write operation, then MDIO signals by MDIO modules Lai
It is controlled, it is continuous to export " 10 " two bits；DATA is the register data domain of frame, totally 16 bit, if read operation, then for
PHY is sent to the serial data of MDIO modules, is then sent to PHY serial data for MDIO modules if write operation；IDLE is frame knot
Idle condition after beam, now MDIO passive drives, locate high-impedance state.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010261809A (en) * | 2009-05-07 | 2010-11-18 | Hitachi Kokusai Electric Inc | Device testing system |
| CN103677671A (en) * | 2013-12-12 | 2014-03-26 | 青岛海信宽带多媒体技术有限公司 | Data reading-writing method and system of electrical port module |
| CN104407279A (en) * | 2014-10-28 | 2015-03-11 | 深圳市芯海科技有限公司 | Code type data, apparatus and test method for automatically testing chip MDIO bus protocol |
| CN105280243A (en) * | 2015-11-17 | 2016-01-27 | 西安电子科技大学 | FPGA-based NOR Flash anti-radiation performance test system |
| CN106936847A (en) * | 2017-04-11 | 2017-07-07 | 深圳市米尔声学科技发展有限公司 | The processing method and processor of voice data |
-
2017
- 2017-07-12 CN CN201710565496.0A patent/CN107478925A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010261809A (en) * | 2009-05-07 | 2010-11-18 | Hitachi Kokusai Electric Inc | Device testing system |
| CN103677671A (en) * | 2013-12-12 | 2014-03-26 | 青岛海信宽带多媒体技术有限公司 | Data reading-writing method and system of electrical port module |
| CN104407279A (en) * | 2014-10-28 | 2015-03-11 | 深圳市芯海科技有限公司 | Code type data, apparatus and test method for automatically testing chip MDIO bus protocol |
| CN105280243A (en) * | 2015-11-17 | 2016-01-27 | 西安电子科技大学 | FPGA-based NOR Flash anti-radiation performance test system |
| CN106936847A (en) * | 2017-04-11 | 2017-07-07 | 深圳市米尔声学科技发展有限公司 | The processing method and processor of voice data |
Non-Patent Citations (1)
| Title |
|---|
| 方学南: "基于FPGA的芯片自动测试平台的研究与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
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Application publication date: 20171215 |
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| RJ01 | Rejection of invention patent application after publication |