CN109144932A - A kind of device and method of the quick dynamic configuration FPGA based on DSP - Google Patents
A kind of device and method of the quick dynamic configuration FPGA based on DSP Download PDFInfo
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- CN109144932A CN109144932A CN201810876294.2A CN201810876294A CN109144932A CN 109144932 A CN109144932 A CN 109144932A CN 201810876294 A CN201810876294 A CN 201810876294A CN 109144932 A CN109144932 A CN 109144932A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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Abstract
The device and method of the present invention provides a kind of quick dynamic configuration FPGA based on DSP, belongs to field of communication technology.Described device included multiple boards of VPX bus connection, it include dsp processor, CPLD chip and fpga chip on any board, wherein, dsp processor connects host computer by Ethernet interface, one end of CPLD chip connects the dsp processor by EMIF interface, and the other end of CPLD chip connects fpga chip by SPI interface.Pass through the host computer first the method includes the configuration file to fpga chip and sends CPLD chip to through dsp processor, the FPGA configuration file of parallel transmission is converted into the SPI timing from string configuration by the CPLD chip again, and the fpga chip is sent to by SPI interface.Dynamic Configuration Online can be carried out to more board FPGA in the case where not unpacking by the invention, there is preferable flexibility.
Description
Technical field
The invention belongs to fields of communication technology, and in particular to the device of the quick dynamic configuration FPGA based on DSP a kind of and
Method.
Background technique
Field programmable gate array (FPGA) is with its high flexibility, logic abundant and I/O resource in electronics, communication
Field is using more and more extensive.The FPGA of mainstream is all based on SRAM technique substantially at present, and FPGA can lose all logics after power down
Relationship, so the general configuration data for being all equipped with an eeprom chip and being used to store FPGA, after powering on every time again to FPGA
It is loaded.This loading method not only increases system cost, and system flexibility is made to have a greatly reduced quality, and holds in configuration process
Easily because environmental factor leads to configuration failure.
Complication and functional diversities with communication system, many system needs realize different function in different moments
Energy.For example, it is desired to realize that FPGA program is quickly loaded in the case where not being switched on case, this carries out at the scene the upgrading of program with
It is particularly important in scheduling and planning.
Summary of the invention
It, can be in view of the above-mentioned problems, the present invention provides a kind of installation method based on the quick dynamic configuration FPGA of DSP/CPU
It is not switched in the case where case and dynamic configuration is carried out to muti-piece FPGA on platform, there is preferable flexibility and reliability.
The device of present invention firstly provides a kind of quick dynamic configuration FPGA based on DSP, including connected by VPX bus
The multiple boards connect, wherein include dsp processor, CPLD chip and fpga chip on any board, wherein dsp processor
Host computer is connected by Ethernet interface, one end of CPLD chip connects the dsp processor, CPLD chip by EMIF interface
The other end fpga chip is connected by SPI interface；
The host computer is passed through to the configuration file of fpga chip first and sends CPLD chip to through dsp processor, then by
The FPGA configuration file of parallel transmission is converted to the SPI timing from string configuration by the CPLD chip, and is sent by SPI interface
To the fpga chip.
Preferably, the CPLD chip further comprises:
EMIF configuration data receiving module, the FPGA configuration file sent for receiving the dsp processor, the FPGA
Configuration file is transmitted by parallel schema；
FPGA configuration module, the FPGA configuration file sent for receiving the EMIF configuration data receiving module, and turn
It is changed to the SPI timing carried out to FPGA from string configuration.
Preferably, the FPGA configuration module further include: detection and feedback unit are for detecting the FPGA configuration
No completion, and inform the EMIF configuration data receiving module, it is configured by the FPGA configuration module from the EMIF is newly received
Parallel data that data reception module is sent and processing.
Another aspect of the present invention provides the method for quick dynamic configuration FPGA based on DSP a kind of, specifically includes that
Step 1: system electrification and hardware initialization；
Step 2: host computer transmits FPGA configuration file to dsp processor；
Step 3: dsp processor sends the FPGA configuration file to CPLD chip by EMIF interface；
Step 4: the FPGA configuration file received is converted to the SPI timing configured from string by CPLD chip；
Step 5: FPGA configuration file is written in fpga chip to be configured by CPLD chip.
Preferably, before the step 2 executes, host computer transmits the FPGA configuration file to dsp processor in advance
Length and chip selection signal, and according to the length information FPGA configuration file is tested after step 2 execution
Card, and according to the chip selection signal, the selection of fpga chip to be configured after determining.
Preferably, the step 4 further comprises:
The FPGA configuration file that step 41, reception are sended in parallel mode by dsp processor；
The data that the parallel schema transmits are converted to string from the SPI timing of string configuration according to FPGA progress by step 42
The data of row mode transmission.
Preferably, the step 5 further include:
Step 51 judges whether to complete that fpga chip to be configured is written FPGA configuration file into；
If step 52 does not complete write operation, return step four.
Advantages of the present invention is mainly reflected in:
1) it is very suitable for the system to cost and volume-sensitive that system cost, reduction power consumption, reduction system bulk are saved
With；
2) it is suitable for the certain pairs of higher fields of security requirement, the program file of FPGA must carry out encrypting storing, on
It is electrolysed close rear dynamically load；
3) flexible in application due to that can realize the load of quick program in the case where system is not switched on case, at the scene into
It is particularly important in the upgrading of line program and scheduling and planning.
4) dynamic Configuration Online is carried out to more board FPGA in the case where not unpacking, there is preferable flexibility, needing
Dynamic changes the applications such as the Software Radio platform of FPGA configuration with good application prospect.
Detailed description of the invention
Fig. 1 is according to the present invention is based on the devices of a preferred embodiment of the device of the quick dynamic configuration FPGA of DSP/CPU
Connection schematic diagram.
Fig. 2 is the CPLD chip structure schematic diagram according to embodiment illustrated in fig. 1 of the present invention.
Fig. 3 is according to the present invention is based on the processes of a preferred embodiment of the method for the quick dynamic configuration FPGA of DSP/CPU
Figure.
Fig. 4 is the CPLD chip and fpga chip connection schematic diagram according to embodiment illustrated in fig. 1 of the present invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the invention implemented clearer, below in conjunction in the embodiment of the present invention
Attached drawing, technical solution in the embodiment of the present invention is further described in more detail.In the accompanying drawings, identical from beginning to end or class
As label indicate same or similar element or element with the same or similar functions.Described embodiment is the present invention
A part of the embodiment, instead of all the embodiments.The embodiments described below with reference to the accompanying drawings are exemplary, it is intended to use
It is of the invention in explaining, and be not considered as limiting the invention.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.Under
Face is described in detail the embodiment of the present invention in conjunction with attached drawing.
To solve to realize that FPGA program is quickly loaded in the case where not being switched on case, the present invention provides a kind of based on DSP/
The device and method of the quick dynamic configuration FPGA of CPU, specific embodiments of the present invention will be described in detail with reference to the accompanying drawing.
Referring initially to Fig. 1, the present invention provides a kind of device based on the quick dynamic configuration FPGA of DSP/CPU, the devices
Including the multiple boards connected by VPX bus, wherein include dsp processor, CPLD chip and FPGA core on any board
Piece, wherein dsp processor connects host computer by Ethernet interface, and one end of CPLD chip passes through described in the connection of EMIF interface
The other end of dsp processor, CPLD chip connects fpga chip by SPI interface.
Management control center of the VPX master control borad as platform is responsible for using DSP/CPU as core processor to each function
The FPGA of energy plate carries out dynamic configuration.Master control borad stores the interim configuration data of each board using Flash, and can by serial ports and
Ethernet interface is connected with the PC machine of platform exterior.If you need to upgrade configuration data, can be downloaded from outer PC by Ethernet.
Master control borad forms star-like interconnection by VPX bus with each feature board (board), and Data Transport Protocol is total using the SPI for being easier to realize
Wire protocol.Since CPLD has the characteristics that interface realizes that configuration data is not lost in easy, power-off, each feature board uses CPLD
It realizes SPI interface circuitry and carries out the control logic of dynamic configuration to FPGA.
It should be noted that under normal conditions, for any board, being provided with a dsp processor, one
CPLD chip and multiple fpga chips, but be to be written by other auxiliary devices to the configuration of the fpga chip,
There is the defects of connection is cumbersome, for this purpose, the present invention does not pass through it by resetting to above-mentioned each module connection relationship to reach
The purpose of the write-in of configuration file (such as bin file) can be completed in his auxiliary device.By above-mentioned connection, to fpga chip
Configuration file passes through the host computer first and sends CPLD chip to through dsp processor, then will be passed parallel by the CPLD chip
Defeated FPGA configuration file is converted to the SPI timing from string configuration, and is sent to the fpga chip by SPI interface.
As shown in Fig. 2, the CPLD chip further comprises EMIF configuration data receiving module and FPGA configuration module,
In, EMIF configuration data receiving module, the FPGA configuration file sent for receiving the dsp processor, FPGA configuration
File is transmitted by parallel schema；FPGA configuration module, the FPGA sent for receiving the EMIF configuration data receiving module
Configuration file, and be converted to and the SPI timing configured from string is carried out to FPGA, FPGA configuration module carries out from string FPGA in realization
After the SPI timing of configuration, configuration file is written in FPGA to be configured.
On the other hand, above-mentioned FPGA configuration module further include: detection and feedback unit are for detecting the FPGA configuration
No completion, and inform the EMIF configuration data receiving module, it is configured by the FPGA configuration module from the EMIF is newly received
The parallel data and processing, the detection and feedback unit that data reception module is sent are realized by low and high level, are detected first
Journey is reflected according to the height of two level DONE and Init_B of fpga chip, secondly, feedback procedure is FPGA configuration
Module indicates the level DONE's and Init_B of fpga chip using the level height of two stitch of CFG_FINISH and ERROR
Just, whether FPGA configuration process is completed to be sent to EMIF configuration data receiving module as a result, due to EMIF configuration data
Receiving module has the characteristics that storing data is stablized, and can send data to fpga chip again.
With reference to Fig. 3, the method for the present invention also provides a kind of quick dynamic configuration FPGA based on DSP is specifically included that
Step 1: system electrification and hardware initialization；
Step 2: host computer transmits FPGA configuration file to dsp processor；
Step 3: dsp processor sends the FPGA configuration file to CPLD chip by EMIF interface；
Step 4: the FPGA configuration file received is converted to the SPI timing configured from string by CPLD chip；
Step 5: FPGA configuration file is written in fpga chip to be configured by CPLD chip.
In the present embodiment, with reference to Fig. 3, before the step 2 executes, host computer is in advance to described in dsp processor transmission
The length and chip selection signal of FPGA configuration file, and the FPGA is configured according to the length information after step 2 execution
File is verified, and according to the chip selection signal, the selection of fpga chip to be configured after determining.After being verified, DSP
Processor begins through EMIF interface to CPLD transmitting configuration file and enable signal, while CPLD receives configuration data and right
FPGA is configured.
In the present embodiment, the step 4 further comprises:
The FPGA configuration file that step 41, reception are sended in parallel mode by dsp processor；
The data that the parallel schema transmits are converted to string from the SPI timing of string configuration according to FPGA progress by step 42
The data of row mode transmission.
In the present embodiment, the step 5 further include:
Step 51 judges whether to complete that fpga chip to be configured is written FPGA configuration file into；
If step 52 does not complete write operation, return step four.
Specifically, CPLD first passes through the frame configuration data that EMIF interface is sent to DSP/CPU, configuration module is again
Parallel configuration data is converted to serial configuration data, and is sent to by SPI interface according to the modularization design of FPGA
FPGA.After being sent, FPGA configuration module starts to receive next frame data, until configuration data all finishes receiving.Configuration
After data receiver is complete, in conjunction with Fig. 2 and Fig. 4, FPGA configuration module will test DONE and Init_B.If detecting, DONE is height,
CCLK keeps configuration process after 8 periods to terminate.Meanwhile CFG_FINISH will be raised, and notify DSP/CPU configuration successful.If
Detect INIT_B be it is low, then ERROR will be raised, notify DSP/CPU configuration failure.With reference to Fig. 4, the CPLD chip of upper left side
And right side fpga chip and its between connection relationship cover in the inventive solutions, and the jtag interface of lower left side
Connection with fpga chip is the prior art, when due to by jtag interface to fpga chip burning configuration file, needs to open
The fpga chip is connected replicating machine by jtag interface by cabinet, and in the different configuration file of burning, is needed in repetition
Electricity, power-off etc., process is cumbersome, and the present invention is based on the components integrated on existing board, are written and are configured to FPGA by CPLD
File can not be limited by quantity of documents, in the debugging of outfield, it is not necessary to repeat to power off because of multiple burning configuration file.
Figure 4, it is seen that CPLD chip mainly passes through five stitch connection FPGA, clock signal is respectively included
CLOCK, the SERIAL_OUT signal that data are written, the PROGRAM_B signal of control switch, completion signal DONE and burning are lost
Lose signal INIT_B.The signals such as remaining reset input conventional design, and the stitch that FPGA is connect with jtag interface belongs to the prior art,
And it is not belonging to the content of present invention, it repeats no more.
It is understood that completing signal DONE and burning failure signal INIT_B is by FPGA reverse transfer to CPLD
, in conjunction with Fig. 2, it is respectively used to by ERROR and CFG_FINISH that FPGA configuration module is directed toward EMIF configuration data receiving module
Respond above-mentioned INIT_B and DONE signal.
Advantages of the present invention is mainly reflected in:
1) it is very suitable for the system to cost and volume-sensitive that system cost, reduction power consumption, reduction system bulk are saved
With；
2) it is suitable for the certain pairs of higher fields of security requirement, the program file of FPGA must carry out encrypting storing, on
It is electrolysed close rear dynamically load；
3) flexible in application due to that can realize the load of quick program in the case where system is not switched on case, at the scene into
It is particularly important in the upgrading of line program and scheduling and planning.
4) dynamic Configuration Online is carried out to more board FPGA in the case where not unpacking, there is preferable flexibility, needing
Dynamic changes the applications such as the Software Radio platform of FPGA configuration with good application prospect.
Finally it is noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations.To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, those skilled in the art should understand that: it is still
It is possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is equally replaced
It changes；And these are modified or replaceed, the essence for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution
Mind and range.
Claims (7)
1. a kind of device of the quick dynamic configuration FPGA based on DSP, which is characterized in that more including being connected by VPX bus
A board, wherein on any board include dsp processor, CPLD chip and fpga chip, wherein dsp processor by with
Too network interface connects host computer, and one end of CPLD chip connects the dsp processor by EMIF interface, CPLD chip it is another
End connects fpga chip by SPI interface；
The host computer is passed through to the configuration file of fpga chip first and sends CPLD chip to through dsp processor, then by described
The FPGA configuration file of parallel transmission is converted to the SPI timing from string configuration by CPLD chip, and is sent to institute by SPI interface
State fpga chip.
2. the device of the quick dynamic configuration FPGA based on DSP as described in claim 1, which is characterized in that the CPLD core
Piece further comprises:
EMIF configuration data receiving module, the FPGA configuration file sent for receiving the dsp processor, FPGA configuration
File is transmitted by parallel schema；
FPGA configuration module, the FPGA configuration file sent for receiving the EMIF configuration data receiving module, and be converted to
SPI timing from string configuration is carried out to FPGA.
3. the device of the quick dynamic configuration FPGA based on DSP as claimed in claim 2, which is characterized in that the FPGA matches
Set module further include: detection and feedback unit for detecting whether the FPGA configuration is completed, and inform the EMIF configuration number
According to receiving module, by the FPGA configuration module from newly receiving parallel data that the EMIF configuration data receiving module is sent simultaneously
Processing.
4. a kind of method of the quick dynamic configuration FPGA based on DSP characterized by comprising
Step 1: system electrification and hardware initialization；
Step 2: host computer transmits FPGA configuration file to dsp processor；
Step 3: dsp processor sends the FPGA configuration file to CPLD chip by EMIF interface；
Step 4: the FPGA configuration file received is converted to the SPI timing configured from string by CPLD chip；
Step 5: FPGA configuration file is written in fpga chip to be configured by CPLD chip.
5. the device of the quick dynamic configuration FPGA based on DSP as described in benefit requires 4, which is characterized in that the step 2 is held
Before row, host computer transmits the length and chip selection signal of the FPGA configuration file to dsp processor in advance, and holds in step 2
The FPGA configuration file is verified according to the length information after row, and according to the chip selection signal, after determining
The selection of fpga chip to be configured.
6. benefit require 4 as described in the quick dynamic configuration FPGA based on DSP device, which is characterized in that the step 4 into
One step includes:
The FPGA configuration file that step 41, reception are sended in parallel mode by dsp processor；
The data that the parallel schema transmits are converted to serial mould from the SPI timing of string configuration according to FPGA progress by step 42
The data of formula transmission.
7. the device of the quick dynamic configuration FPGA based on DSP as described in benefit requires 4, which is characterized in that the step 5 is also
Include:
Step 51 judges whether to complete that fpga chip to be configured is written FPGA configuration file into；
If step 52 does not complete write operation, return step four.
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| CN110311752A (en) * | 2019-06-14 | 2019-10-08 | 杭州爱科科技股份有限公司 | For the quick stable communication means and its communication device fastly of chip chamber |
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Application publication date: 20190104 |