CN110311752B

CN110311752B - Communication method and communication device for rapid, fast and stable communication between chips

Info

Publication number: CN110311752B
Application number: CN201910513629.9A
Authority: CN
Inventors: 方云科; 伍郁杰
Original assignee: Hangzhou Iecho Technology Co ltd
Current assignee: Hangzhou Iecho Technology Co ltd
Priority date: 2019-06-14
Filing date: 2019-06-14
Publication date: 2022-04-08
Anticipated expiration: 2039-06-14
Also published as: CN110311752A

Abstract

The invention relates to a communication method and a communication device for rapid, fast and stable communication between chips, and belongs to the field of chip communication. The invention adds a SUCCED pin and an INTERRUPT _ REQ pin on the basis of standard SPI communication, realizes CRC16 verification in a hardware mode during SPI communication, and quickly returns back to a sending end synchronously through a SUCCEED pin line, wherein the INTERRUPT _ REQ pin is used for a receiving end to request data of the sending end. The invention has convenient communication, safety and reliability, can ensure the fast and stable communication between chips, simultaneously detects errors and ensures the real-time requirement.

Description

Communication method and communication device for rapid, fast and stable communication between chips

Technical Field

The invention relates to a communication method and a communication device thereof, in particular to a quick, quick and stable communication method and a communication device thereof used between chips, which can improve the real-time response capability between the chips and belong to the field of chip communication.

Background

The motion control system is a system with high real-time requirement, a good motion control system can control the motion command to be subdivided in microsecond level, and the minimum scanning period can reach 0.1 ms. Because the continuity of motion requires a high real-time response speed of the motion control system. This requires that the motion control commands be quickly prepared for error-free issuance in real time and receive feedback positions of the respective motion units in real time.

The multi-axis interpolation motion controller generally concentrates multi-path position feedback signals to the FPGA for unified reception and then transmits the signals to the main chip through inter-chip communication, thereby requiring the inter-chip communication to be fast and real-time and capable of detecting errors. The method solves the problems of real-time communication and error detection of the peripheral chip and the main chip.

In chinese patent with publication number CN 108073102 a, publication number is 25/05/2018, a communication method and a communication control system of a communication system are disclosed, in which a main controller of the patent sends a PWM waveform control signal with a certain duty ratio, a microprocessor receives the control signal and analyzes the control signal to generate a driving signal, and the driving signal drives an execution element to move; the communication method also comprises an event processing step, wherein an event list is prestored in the event processing step and comprises a plurality of groups of event information representing event states, the microprocessor acquires the current operating state of the execution element at intervals of a certain time, when the current operating state is the same as the event state corresponding to the event information of the event list, the microprocessor activates or closes the event information in the event list according to the event processing step and feeds back the event information to the main controller, the event information is irrelevant to the specific execution element, although the universality of the communication method is improved, the main controller acquires feedback information and controls more timely and accurately, the problems of real-time communication and error detection of peripheral chips and a main chip cannot be solved, the real-time quick preparation cannot be sent out, the requirements achieved by the motion control system cannot be met, and the defects are also existed.

Therefore, it is necessary to provide a communication method and a communication apparatus thereof, which are convenient for communication, can ensure fast and stable communication between chips, and simultaneously detect errors, and ensure real-time requirements.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned deficiencies in the prior art, and provides a communication method and a communication apparatus for fast and stable communication between chips, which are convenient, safe and reliable, and can ensure fast and stable communication between chips and error detection, and ensure real-time requirements.

The technical scheme adopted by the invention for solving the problems is as follows: the communication method for the rapid and stable communication between the chips is characterized in that: on the basis of standard SPI communication, a SUCCED pin and an INTERRUPT _ REQ pin are added, a sending end is a DSP, a receiving end is an FPGA, and the method specifically comprises the following steps:

the method comprises the following steps: the DSP sends a motion command and waits for a SUCCEED signal to confirm success;

step two: the FPGA distributes a motion command to a motion unit, collects position information and uploads the position information to the DSP;

step three: if no command is executable, the FPGA actively requests the command by setting the INTERRUPT _ REQ signal high, and how to respond is determined by the DSP.

Preferably, in the second step of the present invention, the uploading action is actively queried by the DSP.

Preferably, in the second step of the present invention, the FPGA generates an INTERRUPT signal through the INTERRUPT _ REQ signal pin to force the DSP to receive a signal that needs to be processed.

The invention also provides a device used in the communication method for fast and stable communication between chips, which is characterized in that: including SPI communication, SPI communication includes Master SPI and Slave SPI, its characterized in that: the device also comprises a SUCCED pin and an INTERRUPT _ REQ pin, communication verification is realized in real time, the SUCCED pin returns back to the sending end, the receiving end actively initiates application data through the INTERRUPT _ REQ signal pin, and synchronization after data errors is realized.

Preferably, the Master SPI is a six-axis motion control system motion command transmission center, and is responsible for generating six-axis motion control commands and processing return information.

Preferably, the Slave SPI according to the present invention is a sport command distribution center, and is responsible for distributing a sport command to each of the sport units and collecting location information of each of the sport units.

Preferably, the SPI communication of the present invention is a standard SPI communication.

Preferably, the SPI communication of the present invention is checked by its own CRC 16.

Preferably, the transmitting end of the invention is a DSP.

Preferably, the receiving end of the invention is an FPGA.

Compared with the prior art, the invention has the following advantages and effects: the communication is convenient, safe and reliable, and the SPI communication method with CRC16 check is adopted; the communication between the chips can be ensured to be rapid and stable, and the error detection is carried out at the same time, thereby ensuring the real-time requirement.

Drawings

Fig. 1 is a schematic diagram of an SPI communication device according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of an SPI communication flow according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail below by way of examples with reference to the accompanying drawings, which are illustrative of the present invention and are not to be construed as limiting the present invention.

Examples are given.

Referring to fig. 1 to fig. 2, the method for fast, fast and stable communication between chips in the present embodiment specifically includes the following steps: the method comprises the following steps: the DSP sends a motion command and waits for the success signal to confirm success.

Step two: the FPGA distributes a motion command to the motion unit, collects position information and uploads the position information to the DSP.

The uploading action in the second step of this embodiment may be actively queried by the DSP, or the FPGA may generate an INTERRUPT signal through the INTERRUPT _ REQ signal pin to force the DSP to receive a signal that needs to be processed.

This embodiment is used for quick stable communication device between chip to include SPI communication, SUCCED pin and INTERRUPT _ REQ pin, and SPI communication includes Master SPI and Slave SPI, realizes communication check in real time and returns the transmitting terminal with the SUCCED pin, and the receiving terminal initiatively launches the application data through INTERRUPT _ REQ signal pin to realize the synchronization after the data mistake.

The Master SPI in this embodiment is a DSP, which is a six-axis motion control system motion command transmission center and is responsible for generating a six-axis motion control command and processing return information.

The Slave SPI in this embodiment is an FPGA chip, and the FPGA movement command distribution center is responsible for distributing movement commands to the movement units and collecting position information of the movement units.

The SPI communication in the embodiment is standard SPI communication; the SPI communication is checked with CRC 16; the sending end is a DSP; the receiving end is an FPGA.

In the method, two pin lines such as SUCCED and INTERRUPT _ REQ are added on the basis of standard SPI communication, CRC16 verification is realized in a hardware mode while the SPI communication is carried out, and the CRC16 verification is synchronously and quickly returned to a transmitting end (a host end) through the SUCCEED pin lines; the other newly added pin line is INTERRUPT _ REQ for the receiving end (slave) to request the data of the sending end (master).

And will be apparent to those skilled in the art from the foregoing description.

In addition, it should be noted that the specific embodiments described in the present specification may be different in the components, the shapes of the components, the names of the components, and the like, and the above description is only an illustration of the structure of the present invention. Equivalent or simple changes in the structure, characteristics and principles of the invention are included in the protection scope of the patent. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.

Claims

1. A communication method for fast and stable chip is characterized in that: on the basis of standard SPI communication, a SUCCED pin and an INTERRUPT _ REQ pin are added, a sending end is a DSP, a receiving end is an FPGA, and the method specifically comprises the following steps:

step two: the FPGA distributes a motion command to a motion unit, collects position information and uploads the position information to the DSP; uploading action is actively inquired by the DSP; in the uploading action, the FPGA generates an INTERRUPT signal through an INTERRUPT _ REQ signal pin to force the DSP to receive a signal which needs to be processed;

2. An apparatus as claimed in claim 1, for use in a communication method for fast and stable communication between chips, wherein: including SPI communication, SPI communication includes Master SPI and Slave SPI, its characterized in that: the device also comprises a SUCCED pin and an INTERRUPT _ REQ pin, communication verification is realized in real time, the SUCCED pin returns back to the sending end, the receiving end actively initiates application data through the INTERRUPT _ REQ signal pin, and synchronization after data errors is realized; the Master SPI is a six-axis motion control system motion command sending center and is responsible for generating six-axis motion control commands and processing return information.

3. The communication device for fast and stable communication between chips according to claim 2, wherein: the Slave SPI is a sport command distribution center, and is responsible for distributing a sport command to each sport unit and collecting position information of each sport unit.

4. The communication device for fast and stable communication between chips according to claim 2, wherein: the SPI communication is a standard SPI communication.

5. The communication device for fast and stable communication between chips according to claim 2, wherein: the SPI communication is checked with CRC 16.

6. The communication device for fast and stable communication between chips according to claim 2, wherein: the sending end is a DSP.

7. The communication device for fast and stable communication between chips according to claim 2, wherein: the receiving end is an FPGA.