CN114924808A - SRAM type FPGA on-orbit reliable loading method based on duplicate storage program - Google Patents

SRAM type FPGA on-orbit reliable loading method based on duplicate storage program Download PDF

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CN114924808A
CN114924808A CN202210512827.5A CN202210512827A CN114924808A CN 114924808 A CN114924808 A CN 114924808A CN 202210512827 A CN202210512827 A CN 202210512827A CN 114924808 A CN114924808 A CN 114924808A
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fpga
configuration program
sram type
bin file
norflash
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CN114924808B (en
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潘虹臣
陈林
刘禹圻
余辉
姜博文
王遂生
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CETC 29 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G06F9/4451—User profiles; Roaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Stored Programmes (AREA)

Abstract

The invention discloses an on-orbit reliable loading method of an SRAM (static random Access memory) type FPGA (field programmable Gate array) based on a duplicate storage program, which comprises the following steps of: dividing a check unit in an FPGA configuration program bin file and inserting CRC (cyclic redundancy check) into the FPGA configuration program bin file; injecting the bin file of the FPGA configuration program added with the verification into different positions in NORFlash in two times; when the rail is powered on, the antifuse FPGA selects correct FPGA configuration program bin file data to load the SRAM type FPGA; after the SRAM type FPGA is successfully started, rewriting the Block with bit upset according to the checking condition in NORFlast. The invention realizes the loading of SRAM type FPGA through the double-copy program in NORFlash, and reduces the requirement on NORFlash capacity on the basis of ensuring the reliability; the method has an on-orbit error detection and update mechanism of the SRAM type FPGA configuration file, greatly reduces the probability that the same position of a duplicate program is knocked over by a single particle under the condition of long-time on-orbit working, and greatly improves the reliability of the SRAM type FPGA configuration program.

Description

SRAM type FPGA on-orbit reliable loading method based on duplicate storage program
Technical Field
The invention relates to the technical field of spacecrafts, in particular to an on-orbit reliable loading method of an SRAM (static random Access memory) type FPGA (field programmable Gate array) based on a duplicate storage program.
Background
SRAM type FPGAs have the advantage of repeated programming, requiring power up for loading configuration. In the on-orbit operation of the SRAM type FPGA, a chip and a configuration memory of the chip face the threat of a single event effect, particularly once a configuration program in the memory is subjected to single event upset, the FPGA cannot be loaded successfully, and if the upset configuration program cannot be recovered, catastrophic failure of extension set or system failure can be caused. The PROM with a high single event upset threshold value can effectively protect the configuration program, but the PROM has small capacity, and the memory capacity requirement can be met by multiple PROMs; and PROM can not be repeatedly erased and written, so FPGA loses on-track updating capability. The use of NORFlash as a configuration memory chip has the advantage of being rewritable, the configuration process can be reconfigured on-track, but the rollover threshold of NORFlash is relatively low. Usually, three NORFlash pieces are used for chip level three-mode design, or 3 programs are stored in a single chip to realize three-mode redundancy design. The former requires a large number of chips; the latter has a great demand for the NORFlash chip capacity when storing large-capacity configuration files, and the NORFlash with large capacity has a larger size and higher price, which results in the increase of the PCB layout difficulty and development cost.
Disclosure of Invention
In view of the above, the invention provides an on-orbit reliable loading method for an SRAM type FPGA based on a duplicate storage program, which realizes correct selection of an SRAM type FPGA loading file through two bin files with check information; after successful loading, the bin file in NORFlast is periodically checked, the data with bit upset is updated, and error data accumulation is avoided.
The invention discloses an on-orbit reliable loading method of an SRAM (static random Access memory) type FPGA (field programmable Gate array) based on a duplicate storage program, which comprises the following steps of:
step 1: dividing a check unit in an FPGA configuration program bin file and inserting CRC (cyclic redundancy check) into the FPGA configuration program bin file;
and 2, step: injecting the FPGA configuration program bin file added with the verification into different positions in NORFlash in two times;
and 3, step 3: when the rail is powered on, the antifuse FPGA selects correct FPGA configuration program bin file data to load the SRAM type FPGA;
and 4, step 4: after the SRAM type FPGA is successfully started, rewriting the Block with bit reversal according to the check condition in NORFlast.
Further, the step 1 specifically includes:
step 1-1: generating an FPGA configuration program bin file by using an FPGA development tool;
step 1-2: defining the size of a check unit to be N bytes according to the size of the NORFlast block; each NORFlast block comprises at least one check unit; each check unit consists of bin file data and CRC check bits;
step 1-3: each check unit sequentially takes out N-2 bytes of data from the first byte in the FPGA configuration program bin file, and if the tail is less than N-2 bytes, 0 to N-2 bytes are supplemented; and generates a CRC check value in each check unit according to the CRC16 check method, respectively.
Further, the step 2 specifically includes:
step 2-1: when an FPGA configuration program bin file added with verification is injected for the first time, a NORFlash has no configuration program and cannot be started, and a JTAG interface is used for downloading an FPGA program on line to enable the FPGA to work;
step 2-2: the external communication interface sends the same checked FPGA configuration program bin file into an SRAM type FPGA twice, and the SRAM type FPGA transmits the checked FPGA configuration program bin file after analyzing the communication protocol to the antifuse FPGA; and the anti-fuse FPGA writes the two FPGA configuration program bin files added with the verification into different positions in NORFlash respectively.
Further, the step 3 specifically includes:
step 3-1: when the rail is electrified, the antifuse FPGA first loads an SRAM type FPGA from a first FPGA configuration program bin file stored in NORFlash;
step 3-2: if the first bin file stored in NORFlash can not be loaded, the antifuse FPGA takes the second FPGA configuration program bin file stored in NORFlash to load the SRAM type FPGA;
step 3-3: and if the second FPGA configuration program bin file stored in the NORFlash can not be loaded, the antifuse FPGA selects correct FPGA configuration program bin file data from the two programs according to the sequence of the check units to load the SRAM type FPGA.
Further, the step 3-1 specifically includes:
step 3-1-1: when the power is on, the antifuse FPGA takes a first FPGA configuration program bin file stored in NORFlash, skips over check bits in each check unit, and directly transmits data to the SRAM type FPGA for loading;
step 3-1-2: and after the first FPGA configuration program bin file stored in the NORFlast is transmitted to the SRAM type FPGA, the anti-fuse FPGA judges whether the FPGA is loaded successfully or not through a done signal of the SRAM type FPGA.
Further, the step 3-2 specifically includes:
step 3-2-1: the antifuse FPGA takes a second FPGA configuration program bin file stored in NORFlash, skips over check bits in each check unit, and directly transmits data to the SRAM type FPGA for loading;
step 3-2-2: and after the second FPGA configuration program bin file stored in the NORFlast is transmitted to the SRAM type FPGA, the anti-fuse FPGA judges whether the FPGA is loaded successfully or not through a done signal of the SRAM type FPGA.
Further, the step 3-3 specifically includes:
step 3-3-1: the anti-fuse FPGA firstly takes a first check unit of a first FPGA configuration program bin file stored in NORFlast to carry out CRC check, and if the check is correct, data are transmitted to the SRAM type FPGA; if the verification is wrong, a first verification unit of a second FPGA configuration program bin file stored in NORFlast is taken for verification, and if the verification is correct, the data is transmitted to the SRAM type FPGA;
step 3-3-2: and (3) selecting correct data from each check unit in the two FPGA configuration program bin files by the antifuse FPGA according to the mode of the step 3-3-1 to load the SRAM type FPGA.
Further, the step 4 specifically includes:
step 4-1: after the digital circuit works normally, the antifuse FPGA periodically checks an FPGA configuration program bin file in NORFlash, and reports a Block number which is checked to be wrong to the SRAM type FPGA, and the SRAM type FPGA sends the serial number of the wrong NORFlash to a house keeping computer through an external communication interface and finally transmits the serial number to the ground through digital telemetering;
step 4-2: the ground can upload all correct checking units in the NORFlash block with the wrong checking to the satellite through the satellite-ground communication link, the SRAM type FPGA acquires the reinjected checking units through the external communication interface and sends the reinjected checking units to the antifuse FPGA, and the antifuse FPGA writes the checking units into the original position of the NORFlash and finally realizes the updating of error data.
Due to the adoption of the technical scheme, the invention has the following advantages: (1) the loading of the SRAM type FPGA is realized through the duplicate program in the NORFlash, and the requirement on the NORFlash capacity is reduced on the basis of ensuring the reliability; (2) the invention has the on-orbit error detection and update mechanism of the SRAM type FPGA configuration file, greatly reduces the probability of single-particle overturn of the same position of a duplicate program under the condition of long-time working on the orbit, and greatly improves the reliability of the SRAM type FPGA configuration program.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments described in the embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings.
FIG. 1 is a schematic diagram of a flow chart of an on-track reliable loading method for an SRAM type FPGA based on a duplicate storage program according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a partitioning manner of a verification unit according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating an SRAM-type FPGA configuration program according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a method for selectively loading a file by an antifuse FPGA according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples, it being understood that the examples described are only some of the examples and are not intended to limit the invention to the embodiments described herein. All other embodiments available to those of ordinary skill in the art are intended to be within the scope of the embodiments of the present invention.
The first embodiment is as follows:
referring to fig. 1, the present invention provides an embodiment of an SRAM type FPGA on-track reliable loading method based on duplicate storage programs, which includes the following steps:
step 1: and dividing a check unit in the FPGA configuration program bin file and inserting CRC check.
Step 1-1: and generating an FPGA configuration program bin file by using an FPGA development tool.
Step 1-2: according to the NORFlash Block (Block) size, a check unit size is defined as N bytes. One Block may contain one or more check units. NORFlash is usually operated by word, CRC16 check algorithm can be used, check bit is 2 bytes, and FPGA configurator bin file data which can be stored in a file in a check unit is N-2 bytes. And the data of the bin file of the FPGA configuration program and the CRC check bit jointly form a check unit.
Step 1-3: and each checking unit sequentially takes out N-2 bytes of data from the bin file from front to back, and if the tail is less than N-2 bytes, the data is supplemented by 0 to N-2 bytes. And generates a CRC check value in each check unit according to the CRC16 check method, respectively. The FPGA configurator bin file inserted with the check is shown in fig. 2.
Step 2: the bin file added to the check was injected in two different places in NORFlash.
Step 2-1: when the FPGA configuration program bin file added with the verification is injected for the first time, the NORFlash has no configuration program and cannot be started, and a JTAG interface is required to be used for downloading the FPGA program on line so that the FPGA works.
Step 2-2: and the external communication interface sends the same verified FPGA configuration program bin file to the SRAM type FPGA twice, and the SRAM type FPGA sends the verified FPGA configuration program bin file subjected to communication protocol analysis to the antifuse FPGA. And the antifuse FPGA writes two parts of the verified FPGA configuration program bin files into different positions in the NORFlash respectively.
And 3, step 3: when the on-rail power is on, the antifuse FPGA preferentially takes a first FPGA configuration program bin file to load the SRAM type FPGA.
Step 3-1: when the power is on, the antifuse FPGA takes the first bin file stored in NORFlast, skips over the check bit in each check unit, and directly sends data to the SRAM type FPGA for loading, as shown in a path a of FIG. 3. The basis of this step is: the occurrence of the single event is a small probability event, the turnover threshold of the Flash is high in the power-off state, and the configuration program in the NORFlash is not turned over in a large probability when the power is on the rail. The purpose of this step is: and (3) shortening the loading time of the SRAM type FPGA under normal conditions, wherein if the NORFlash needs to be read twice by adopting a mode of firstly verifying the first program and then loading, the time is 1 time longer than that of direct loading.
Step 3-2: after a first FPGA configuration program bin file stored in NORFlash is completely sent to the SRAM type FPGA, the antifuse FPGA judges whether the FPGA is loaded successfully or not through done signals of the SRAM type FPGA.
And 4, step 4: and if the first FPGA configuration program bin file stored in the NORFlash can not be loaded, the antifuse FPGA takes the second FPGA configuration program bin file to load the SRAM type FPGA.
Step 4-1: the antifuse FPGA takes the second FPGA configuration program bin file stored in NORFlash, skips over the check bit in each check unit, and directly sends the data to the SRAM type FPGA for loading, as shown in path b of fig. 3.
Step 4-2: and after the second FPGA configuration program bin file stored in the NORFlast is completely sent to the SRAM type FPGA, the antifuse FPGA judges whether the FPGA is loaded successfully or not according to done signals of the SRAM type FPGA.
And 5: and if the bin file of the second FPGA configuration program stored in the NORFlash can not be loaded, the anti-fuse FPGA selects correct bin file data from the two programs according to the sequence of the check units to load the SRAM type FPGA.
Step 5-1: the anti-fuse FPGA preferentially takes a first check unit of a first FPGA configuration program bin file for CRC check, and if the check is correct, the data are sent to the SRAM type FPGA; and if the verification is wrong, the first verification unit of the second bin file is taken for verification, and if the verification is correct, the data is sent to the SRAM type FPGA, which is shown in a path c of FIG. 3. The basis of this step is: the probability of single event occurrence is small, and the probability that the same check unit of different bin files in NORFlash is simultaneously knocked over by single particles is very small, so that the data of at least one check unit can be used for program loading, and the reliability is ensured.
Step 5-2: and (4) selecting correct data from each check unit in the two FPGA configuration program bin files by the antifuse FPGA according to the mode of the step 5-1 to load the SRAM type FPGA.
Step 6: after the SRAM type FPGA is successfully started, rewriting the Block with bit reversal according to the check condition in NORFlast.
Step 6-1: after the digital circuit works normally, the antifuse FPGA periodically checks an FPGA configuration program bin file in NORFlash, and reports the serial number of a Block with an error check to the SRAM type FPGA, and the SRAM type FPGA sends the number of the error Block to a house keeping computer through an external communication interface and finally transmits the number to the ground through digital telemetering.
Step 6-2: the ground can upload all correct check units in the Block numbers with the check errors to the satellite through the satellite-ground communication link, the SRAM type FPGA acquires the check units which are injected again through the external communication interface and sends the check units to the antifuse FPGA, and the antifuse FPGA writes the check units into the original position of NORFlash, so that the update of error data is realized newly.
Example two:
to facilitate understanding, a more specific embodiment of the invention is given:
the SRAM type FPGA of a certain circuit selects XC7K325T-2FFG900I, the antifuse FPGA selects A54SX72ACQ208B, and the NORFlash selects VDRF256M16RS54MS4V90 of 256 Mb. NORFlash with a K7 fpbin file of 11443612Byte, 256Mb can only store two programs at the most. The steps for loading the SRAM model by using the method are as follows:
firstly, dividing check units in bin files of K7FPGA, and inserting check polynomial G (x) x into every 65534Byte 16 +x 10 +x 2 +1 CRC16 checks, with 65536Byte (1 NORFlashBlock size) per check unit. The bin file after insertion checking has 175 checking units in total and the file size is 11468800 Byte.
And secondly, downloading the FPGA program on line by using a JTAG debugging interface, and respectively injecting the bin file inserted into the verification into different positions of NORFlash.
And thirdly, after the power is re-electrified, the antifuse FPGA preferentially takes a first FPGA configuration program bin file stored in NORFlast to load the SRAM type FPGA, and the first program is successfully started in about 4 seconds.
Fourthly, referring to fig. 4, if the first part of the FPGA configuration program bin file stored in the NORFlash cannot be loaded, the antifuse FPGA loads the SRAM type FPGA by using the second part of the FPGA configuration program bin file stored in the NORFlash. To simulate the process, the first Block of the first program was injected into the program to check for errors, and after re-powering up, the second program was successfully started in about 8 seconds.
And fifthly, if the second FPGA configuration program bin file stored in the NORFlash can not be loaded, the antifuse FPGA selects correct FPGA configuration program bin file data from the two programs stored in the NORFlash according to the sequence of the check units to load the SRAM type FPGA. In order to simulate the process, on the basis that the first Block data of the first FPGA configuration program bin file is wrong, the second Block of the second FPGA configuration program bin is injected with data for checking the error, and after the second FPGA configuration program bin is electrified again, the FPGA is started successfully after about 16 seconds.
And sixthly, after the SRAM type FPGA is successfully started, rewriting the Block with the bit upset according to the checking condition in NORFlast. And the SRAM type FPGA reports the positions of a first Block of a first bin file and a second Block of a second program which are checked to be wrong, and correct data are respectively written into the two blocks by utilizing an external communication interface of the SRAM type FPGA.
The measures can reduce the probability of incapability of loading caused by single event upset of the configuration program to 1/174 of the conventional single configuration file means, and greatly improve the reliability of program loading.
The implementation of the invention is described above by taking three devices of XC7K325T-2FFG900I, A54SX72ACQ208B and VDRF256M16RS54MS4V90 as examples, but the invention is also applicable to other devices of different types.
Finally, it should be noted that: although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.

Claims (8)

1. An on-orbit reliable loading method of an SRAM type FPGA based on a duplicate storage program is characterized by comprising the following steps:
step 1: dividing a check unit in an FPGA configuration program bin file and inserting CRC (cyclic redundancy check) check;
and 2, step: injecting the FPGA configuration program bin file added with the verification into different positions in NORFlash in two times;
and 3, step 3: when the rail is electrified, the antifuse FPGA selects correct FPGA configuration program bin file data to load the SRAM type FPGA;
and 4, step 4: after the SRAM type FPGA is successfully started, rewriting the Block with bit upset according to the checking condition in NORFlast.
2. The method according to claim 1, wherein step 1 specifically comprises:
step 1-1: generating bin files by using an FPGA development tool;
step 1-2: defining the size of a check unit as N bytes according to the size of the NORFlast block; each NORFlast block comprises at least one check unit; each check unit consists of bin file data and CRC check bits;
step 1-3: each check unit sequentially takes out N-2 bytes of data from the first byte in the bin file, and if the tail of the data is less than N-2 bytes, the data is supplemented by 0 to N-2 bytes; and generates a CRC check value in each check unit according to the CRC16 check method, respectively.
3. The method according to claim 1, wherein the step 2 specifically comprises:
step 2-1: when an FPGA configuration program bin file added with verification is injected for the first time, a NORFlash has no configuration program and cannot be started, and a JTAG interface is used for downloading an FPGA program on line to enable the FPGA to work;
step 2-2: the external communication interface sends the same checked FPGA configuration program bin file into an SRAM type FPGA twice, and the SRAM type FPGA transmits the checked FPGA configuration program bin file after analyzing the communication protocol to the antifuse FPGA; and the antifuse FPGA writes two parts of the verified FPGA configuration program bin files into different positions in the NORFlash respectively.
4. The method according to claim 1, wherein step 3 specifically comprises:
step 3-1: when the rail is electrified, the antifuse FPGA firstly takes a first FPGA configuration program bin file stored in NORFlash to load an SRAM type FPGA;
step 3-2: if the first part of FPGA configuration program bin file stored in NORFlash can not be loaded, the antifuse FPGA takes the second part of FPGA configuration program bin file stored in NORFlash to load the SRAM type FPGA;
step 3-3: and if the second part of FPGA configuration program bin file stored in the NORFlast can not be loaded, the antifuse FPGA selects correct FPGA configuration program bin file data from the two parts of programs according to the sequence of the check units to load the SRAM type FPGA.
5. The method according to claim 4, wherein the step 3-1 specifically comprises:
step 3-1-1: when the power is on, the antifuse FPGA takes a first FPGA configuration program bin file stored in NORFlash, skips over check bits in each check unit, and directly transmits data to the SRAM type FPGA for loading;
step 3-1-2: and after the first FPGA configuration program bin file stored in the NORFlash is transmitted to the SRAM type FPGA, the antifuse FPGA judges whether the FPGA is loaded successfully or not according to a done signal of the SRAM type FPGA.
6. The method according to claim 5, wherein the step 3-2 specifically comprises:
step 3-2-1: the anti-fuse FPGA takes a second FPGA configuration program bin file stored in NORFlast, skips over check bits in each check unit, and directly transmits data to the SRAM type FPGA for loading;
step 3-2-2: and after the second FPGA configuration program bin file stored in the NORFlast is transmitted to the SRAM type FPGA, the anti-fuse FPGA judges whether the FPGA is loaded successfully or not through a done signal of the SRAM type FPGA.
7. The method according to claim 6, wherein said step 3-3 comprises in particular:
step 3-3-1: the anti-fuse FPGA firstly takes a first check unit of a first FPGA configuration program bin file stored in NORFlash to carry out CRC check, and if the check is correct, data are transmitted to the SRAM type FPGA; if the verification is wrong, a first verification unit of a second FPGA configuration program bin file stored in NORFlast is taken for verification, and if the verification is correct, the data is transmitted to the SRAM type FPGA;
step 3-3-2: and (4) selecting correct data from each check unit in the two FPGA configuration program bin files by the antifuse FPGA according to the mode of the step 3-3-1 and loading the correct data into the SRAM type FPGA.
8. The method according to claim 1, wherein the step 4 specifically comprises:
step 4-1: after the digital circuit works normally, the antifuse FPGA periodically checks an FPGA configuration program bin file in NORFlash, and reports a Block number which is checked to be wrong to the SRAM type FPGA, and the SRAM type FPGA sends the serial number of the wrong NORFlash to a house keeping computer through an external communication interface and finally transmits the serial number to the ground through digital telemetering;
step 4-2: the ground can upload all correct checking units in the NORFlash block with the wrong checking to the satellite through the satellite-ground communication link, the SRAM type FPGA acquires the reinjected checking units through the external communication interface and sends the reinjected checking units to the antifuse FPGA, and the antifuse FPGA writes the checking units into the original position of the NORFlash and finally realizes the updating of error data.
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