CN109542532A - Method for loading program from FPGA configuration chip to single chip microcomputer - Google Patents
Method for loading program from FPGA configuration chip to single chip microcomputer Download PDFInfo
- Publication number
- CN109542532A CN109542532A CN201811268830.7A CN201811268830A CN109542532A CN 109542532 A CN109542532 A CN 109542532A CN 201811268830 A CN201811268830 A CN 201811268830A CN 109542532 A CN109542532 A CN 109542532A
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- China
- Prior art keywords
- program
- chip
- fpga
- chip microcontroller
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 4
- 230000037431 insertion Effects 0.000 claims description 4
- 230000008676 import Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses a method for loading programs from an FPGA configuration chip to a singlechip, which is characterized in that the singlechip program is stored in the FPGA configuration chip as user data; and the SRAM is adopted to replace the EEPROM and is used as a program storage space of the singlechip. The FPGA reads out the program of the singlechip in the configuration chip, and stores the program into the SRAM by matching with the singlechip, and then the singlechip executes the program in the SRAM. The invention solves the problems that the cost of the EEPROM import of the program storage chip of the singlechip is high and the market demand can not be met.
Description
Technical field
The present invention relates to flush type circuit fields, in particular to a kind of to add from FPGA configuration chip to single-chip microcontroller progress program
The method of load.
Background technique
In AEROSPACE APPLICATION, select electronic component when need to consider various performance indicators, as Flouride-resistani acid phesphatase, power, heat, can
By property etc., it is thus possible to which the part category for meeting application demand is relatively fewer, and many devices need to rely on import.In space flight
The SCM program storage chip EEPROM that technology is used, is a chip from external import, price is excessively high, and cannot
Guarantee the market demand.But abundant verifying is not yet received in domestic substitution chip.In this way, increasing the cost of development, work is affected
Make progress.
Summary of the invention
It is excessively high that there are prices in order to solve above-mentioned SCM program storage chip EEPROM, and is unable to asking for meet demand
Topic configures the method that chip carries out program load to single-chip microcontroller from FPGA the present invention provides a kind of.
The technical scheme adopted by the invention is that:
A method of chip is configured from FPGA and carries out program load to single-chip microcontroller, is characterized in that
1] it is stored in SCM program as user data in FPGA configuration chip；The SCM program includes monolithic
The original program of machine and program is moved for move the original program of single-chip microcontroller；
2] FPGA reads the SCM program from the configuration chip；
3] single-chip microcontroller execute in FPGA it is described move program, the original program of single-chip microcontroller configured in chip is moved into list
In the SRAM of piece machine peripheral hardware, and run the program in SRAM.
Further, step 1] specifically:
1.1] into single-chip microcontroller original program, program is moved in insertion, generates file destination；
1.2] condition code of 8 bytes is inserted into the initial position of the file destination, as user data；The feature
The starting of code user data for identification；
1.3] user data and the file destination generate together can programming file, be stored in FPGA configuration chip
In.
Further, step 2] specifically:
2.1] FPGA exports clock and drives the FPGA configuration chip output serial data；
2.2] serial data is converted into parallel data；
2.3] it identifies described document information, judges the initial position of user data；
2.4] by moving in the accessible BPRAM of program deposit single-chip microcontroller in the user data, by single-chip microcontroller original
There is program to be stored in the accessible FIFO of single-chip microcontroller when reading, and discharges monolithic processor resetting.
Further, step 3] specifically:
3.1] SCM program space zero-address is mapped to BPRAM in FPGA and executes data after monolithic processor resetting release
Program instruction is moved, data are read from FIFO, by data-moving in FIFO into single-chip microcontroller peripheral hardware SRAM；
3.2] after data-moving is completed, SCM program address pointer is directed toward SRAM, executes the instruction in SRAM, program
Load is completed.
Compared with prior art, the beneficial effects of the present invention are:
1, the program storage using SRAM substitution EEPROM as single-chip microcontroller, the application solved in space flight work need
It asks, and SRAM price is far below EEPROM, reduces costs.
2, the present invention not will increase device in circuit for the circuit simultaneously containing single-chip microcontroller and FPGA, and circuit change is few.
3, compared with prior art, the present invention moves program by insertion, realizes that the original program of single-chip microcontroller is moved
In peripheral hardware SRAM, without being stored in FPGA in RAM, FPGA type selecting storage resource index is reduced, loose single-chip microcontroller journey
The constraint of preface and table of contents mark file size.
Detailed description of the invention
Fig. 1 is that chip is configured from FPGA to single-chip microcontroller loading procedure block diagram.
Fig. 2 is the flow chart that SCM program is stored in that FPGA configures chip.
Fig. 3 is the block diagram that FPGA reads user data from configuration PROM.
Specific embodiment
The present invention is further described by 1-3 with reference to the accompanying drawing.
It is provided by the present invention to specifically include following step from FPGA configuration chip to the method that single-chip microcontroller carries out program load
It is rapid:
1] using SCM program as in the configuration chip PROM of user data deposit FPGA, the SCM program includes
There are the original program of single-chip microcontroller and the program of moving for moving the original program of single-chip microcontroller, specific implementation is as shown in Figure 2:
1.1] into single-chip microcontroller original program, program is moved in insertion, is generated file destination (.bin)；
1.2] condition code of 8 bytes is inserted into the initial position of single-chip microcontroller file destination, as user data；The spy
Levy the starting of code user data for identification；Why use 8 bytes condition code, be in order to guarantee condition code will not with
User data is obscured.
1.3] user data and FPGA file destination (.Bit file) generate together can programming file (.mcs), deposit
In the configuration PROM.
2] FPGA reads SCM program (user data) from configuration chip PROM, and specific implementation is as shown in Figure 3:
2.1] FPGA exports clock driving configuration chip PROM and exports serial data；
2.2] serial data is converted into parallel data (i.e. serioparallel exchange)；
2.3] it identifies described document information, judges the initial position of user data；
2.4] by moving in the accessible BPRAM of program deposit single-chip microcontroller in user data, the original program of single-chip microcontroller
Side is read, and side is stored in the accessible FIFO of single-chip microcontroller, and discharges monolithic processor resetting.
3] single-chip microcontroller completes program load, referring to Fig. 1:
3.1] SCM program space zero-address is mapped to BPRAM in FPGA and executes data after monolithic processor resetting release
Program instruction is moved, data are read from FIFO, by data-moving in FIFO into single-chip microcontroller peripheral hardware SRAM；
3.2] after data-moving is completed, SCM program address pointer is directed toward SRAM, executes the instruction in SRAM, program
Load is completed.
Claims (4)
1. a kind of configure the method that chip carries out program load to single-chip microcontroller from FPGA, it is characterised in that:
1] it is stored in SCM program as user data in FPGA configuration chip；The SCM program includes single-chip microcontroller original
There is program and moves program for move the original program of single-chip microcontroller；
2] FPGA reads the SCM program from the configuration chip；
3] single-chip microcontroller execute in FPGA it is described move program, the original program of single-chip microcontroller configured in chip is moved into single-chip microcontroller
In the SRAM of peripheral hardware, and run the program in SRAM.
2. according to claim 1 configure the method that chip carries out program load to single-chip microcontroller from FPGA, it is characterised in that:
Step 1] specifically:
1.1] into single-chip microcontroller original program, program is moved in insertion, generates file destination；
1.2] condition code of 8 bytes is inserted into the initial position of the file destination, as user data；Described document information is used
In the starting of identification user data；
1.3] user data and the file destination generate together can programming file, be stored in FPGA configuration chip.
3. according to claim 2 configure the method that chip carries out program load to single-chip microcontroller from FPGA, it is characterised in that:
Step 2] specifically:
2.1] FPGA exports clock and drives the FPGA configuration chip output serial data；
2.2] serial data is converted into parallel data；
2.3] it identifies described document information, judges the initial position of user data；
2.4] by moving in the accessible BPRAM of program deposit single-chip microcontroller in the user data, by the original journey of single-chip microcontroller
Sequence is stored in the accessible FIFO of single-chip microcontroller when reading, and discharges monolithic processor resetting.
4. according to claim 3 configure the method that chip carries out program load to single-chip microcontroller from FPGA, it is characterised in that:
Step 3] specifically:
3.1] SCM program space zero-address is mapped to BPRAM in FPGA and executes data-moving after monolithic processor resetting release
Program instruction reads data from FIFO, by data-moving in FIFO into single-chip microcontroller peripheral hardware SRAM；
3.2] after data-moving is completed, SCM program address pointer is directed toward SRAM, executes the instruction in SRAM, program load
It completes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811268830.7A CN109542532A (en) | 2018-10-29 | 2018-10-29 | Method for loading program from FPGA configuration chip to single chip microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811268830.7A CN109542532A (en) | 2018-10-29 | 2018-10-29 | Method for loading program from FPGA configuration chip to single chip microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109542532A true CN109542532A (en) | 2019-03-29 |
Family
ID=65845764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811268830.7A Pending CN109542532A (en) | 2018-10-29 | 2018-10-29 | Method for loading program from FPGA configuration chip to single chip microcomputer |
Country Status (1)
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| CN (1) | CN109542532A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111856989A (en) * | 2020-06-19 | 2020-10-30 | 中电科航空电子有限公司 | Dynamic linking method for single chip microcomputer |
| CN114924808A (en) * | 2022-05-12 | 2022-08-19 | 中国电子科技集团公司第二十九研究所 | SRAM type FPGA on-orbit reliable loading method based on duplicate storage program |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1598772A (en) * | 2004-08-31 | 2005-03-23 | 四川长虹电器股份有限公司 | Program updating method of single chip processor |
| CN1889494A (en) * | 2006-06-26 | 2007-01-03 | 株洲南车时代电气股份有限公司 | Multi-bus automobile communication control module based on TCN |
| CN101901156A (en) * | 2010-07-26 | 2010-12-01 | 四川九洲电器集团有限责任公司 | Method and system for dynamically loading processor application programs |
| CN103530140A (en) * | 2012-07-06 | 2014-01-22 | 河南思维自动化设备股份有限公司 | Online programming system for early-stage single chip microcomputer system and method thereof |
-
2018
- 2018-10-29 CN CN201811268830.7A patent/CN109542532A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1598772A (en) * | 2004-08-31 | 2005-03-23 | 四川长虹电器股份有限公司 | Program updating method of single chip processor |
| CN1889494A (en) * | 2006-06-26 | 2007-01-03 | 株洲南车时代电气股份有限公司 | Multi-bus automobile communication control module based on TCN |
| CN101901156A (en) * | 2010-07-26 | 2010-12-01 | 四川九洲电器集团有限责任公司 | Method and system for dynamically loading processor application programs |
| CN103530140A (en) * | 2012-07-06 | 2014-01-22 | 河南思维自动化设备股份有限公司 | Online programming system for early-stage single chip microcomputer system and method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111856989A (en) * | 2020-06-19 | 2020-10-30 | 中电科航空电子有限公司 | Dynamic linking method for single chip microcomputer |
| CN114924808A (en) * | 2022-05-12 | 2022-08-19 | 中国电子科技集团公司第二十九研究所 | SRAM type FPGA on-orbit reliable loading method based on duplicate storage program |
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Application publication date: 20190329 |
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