CN109614122B - Satellite-borne multiprocessor software on-orbit programming system and design method thereof - Google Patents
Satellite-borne multiprocessor software on-orbit programming system and design method thereof Download PDFInfo
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- CN109614122B CN109614122B CN201811494157.9A CN201811494157A CN109614122B CN 109614122 B CN109614122 B CN 109614122B CN 201811494157 A CN201811494157 A CN 201811494157A CN 109614122 B CN109614122 B CN 109614122B
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Abstract
The invention discloses an on-orbit programming system of satellite-borne multiprocessor software and a design method thereof, wherein the system comprises the following components: the chip comprises a single anti-fuse type FPGA chip, a plurality of PROM chips, a single NOR FLASH chip and a plurality of processor chips; the invention discloses an on-orbit programming design method of satellite-borne multiprocessor software, which stores on-orbit programming software of a plurality of processor chips in different partitions of a single NOR FLASH chip. According to the invention, the on-orbit programming software of a plurality of large-scale processors injected on the ground is solidified into the same high-capacity NOR FLASH chip through the management FPGA software stored in the anti-fuse type FPGA chip, so that the hardware cost and complexity are reduced, and the on-orbit programming code is not lost after power failure; the original safety software of each processor is stored in the respective PROM, the FPGA software is managed to control the original safety program loaded from the PROM or the on-track programming program of the corresponding processor loaded from a certain partition of the NOR FLASH chip, and the operation is flexible.
Description
Technical Field
The invention relates to the technical field of satellite-borne software, in particular to an on-orbit programming system of satellite-borne multiprocessor software and a design method thereof.
Background
The satellite-borne software is embedded software running on a satellite-borne processor and is a control core of a satellite. After the satellite is launched, on-orbit modification or upgrade maintenance of software codes needs to be realized due to the defects of software, software function upgrade and the like, and an on-orbit programming technology is a feasible technical means, so that the availability and reliability of the satellite are greatly improved. The increasing complexity of the satellite functions brings about the increasing number of satellite-borne processors and the increasing scale of satellite-borne software codes, the existing on-orbit programming method has certain limitation, and how to design a simple and practical on-orbit programming method of the satellite-borne multiprocessor software is very important.
Non-patent document "design and implementation technology of on-orbit programming function of satellite-borne software" implements on-orbit programming by injecting a subprogram and modifying an entry address of the subprogram in an address table, does not need an external memory, is not suitable for large-scale on-orbit programming of software, and an on-orbit programming code cannot be solidified, and once power is off or reset, on-orbit programming needs to be carried out again, so that normal operation of a satellite task is influenced. Non-patent document 'research on spaceborne software reconstruction technology based on ARM + Uc/OS-II' proposes an ARM instruction dynamic reconstruction method, and the method is only suitable for on-orbit programming of software adopting an ARM processor + Uc/OS-II operating system structure and has limitation.
Patent document CN105373411A, "an on-orbit programming system and design method for satellite-borne digital signal processor", only implements on-orbit programming for satellite-borne DSP (digital signal processor) software, is not suitable for on-orbit programming for satellite-borne FPGA (programmable gate array) software, and the on-orbit programming code cannot be solidified. Patent document CN107391189A discloses an on-orbit programming method for satellite-borne software, which proposes a method for implementing on-orbit programming by using EEPROM (electrically erasable programmable read only memory), but the EEPROM has relatively small capacity, and requires multiple EEPROM chips to implement on-orbit programming of large-scale software or multiple processor software, thereby increasing hardware cost and complexity. Patent document CN107168721A, entitled "device, method, and method for loading and loading concentrated storage of satellite-borne multiprocessor software", uses a bus and a plurality of control chips to implement loading and updating of satellite-borne multiprocessor software, and has a complex control logic, which is completely different from the contents described in the present invention.
Disclosure of Invention
The invention aims to provide an on-orbit programming system of satellite-borne multiprocessor software and a design method thereof, wherein the original safety software of each satellite-borne multiprocessor software is stored in a respective PROM (programmable read only memory), a plurality of large-scale processor software injected on the ground are solidified into the same high-capacity NOR FLASH (nonvolatile FLASH memory) chip under the control of the management FPGA software stored in an antifuse type FPGA chip, and the original safety software of the processor loaded from the PROM or the on-orbit programming software of a corresponding processor loaded from a certain partition of the NOR FLASH chip can be controlled.
In order to achieve the purpose, the invention is realized by the following technical scheme:
an on-board multiprocessor software in-orbit programming system, comprising:
a monolithic antifuse-type FPGA chip;
the data lines and the control lines of the plurality of PROM chips are connected with the anti-fuse type FPGA chip;
the address line, the data line and the control line of the single-chip NOR FLASH chip are connected with the anti-fuse type FPGA chip;
and the loading configuration pins of the multi-chip processor chip are connected with the anti-fuse type FPGA chip.
Preferably, the single-chip antifuse-type FPGA chip is used for storing and managing FPGA software, automatically operates after being electrified, and realizes a remote control injection function and loading control on multiprocessor software;
the plurality of PROM chips are used for storing respective original safety software of the plurality of processor chips;
the single-chip NOR FLASH chip is used for storing the respective on-track programming software of the multi-chip processor chip in a partitioning manner;
the multi-chip processor chip controls the original security software loaded from the multi-chip PROM chip or the on-orbit programming software of the corresponding processor loaded from a certain partition of the single NOR FLASH chip through the management FPGA software stored in the single anti-fuse type FPGA chip, and each processor chip realizes respective function.
A design method based on the on-orbit programming system of the satellite-borne multiprocessor software comprises the following steps:
s1, after the system is powered on, managing the FPGA software to load the original safety software of each satellite-borne processor chip from the PROM chip by default, and enabling the system to work normally;
s2, if one or more satellite processor software needs to be programmed on the orbit, the on-orbit programming program design is carried out on the ground computer;
s3, generating program binary codes of certain or several satellite-borne processor software which need to be subjected to on-orbit programming by using a program compiler, and performing EDAC (electronic design automation) coding protection on data to generate respective on-orbit programming upper injection codes;
s4, writing in-orbit programming upper note codes of different satellite-borne processor chips into corresponding partitions of the same NOR FLASH chip through an antifuse type FPGA chip by adopting a remote note number mode;
and S5, after successful injection, selecting the antifuse-type FPGA chip through a remote control instruction, loading the injected on-orbit programming software code from the corresponding partition of the NOR FLASH chip into the corresponding on-board processor chip, and realizing on-orbit programming.
Preferably, during the on-track programming, encoding and software uploading process of steps S2-S4, each on-board processor chip is still running the original security software.
Preferably, if the software program of one or more onboard processor chips needs to be modified again, the process jumps back to step S2, and the steps S2 to S5 are executed again.
Preferably, if one or more satellite-borne processor chips need to return original security software, only the anti-fuse type FPGA chip needs to be selected through a remote control instruction to load the original security software of each satellite-borne processor chip from the PROM chip.
Compared with the prior art, the invention has the following advantages:
according to the invention, a plurality of large-scale processor software injected on the ground are solidified into the same high-capacity NOR FLASH chip through the management FPGA software stored in the anti-fuse type FPGA chip, so that the hardware cost and complexity are reduced, and the on-track programming code is not lost after power failure; the original safety software of each processor is stored in the respective PROM, the FPGA software is managed to control the original safety program loaded from the PROM or the on-track programming program of the corresponding processor loaded from a certain partition of the NOR FLASH chip, and the operation is flexible.
Drawings
FIG. 1 is a block diagram of an on-board multiprocessor software in-orbit programming system according to the present invention;
FIG. 2 is a flowchart of a design method for on-orbit programming of on-board multiprocessor software according to the present invention.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
As shown in fig. 1, an on-board multiprocessor software on-track programming system includes: the single anti-fuse type FPGA chip is a control core of the whole system; the data lines and the control lines of the plurality of PROM chips are connected with the anti-fuse type FPGA chip; the address line, the data line and the control line of the single-chip NOR FLASH chip are connected with the anti-fuse type FPGA chip; and the loading configuration pins of the multi-chip processor chip are connected with the anti-fuse type FPGA chip.
The single anti-fuse type FPGA chip is used for storing and managing FPGA software, automatically operates after being powered on, and realizes a remote control injection function and loading control on multiprocessor software;
the plurality of PROM chips have the characteristics of high reliability and non-reprogrammability and are used for storing respective original safety software of the multiprocessor chips;
the single-chip NOR FLASH chip has large storage capacity and supports reprogrammable support, is used for storing the respective on-track programming software of the multi-chip processor chip in a partitioning manner, reduces the hardware cost and complexity, and does not lose on-track programming codes after power failure;
the multi-chip processor chip controls the original security software loaded from the multi-chip PROM chip or the on-orbit programming software of the corresponding processor loaded from a certain partition of the single NOR FLASH chip through the management FPGA software stored in the single anti-fuse type FPGA chip, and each processor chip realizes respective function.
Specifically, the monolithic antifuse-type FPGA chip in this example selects AX2000-1CG624M of ACTEL corporation for storing and managing FPGA software, operates automatically after being powered on, realizes a remote control injection function and loading control on multiprocessor software, and is a control core of the whole system;
the processor chip in the example selects SRAM type FPGA of XILINX company, the specific model specification is XQR4VSX55, each FPGA chip realizes respective function, and the data volume of each configuration software is 21.69 Mbit;
the PROM chip in the example selects XQR17V16CC44V of XILINX company, the storage capacity is 16Mbit, and aiming at the configuration software data volume of the XQR4VSX55 processor selected in the example, each processor needs to be provided with 2 PROM chips for storing respective original safety software;
the single-chip NOR FLASH chip in the embodiment selects 3DFO256M16VS4269 of 3D PLUS company, the storage capacity of the NOR FLASH is 256Mbit, the data volume of the XQR4VSX55 processor selected in the embodiment is considered to be encoding efficiency and storage efficiency, the size of a storage unit actually occupied by the software of the single-chip processor is 34.7Mbit, the single-chip NOR FLASH chip in the embodiment can store the configuration software of 7 processors, the hardware cost and complexity are reduced, and the on-track programming code is not lost after power failure.
In this example, preferably, as shown in FIG. 1, the 7 load configuration pins CCLK, DONE, PROG _ B, RDWR _ B, BUSY, CS _ B, INIT _ B of each XQR4VSX55 processor chip are all connected to an antifuse-type FPGA chip AX2000-1CG 624M.
In this example, as shown in fig. 1, the data lines D0-D7 and the control lines OE, CE, CLK, BUSY of each PROM chip are preferably connected to the antifuse-type FPGA chip AX2000-1CG 624M.
In this example, as shown in FIG. 1, the address lines A0-A21, the data lines D0-D15 and the control lines RESET, OE, WE, CE 0-CE 3, WP/ACC 0-WP/ACC 3, BYTE, RY/BY of the monolithic NOR FLASH chip are all connected with the antifuse type FPGA chip AX2000-1CG 624M.
The on-board multiprocessor software on-orbit programming system according to the embodiment of the invention is described above with reference to fig. 1. Further, the invention also discloses a design method based on the system, which comprises the following steps:
after the system is powered on, managing the original safety software of each satellite-borne processor chip loaded from a PROM chip by default by FPGA software, and enabling the system to work normally;
step two, if one or more satellite-borne processor software needs to be subjected to on-orbit programming, performing on-orbit programming on a ground computer;
generating a program binary code of certain or several satellite-borne processor software which needs on-track programming by using a program compiler, and performing EDAC (electronic design automation) coding protection on data, wherein the coding mode is (8, 4) Hamming codes, the coding efficiency is 2/3, namely 66.67%, namely 4-bit supervisory bit data needs to be added to single byte data, and respective on-track programming upper injection codes are generated;
writing in on-track programming upper-note codes of different satellite-borne processor chips into corresponding partitions of the same NOR FLASH chip through an antifuse type FPGA chip in a remote control note number mode, writing in a page mode during upper note, wherein 128 bytes are written in each page, the length of a single software upper-note data packet is limited to 240 bytes, writing is performed in two pages, each page has 8-byte redundancy, namely the storage efficiency is 120/128, namely 93.75%;
and step five, after successful uploading, selecting the anti-fuse type FPGA chip through a remote control instruction to load the uploaded and uploaded on-orbit programming software code from the corresponding partition of the NOR FLASH chip into the corresponding on-board processor chip, thereby realizing on-orbit programming.
In the on-orbit programming program design, coding and software uploading process from the second step to the fourth step, each satellite-borne processor chip still runs original safety software, and the normal work of the system is not influenced.
And if the software program of one or more satellite-borne processor chips needs to be modified again, jumping back to the step two, and re-executing the step two to the step five.
If one or more satellite-borne processor chips need to return to original safety software, the anti-fuse type FPGA chip is selected through a remote control instruction to load the original safety software of each satellite-borne processor from the PROM chip.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (5)
1. A design method based on an on-board multiprocessor software on-board programming system comprises the following steps: a monolithic antifuse-type FPGA chip; the data lines and the control lines of the plurality of PROM chips are connected with the anti-fuse type FPGA chip; the address line, the data line and the control line of the single-chip NOR FLASH chip are connected with the anti-fuse type FPGA chip; the multi-chip processor chip is characterized by comprising the following steps of:
s1, after the system is powered on, managing the FPGA software to load the original safety software of each satellite-borne processor chip from the PROM chip by default, and enabling the system to work normally;
s2, if one or more satellite processor software needs to be programmed on the orbit, the on-orbit programming program design is carried out on the ground computer;
s3, generating program binary codes of one or more satellite-borne processor software which need to be subjected to on-orbit programming by using a program compiler, and performing EDAC (electronic design automation) coding protection on data to generate respective on-orbit programming upper injection codes;
s4, writing in-orbit programming upper note codes of different satellite-borne processor chips into corresponding partitions of the same NOR FLASH chip through an antifuse type FPGA chip by adopting a remote note number mode;
and S5, after successful injection, selecting the antifuse-type FPGA chip through a remote control instruction, loading the injected on-orbit programming software code from the corresponding partition of the NOR FLASH chip into the corresponding on-board processor chip, and realizing on-orbit programming.
2. The design method of claim 1, wherein during the on-track programming, encoding and software uploading process of steps S2-S4, each on-board processor chip is still running original security software.
3. The design method of claim 1, further comprising: if the software program of one or more onboard processor chips needs to be modified again, the process jumps back to step S2, and the steps S2 to S5 are executed again.
4. The design method of any one of claims 1-3, further comprising: if one or more satellite-borne processor chips need to return to original safety software, only the anti-fuse type FPGA chip needs to be selected through a remote control instruction to load the original safety software of each satellite-borne processor chip from the PROM chip.
5. The design method of claim 1, wherein the single anti-fuse type FPGA chip is used for storing and managing FPGA software, automatically operates after being powered on, and realizes a remote control annotating function and loading control on multiprocessor software;
the plurality of PROM chips are used for storing respective original safety software of the plurality of processor chips;
the single-chip NOR FLASH chip is used for storing the respective on-track programming software of the multi-chip processor chip in a partitioning manner;
the multi-chip processor chip controls the original security software loaded from the multi-chip PROM chip or the on-orbit programming software of the corresponding processor chip loaded from a certain partition of the single NOR FLASH chip through the management FPGA software stored in the single anti-fuse type FPGA chip, and each processor chip realizes respective function.
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| CN110674046B (en) * | 2019-09-24 | 2023-08-01 | 上海航天电子通讯设备研究所 | Method for improving reliability of satellite-borne embedded file system |
| CN110929465A (en) * | 2019-11-19 | 2020-03-27 | 深圳航天东方红海特卫星有限公司 | Reconfigurable reliability design system and method based on FPGA industrial device |
| CN111611201B (en) * | 2020-06-24 | 2022-04-19 | 中国人民解放军国防科技大学 | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method |
| CN111880841A (en) * | 2020-07-28 | 2020-11-03 | 西安微电子技术研究所 | Program reconstruction method, system and equipment of satellite-borne solid-state memory |
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