CN113867836A - Device for FPGA, program dynamic loading method and data transmission method - Google Patents
Device for FPGA, program dynamic loading method and data transmission method Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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Abstract
The application relates to the technical field of embedded system application, and discloses a device for an FPGA, which comprises: an upper computer; the Zynq chip is configured to establish a first program loading channel based on a PCIe bus protocol with the upper computer; the FPGA chip is configured to establish a second program loading channel based on a PCIe bus protocol with the Zynq chip; the upper computer sends a program file to be loaded to the Zynq chip through the first program loading channel, and the Zynq chip sends the program file to be loaded to the FPGA chip through the second program loading channel, so that the FPGA chip loads the program file to be loaded. According to the method and the device, the loading rate of the FPGA chip to the program file and the data transmission continuity can be improved, and the integration and integration degree of the platform can be improved. The application also discloses a method for dynamic loading and data transmission of the FPGA program.
Description
Technical Field
The present application relates to the field of embedded system application technologies, and for example, to an apparatus for an FPGA, a program dynamic loading method, and a data transmission method.
Background
A Field Programmable Gate Array (FPGA) is a Static Random-Access Memory (SRAM) based Field Programmable logic device, and is a core device in a software radio platform. With the improvement of the requirements on the flexibility and the openness of a modern communication system, the software radio platform has new requirements on loading a program loading file on an FPGA chip.
In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:
when the existing software wireless level station loads a program file on an FPGA chip, the whole system needs to be powered on again or loaded again, and the loading process is complicated while the work of other devices is influenced. Meanwhile, when a Joint Test Action Group (JTAG) working mode is adopted, it is not a common link mode of a software radio platform, and requires an external connection line, resulting in poor integration and integration degree, and dynamic loading in a true sense is not realized.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a device for FPGA, a method for dynamically loading an FPGA program, a method for transmitting FPGA data and a software radio platform, so as to improve the loading rate of an FPGA chip to a program file and the continuity of data transmission and improve the integration and integration degree of the platform.
In some embodiments, the apparatus comprises:
an upper computer;
the Zynq chip is configured to establish a first program loading channel based on a PCIe bus protocol with the upper computer;
the FPGA chip is configured to establish a second program loading channel based on a PCIe bus protocol with the Zynq chip;
the upper computer sends a program file to be loaded to the Zynq chip through the first program loading channel, and the Zynq chip sends the program file to be loaded to the FPGA chip through the second program loading channel, so that the FPGA chip loads the program file to be loaded.
In some embodiments, the method for dynamic loading of FPGA programs comprises:
the upper computer sends a configuration program file to the Zynq chip through a first program loading channel so as to establish a second program loading channel based on a PCIe bus protocol between the Zynq chip and the FPGA chip, and the Zynq chip sends a digital signal indicating that the configuration is finished to the upper computer after the configuration is finished;
the upper computer sends a program loading instruction to the Zynq chip through a first program loading channel, and sends a program file to be loaded to the Zynq chip through the first program loading channel;
the Zynq chip receives the program file to be loaded according to the program loading instruction and sends the program file to be loaded to the FPGA chip through a second program loading channel;
the FPGA chip receives and loads the program file to be loaded through a second program loading channel, loading completion information generated after loading is completed is sent to the Zynq chip through a DONE pin, and the Zynq chip sends the loading completion information to the upper computer through a base address register of a PCIe bus protocol.
In some embodiments, the method for FPGA data transmission comprises:
the upper computer sends data to be processed to the Zynq chip through a first data transmission channel;
the Zynq chip sends the data to be processed to an FPGA chip through a second data transmission channel so that the FPGA chip processes the data to be processed;
the FPGA chip sends processing process data and/or processing result data which need to be observed or displayed in the processing process to the Zynq chip through the second data transmission channel;
and the Zynq chip receives and sends the processing process data and/or the processing result data to the upper computer through a first data transmission channel, so that the upper computer displays the processing process data and/or the processing result data.
In some embodiments, the software radio platform comprises an apparatus for FPGA as described above.
The device for FPGA, the method for dynamically loading the FPGA program, the method for transmitting the FPGA data and the software radio platform provided by the embodiment of the disclosure can realize the following technical effects:
according to the method, the first program loading channel and the second program loading channel based on the PCIe bus protocol are respectively established between the upper computer, the Zynq chip and the FPGA chip, the Zynq chip controls the FPGA chip to be loaded, program files are burnt and fed back, the FPGA program files are efficiently and quickly loaded based on the PCIe bus protocol, the system does not need to be reloaded or the FPGA chip is powered on again in the loading process, meanwhile, the work of other devices cannot be influenced, the FPGA program files are dynamically loaded in the real sense, bidirectional data transmission between the upper computer and the loaded FPGA chip can be realized, and the completeness and diversity of hardware structure functions are guaranteed.
In addition, the software radio platform of this application lays host computer, Zynq chip and FPGA chip through PCIe bus mode, has guaranteed the integration and the integration of platform for the human-computer interaction process is more simple and convenient clear, thereby has promoted software radio platform's work efficiency.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is an architecture diagram of an apparatus for an FPGA provided by an embodiment of the present disclosure;
fig. 2 is a signal connection diagram of the Zynq chip and the upper computer provided by the embodiment of the disclosure;
FIG. 3 is a schematic diagram of a method for dynamically loading an FPGA program according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a method for reading a program file to be loaded from an upper computer by a Zynq chip according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a method for receiving and loading the program file to be loaded by the FPGA chip through the second program loading channel according to the embodiment of the present disclosure;
fig. 6 is a pin connection diagram of a Zynq chip and an FPGA chip provided in the embodiments of the present disclosure;
fig. 7 is a schematic diagram of a method for transferring information of load completion by a Zynq chip according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a method for FPGA data transmission according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.
In the embodiment of the disclosure, the upper computer is a computer which can directly send out a control command, and various signal changes can be displayed on a screen of the upper computer; the Zynq chip is a heterogeneous multiprocessor system structure which is provided by the company of saint and adopts an ARM (advanced RISC machine) processor and combines with an FPGA (field programmable gate array), takes the ARM processor as a core, has the programmability of the FPGA and has the high performance and the low power consumption of an Application Specific Integrated Circuit (ASIC) chip; the PCI (Peripheral Component Interconnect-express) bus protocol is a high-speed serial computer expansion bus standard, and the PCIe bus protocol is an end-to-end interconnection protocol, which provides a solution for high-speed transmission bandwidth. PCIe has been developed to the fourth generation PCIe4.0 at present, and the most obvious feature of each generation development is the doubling of speed; the Aurora protocol is an open free link layer protocol provided by the saint company, can be used for point-to-point serial data transmission, and has the characteristics of high efficiency, simplicity and easiness in use for realizing a high-performance data transmission system; the FPGA chip comprises a Programmable Logic (PL) end, a Processor System (PS) end and a Block Random Access Memory (BRAM), the Random Access Memory (BRAM) serving as the PL end of the Zynq chip can be configured as a dual-port RAM, and is used for realizing data interaction and sharing from the PS end to the PL end in the Zynq chip, similar to Memory sharing in a Linux System, namely, data is written into a commonly accessible data space, the PS end and the PL end Access to achieve the purpose of information exchange, the A port of the BRAM is designated as a write port, and the B port of the BRAM is designated as a read port.
Referring to fig. 1, an embodiment of the present disclosure provides an apparatus for an FPGA, including:
an upper computer 101;
the Zynq chip 102 is configured to establish a first program loading channel based on a PCIe bus protocol with the upper computer;
the FPGA chip 103 is configured to establish a second program loading channel based on a PCIe bus protocol with the Zynq chip;
the upper computer 101 sends a program file to be loaded to the Zynq chip 102 through the first program loading channel, and the Zynq chip 102 sends the program file to be loaded to the FPGA chip 103 through the second program loading channel, so that the FPGA chip 103 loads the program file to be loaded.
In the embodiment of the application, the upper computer 101 writes a configuration program to the Zynq chip 102 through a first program loading channel established based on a PCIe bus protocol, so that a second program loading channel based on the PCIe bus protocol is established between the FPGA chip 103 and the Zynq chip 102. Further, the upper computer transmits the program file to be loaded to the Zynq chip 102 through a first program loading channel, the Zynq chip 102 sends the program file to be loaded to the FPGA chip 103 through second program loading, and therefore the Zynq chip 102 serves as a transfer point of data exchange to control programming and information feedback of the program file to be loaded of the FPGA chip 103.
Optionally, the embedded board card may be a computer platform built based on intel X86.
Alternatively, the FPGA chip can be a programmable logic device chip of the XC7VX690T series, such as XC7VX690T-2FFG 1926.
Alternatively, the Zynq chip may be an XC7Z045 family of programmable logic device chips, such as XC7Z045-2FFG 676E.
Optionally, the first program loading channel and the second program loading channel are program programming channels of unidirectional transmission based on a PCIe bus protocol.
According to the method, the first program loading channel and the second program loading channel based on the PCIe bus protocol are respectively established between the upper computer, the Zynq chip and the FPGA chip, the Zynq chip controls the programming and information feedback of the program files to be loaded of the FPGA chip as the transit of data exchange, and therefore the high-efficiency and quick loading of the FPGA program files is achieved based on the PCIe bus protocol, the system does not need to be reloaded or the FPGA is powered on again in the loading process, meanwhile, the work of other devices cannot be influenced, the dynamic loading of the FPGA program files is truly achieved, bidirectional data transmission between the upper computer and the loaded and completed FPGA chip can be achieved, and the completeness and diversity of hardware structure functions are guaranteed.
Optionally, the Zynq chip is further configured to:
and a first data transmission channel based on a PCIe bus protocol is established between the upper computer and the Zynq chip, so that data transmission is carried out between the upper computer and the Zynq chip through the first data transmission channel.
Optionally, the FPGA chip is further configured to:
and a second data transmission channel based on an Aurora protocol is established between the FPGA chip and the Zynq chip, so that the FPGA chip and the Zynq chip can carry out data transmission through the second data transmission channel.
In an embodiment of the application, the first data transmission channel and the second data transmission channel are data transmission channels for bidirectional transmission, and at the same time, the Zynq chip may adjust the data transmission mode of the second data transmission channel according to different kinds of configuration program files selected by the upper computer, where the data transmission mode includes a unidirectional transmission mode of a full duplex mode or a simplex mode or a unidirectional reception mode of a simplex mode, and may also select and control parameters such as a data rate, a user interface mode, and whether to add a user flow control signal.
Therefore, the configuration and program loading selection of the FPGA chip can be better performed through the Zynq chip, and the personalized adjustment of the FPGA chip by a user is realized on the premise of ensuring the rapid transmission.
Optionally, as shown in fig. 2, the Zynq chip includes:
the programmable logic module 201 is configured to be in communication connection with the upper computer through the first program loading channel and the first data transmission channel, and is in communication connection with the FPGA chip through the second program loading channel and the second data transmission channel;
a processor system module 202 configured to configure the FPGA chip and the external device;
a data buffer module 203 configured to be communicatively coupled to the programmable logic module and the processor system module, respectively.
In an embodiment of the present application, the programmable logic module 201 is a PL end of the Zynq chip, the processor system module 202 is a PS end of the Zynq chip, and the data buffer module 203 is a BRAM of the PL end of the Zynq chip, where the processor system module 202 is responsible for configuring, initializing, and resetting an FPGA chip, a digital signal processing chip, and an external device (e.g., a clock distributor, a clock chip, etc.), and the programmable logic module 201 is responsible for an interface of a first data transmission channel and an interface of a first program loading channel between the Zynq chip and an upper computer, and is also responsible for an interface of a second data transmission channel and an interface of a second program loading channel between the Zynq chip and the FPGA chip. And the DONE pin of the FPGA chip and the DONE pin of the Zynq chip are mutually communicated to be used as a feedback transmission path of the loading signal.
In practical application, the upper computer is configured with an embedded Board card and a case supporting a PCIe bus protocol, the Zynq chip and the FPGA chip are loaded into the case through a Printed Circuit Board (PCB), and the case is connected by a power line. Therefore, integration and integration of the software wireless platform can be better realized, the occupied space of the device is reduced, and the deployment is convenient in various occasions.
Referring to fig. 3, an embodiment of the present disclosure provides a method for dynamically loading an FPGA program, including:
step 301: the upper computer sends a configuration program file to the Zynq chip through a first program loading channel so as to establish a second program loading channel based on a PCIe bus protocol between the Zynq chip and the FPGA chip, and the Zynq chip sends a digital signal indicating that the configuration is finished to the upper computer after the configuration is finished.
Step 302: the upper computer sends a program loading instruction to the Zynq chip through the first program loading channel, and sends a program file to be loaded to the Zynq chip through the first program loading channel.
Step 303: and the Zynq chip receives the program file to be loaded according to the program loading instruction and sends the program file to be loaded to the FPGA chip through a second program loading channel.
Step 304: the FPGA chip receives and loads the program file to be loaded through a second program loading channel, loading completion information generated after loading is completed is sent to the Zynq chip through a DONE pin, and the Zynq chip sends the loading completion information to the upper computer through a base address register of a PCIe bus protocol.
In the embodiment of the application, the host computer sends the configuration program file to the Zynq chip through first program loading passageway for establish the second data transmission passageway and the second program loading passageway of Zynq chip and FPGA chip, the FPGA chip will load 1 bit digital signal that produces after finishing and send through the DONE pin Zynq chip, the Zynq chip will 1 bit digital signal sends through the base address register of PCIe bus protocol to the host computer.
The upper computer transmits a program file to be loaded to the Zynq chip in a bin file form through a first program loading channel based on a PCIe bus protocol, simultaneously transmits a program loading instruction to the Zynq chip through a first data transmission channel based on the PCIe bus protocol, after the Zynq chip receives the program loading instruction, the program file to be loaded is transmitted to the FPGA chip to be loaded through a second program loading channel based on the PCIe bus protocol in a bin file form, so that the FPGA chip loads the program file to be loaded, after the loading is completed, the FPGA chip can transmit data which are required to be observed or displayed by a user in the running process of a target program to the Zynq chip through a second data transmission channel based on an Aurora protocol, or receive data transmitted by the Zynq chip from the upper computer, and correspond to the data, the upper computer can also transmit data needing to be transmitted to the FPGA chip to the Zynq chip through a first data transmission channel based on a PCIe bus protocol, and receive the data stored in the Zynq chip and transmitted from the FPGA chip through the first data transmission channel.
By adopting the method for dynamically loading the FPGA program, the PCIe bus protocol is used for transmitting and configuring the program file, the Zynq chip is used as a transfer point for program loading to control the upper computer to dynamically load the program of the FPGA chip, so that the problem that the existing FPGA chip needs to be reloaded with a system or be electrified again is solved, other devices working simultaneously in the platform are not influenced in the loading process, the program dynamic loading of the FPGA is truly realized, the man-machine interaction is simpler and clearer, and the working efficiency of the platform is greatly improved.
Optionally, the sending, by the upper computer, the program loading instruction to the Zynq chip through the first program loading channel, and sending the program file to be loaded to the Zynq chip through the first program loading channel includes:
step 3011: and the upper computer sends a program loading instruction to the Zynq chip through the first program loading channel.
Step 3012: the Zynq chip reads the program file to be loaded in the binary format through the first program loading channel based on the PCIe bus protocol.
Step 3013: and the Zynq chip caches and extracts the program file to be loaded in a ping-pong operation mode through two data buffer modules.
In the embodiment of the present application, as shown in fig. 2, an upper computer is connected to a PL end of a Zynq chip through a first program loading channel based on a PCIe bus protocol, the Zynq chip generates two Block Memory Generators (BMG) and BRAM controllers of two AXI (advanced eXtensible interface) bus protocols, each BRAM controller is connected to a PS end of the Zynq chip through an S _ AXI pin, each BRAM controller is connected to an a port of a BRAM of the Zynq chip through a BRAM _ PORTA port, and a B port of the BRAM is configured to be connected to a configurator in the PL end of the Zynq chip.
After a Random Access Memory (RAM) environment is generated, the Zynq chip reads a program file to be loaded from an upper computer through a first program loading channel based on a PCIe bus protocol, and accesses the program file from two Random Access memories in a ping-pong manner. Wherein, the whole holding operation is as follows: at the first address of the RAM, the upper computer writes 0x00000000 through the first program loading channel to represent that the writing of the RAM data is finished; and 0xffffffff is written into the PL end of the Zynq chip to indicate that the reading of the RAM data is finished.
As shown in fig. 4, the above process specifically includes the following steps:
step 401: the PL side of the Zynq chip writes all f's at the RAM1 first address, indicating that it is ready to receive configuration data.
Step 402: after the upper computer reads the first address data of the RAM1 as full f through the first program loading channel, 8188 bytes of data of the configuration data are written into the RAM1, and after the data are written, the first address data of the RAM1 are written as full 0.
Step 403: when the PL terminal of the Zynq chip detects that the first address data of the RAM1 is 0, the data of the RAM1 is read, and the first address data of the RAM2 is written as full f.
Step 404: when the upper computer detects that the first address data of the RAM2 is full f through the first program loading channel, the read configuration data 8188 bytes are written into the RAM2, and after the write, the first address data of the RAM2 is set to be 0.
Step 405: the PL end of the Zynq chip reads data in the RAM2, and the first address data of the RAM1 is set to be full f.
Step 406: and repeating the steps until the PL end of the Zynq chip finishes reading and writing all data of the RAM.
The process of writing the memory data into the PCIe bus protocol is as follows: and writing 32 bits once every 30 clock cycles, wherein the write data clock of the PCIe bus protocol is 100MHz, and the read data clock of the PL end of the Zynq chip is 50 MHz.
Therefore, the Zynq chip can reliably and stably ensure that the program files to be loaded are completely read on the premise of realizing high-speed data transmission.
Optionally, as shown in fig. 5, the receiving and loading the to-be-loaded program file by the FPGA chip through the second program loading channel includes:
step 501: and powering on the FPGA chip or resetting the configuration so as to enable the FPGA chip to start a configuration program.
Step 502: and initializing the FPGA chip.
Step 503: and after the initialization is finished, the FPGA chip acquires a program file to be loaded and configures a clock signal for the FPGA chip.
Step 504: after the program file to be loaded is completely written, judging whether an INIT _ B pin of the FPGA chip is at a high level; if yes, go to step 505; if not, indicating that the configuration data of the program file to be loaded is loaded wrongly and selecting to reconfigure the FPGA chip
Step 505: and starting condition compensation and detecting whether the DONE pin of the FPGA chip is at a high level. If so, determining that the loading of the program file to be loaded is finished and selecting to reconfigure the FPGA chip; if not, the loading of the program file to be loaded is overtime, and the FPGA chip can be reconfigured.
In the embodiment of the present application, as shown in fig. 6, the FPGA chip starts a configuration program,
configuring a PROGRAM _ B pin and an INIT _ B pin of the FPGA chip to be low level so as to initialize the FPGA chip, acquiring a PROGRAM file to be loaded through a din pin of the FPGA chip when the INIT _ B pin of the FPGA chip is changed to be high level, configuring a clock signal to a CCLK pin of the FPGA chip, and further judging whether the INIT _ B pin of the FPGA chip is high level after the PROGRAM file to be loaded is burnt; if so, indicating that the configuration data of the program file to be loaded is not completely written in or a synchronous head is not detected when the data is received, starting special condition compensation at the moment, detecting whether a DONE pin of the FPGA chip is at a high level or a low level, if the DONE pin is at the high level, determining that the program file to be loaded is completely loaded and selecting to reconfigure the FPGA chip, and if the DONE pin is at the low level, indicating that the program file to be loaded is overtime and selecting to reconfigure the FPGA chip; if not, indicating that the configuration data of the program file to be loaded is loaded in error and selecting to reconfigure the FPGA chip.
Therefore, whether the FPGA chip finishes loading the program file to be loaded or not can be judged better, and a user can take corresponding compensation measures in time under the condition of loading failure or loading overtime.
Optionally, as shown in fig. 7, the sending, to the Zynq chip, loading completion information generated after the loading is completed through a DONE pin, where the Zynq chip sends the loading completion information to the upper computer through a base address register of a PCIe bus protocol, including:
step 701: and the FPGA chip sends a digital signal indicating that the loading is finished to the Zynq chip.
Step 702: and the Zynq chip sends the digital signal to the upper computer based on a base address register of a PCIe bus protocol.
Step 703: and the upper computer reads the digital signal and displays whether the FPGA chip is loaded completely.
In the embodiment of the application, after the to-be-loaded program file is loaded by the FPGA chip, 1-bit digital signals are sent to the Zynq chip through a DONE pin of the FPGA chip to represent that the loading is finished, the Zynq chip reports the 1-bit digital signals to an upper computer through a base address register of a PCIe bus protocol to be displayed, an X86 address of the upper computer is 1100000000001, a read value of F represents that the to-be-loaded program file is successfully programmed, and a read value of 0 represents that the to-be-loaded program file is failed to be programmed.
Therefore, 1-bit digital signals are sequentially transferred from the FPGA chip to the upper computer through the Zynq chip, so that the upper computer can confirm whether the makeup program file is successfully loaded, and interaction of a user with a platform can be better realized.
With reference to fig. 8, an embodiment of the present disclosure provides a method for FPGA data transmission, including:
step 801: and the upper computer sends the data to be processed to the Zynq chip through the first data transmission channel.
Step 802: and the Zynq chip sends the data to be processed to the FPGA chip through a second data transmission channel so that the FPGA chip processes the data to be processed.
Step 803: and the FPGA chip sends processing process data and/or processing result data which need to be observed or displayed in the processing process to the Zynq chip through the second data transmission channel.
Step 804: and the Zynq chip receives and sends the processing process data and/or the processing result data to the upper computer through a first data transmission channel, so that the upper computer displays the processing process data and/or the processing result data.
In the embodiment of the application, the target algorithm corresponding to the program file to be loaded can be executed by the FPGA chip which finishes loading the program file to be loaded, so that the data to be processed from the upper computer is processed, specifically, the upper computer can send the data to be processed to the Zynq chip through the first data transmission channel, or receive the processing process data and/or the processing result data sent from the FPGA chip through the Zynq chip through the first data transmission channel, so that a user can observe the processing process data and/or the processing result data through the upper computer, and meanwhile, the Zynq chip can transmit the data to be processed to the FPGA chip through the second data transmission channel, or receive the processing process data and/or the processing result data from the FPGA chip through the second data transmission channel.
By adopting the method for FPGA data transmission provided by the embodiment of the disclosure, the continuity of a data transmission link is ensured while the dynamic loading of the FPGA program by the upper computer is completed, and the bidirectional data transmission between the upper computer and the loaded FPGA chip can be realized, thereby ensuring the integrity and diversity of hardware structure functions.
The disclosed embodiments provide a software radio platform comprising an apparatus for an FPGA as described herein.
The disclosed embodiments provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for dynamic loading of an FPGA program.
The disclosed embodiments provide a storage medium storing computer-executable instructions configured to perform the above-described method for dynamic loading of an FPGA program.
The storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.
The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising a program for FPGA dynamically loaded" does not exclude the presence of additional like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. An apparatus for an FPGA, comprising:
an upper computer;
the Zynq chip is configured to establish a first program loading channel based on a PCIe bus protocol with the upper computer;
the FPGA chip is configured to establish a second program loading channel based on a PCIe bus protocol with the Zynq chip;
the upper computer sends a program file to be loaded to the Zynq chip through the first program loading channel, and the Zynq chip sends the program file to be loaded to the FPGA chip through the second program loading channel, so that the FPGA chip loads the program file to be loaded.
2. The apparatus of claim 1, wherein the Zynq chip is further configured to:
and a first data transmission channel based on a PCIe bus protocol is established between the upper computer and the Zynq chip, so that data transmission is carried out between the upper computer and the Zynq chip through the first data transmission channel.
3. The apparatus of claim 1, wherein the FPGA chip is further configured to:
and a second data transmission channel based on an Aurora protocol is established between the FPGA chip and the Zynq chip, so that the FPGA chip and the Zynq chip can carry out data transmission through the second data transmission channel.
4. The apparatus of claim 3, wherein the Zynq chip comprises:
the programmable logic module is configured to be in communication connection with the upper computer through the first program loading channel and the first data transmission channel and is in communication connection with the FPGA chip through the second program loading channel and the second data transmission channel;
the processor system module is configured to configure the FPGA chip and the external equipment;
a data buffer module configured to be communicatively coupled to the programmable logic module and the processor system module, respectively.
5. The apparatus of claim 3, wherein the first program load channel and the second program load channel are one-way transmission program programming channels;
the first data transmission channel and the second data transmission channel are data transmission channels for bidirectional transmission.
6. A method for dynamically loading an FPGA program is characterized by comprising the following steps:
the upper computer sends a configuration program file to the Zynq chip through a first program loading channel so as to establish a second program loading channel based on a PCIe bus protocol between the Zynq chip and the FPGA chip, and the Zynq chip sends a digital signal indicating that the configuration is finished to the upper computer after the configuration is finished;
the upper computer sends a program loading instruction to the Zynq chip through a first program loading channel, and sends a program file to be loaded to the Zynq chip through the first program loading channel;
the Zynq chip receives the program file to be loaded according to the program loading instruction and sends the program file to be loaded to the FPGA chip through a second program loading channel;
the FPGA chip receives and loads the program file to be loaded through a second program loading channel, loading completion information generated after loading is completed is sent to the Zynq chip through a DONE pin, and the Zynq chip sends the loading completion information to the upper computer through a base address register of a PCIe bus protocol.
7. The method of claim 6, wherein the upper computer sends a program loading instruction to the Zynq chip through a first program loading channel and sends a program file to be loaded to the Zynq chip through the first program loading channel, and the method comprises the following steps:
the upper computer sends a program loading instruction to the Zynq chip through a first program loading channel;
the Zynq chip reads a program file to be loaded in a binary format through a first program loading channel based on a PCIe bus protocol;
and the Zynq chip caches and extracts the program file to be loaded in a ping-pong operation mode through two data buffer modules.
8. The method according to claim 6, wherein the receiving and loading of the program file to be loaded by the FPGA chip through a second program loading channel comprises:
the FPGA chip is powered on or reset in configuration, so that the FPGA chip starts a configuration program;
initializing the FPGA chip;
after initialization is completed, enabling the FPGA chip to acquire a program file to be loaded and configuring a clock signal for the FPGA chip;
when the high-level signal output by the FPGA chip is detected, determining that the loading of the program file to be loaded is finished;
and when the low level signal output by the FPGA chip is detected, prompting a loading error or overtime loading.
9. A method for FPGA data transmission, comprising:
the upper computer sends data to be processed to the Zynq chip through a first data transmission channel;
the Zynq chip sends the data to be processed to an FPGA chip through a second data transmission channel so that the FPGA chip processes the data to be processed;
the FPGA chip sends processing process data and/or processing result data which need to be observed or displayed in the processing process to the Zynq chip through the second data transmission channel;
and the Zynq chip receives and sends the processing process data and/or the processing result data to the upper computer through a first data transmission channel, so that the upper computer displays the processing process data and/or the processing result data.
10. A software radio platform, comprising an apparatus for FPGA according to any of claims 1 to 5.
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