CN106060462A - High-performance video processing and transmitting system based on Zynq platform - Google Patents
High-performance video processing and transmitting system based on Zynq platform Download PDFInfo
- Publication number
- CN106060462A CN106060462A CN201610413861.1A CN201610413861A CN106060462A CN 106060462 A CN106060462 A CN 106060462A CN 201610413861 A CN201610413861 A CN 201610413861A CN 106060462 A CN106060462 A CN 106060462A
- Authority
- CN
- China
- Prior art keywords
- video
- module
- data
- pcie
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
Abstract
The invention discloses a high-performance video processing and transmitting system based on a Zynq platform. The system is arranged between an external video source and an upper PC machine, and mainly comprises a video input module, used for collecting valid data in an external video source signal; a VDMA module, used for transmitting video signals in a programmable logic (PL) module to a storage at high speed; a video processing module, used for completing a complex video processing function; an AXI interconnection module, used for connecting the PL module with a processing (PS) system; the PS system, used for controlling the managing the whole system; and a PCIe module, used for packaging video frame data into a corresponding PCIe message, and transmitting the data between the system and the upper PC computer at high speed via a PCIe bus. The system of the invention integrates the capacities of collecting, processing and transmitting high-definition videos at high speed, and has the advantages of being strong in processing capacity, high in video quality and fast in transmission speed.
Description
Technical field
The present invention relates to video processing technique and communication technology, be specifically related at a kind of HD video based on Zynq platform
Reason and transmission system.
Background technology
Along with development and the progress of society of national economy, in radio and television, intelligent transportation, immersion shows, security protection is supervised
The fields such as control are more and more higher to definition, stability and the requirement of real-time of video, simultaneously the bandwidth height of high-definition video signal, number
Result also in the collection of high-definition image according to features such as handling capacity are big, process and transmission becomes a difficult problem, therefore to high performance video at
The demand of reason and transmission system is also constantly increasing.
On the one hand, video processing schemes many employings ARM in early days, DSP, FPGA single architecture realizes, due to Video processing
Require high concurrency, for most of arm processors, all do not reach the requirement of data bandwidth and processing speed.And it is right
For DSP and FPGA, although data-handling capacity compares ARM a certain degree of lifting, but is difficult to run complicated figure
Picture, video processnig algorithms.ARM+FPGA subsequently, the expansion scheme of the multi-chips such as ARM+DSP, DSP+FPGA then has system knot
Structure is complicated, develops difficult in maintenance, and power consumption is high, high in cost of production shortcoming.
Zynq is the processing platform expanded based on Xilinx full programmable A ll Programmable, and it is in single-chip
The processing system Processing System (PS) of based on high-performance ARM Cortex-A9 processor of perfect integration and
Xilinx 28nm FPGA Programmable Logic (PL), has provided the user top motility, configurability
And performance.With the arm processor that other are independent or Xilinx FPGA on veneer compared with, Zynq framework has overall performance
The advantages such as lifting, overall power reduction, design cost reduction, design flexibility enhancing.
On the other hand, conventional scheme to using Ethernet to realize, at the transmitting terminal of data the transmission of HD video more
It is compressed respectively and decompression processing with receiving terminal, has been short of in terms of system real time.And PCIe technology is third generation height
The I/O bus of performance, it is provided that two-forty, stable, reliable transmission link, is particularly well-suited to the real-time biography of high-definition video signal
Defeated.
Summary of the invention
It is an object of the invention to provide a kind of high performance Video processing and transmission system so that this system is provided simultaneously with
Powerful video processing capabilities, data transmission capabilities at a high speed and the advantage such as real-time.
In order to realize above-mentioned technical purpose, the technical scheme is that, a kind of high performance video based on Zynq platform
Processing and transmission system, be arranged between external video source and upper PC, described high performance video processing system includes:
PS processing system: be used for controlling and manage whole high performance video processing system；
Memory module, keeping in for video image；
PL programmed logical module；
Described PS processing system is connected with PL programmed logical module and memory communication respectively；
PL programmed logical module includes:
Video input module, for gathering the effective on-screen data in external video source signal；
VDMA module, completes the high-speed video data between PL programmed logical module and memorizer by PS processing system and hands over
Mutually；
AXI interconnection module, for PL programmed logical module and the interconnection of PS processing system；
Video processing module, completes video processing function；
PCIe module, for video requency frame data being encapsulated as corresponding PCIe message or being decoded by PCIe message, and leads to
Cross PCIe bus high-speed transferring data between system and upper PC；
Performance monitoring module, for monitoring the data transmission throughput of VDMA module, memorizer and PCIe module.
Described high performance video processes and transmission system, and described system possesses two kinds of different mode of operations: process real
Time gather the line model of video signal and process from the off-line mode of upper PC historical data, wherein:
Described line model, video input module gathers effective on-screen data from external video source, detects video data
Row field signal and judge resolution, and by VDMA module, the video collected is sent in memorizer at a high speed at video
Reason module processes, and the data that finally will be disposed are encapsulated by PCIe module again, and upload to upper PC and show
And storage；
Described off-line mode, PCIe module directly receives the original video data that upper PC sends over, after decoding
Sending it in memorizer by VDMA module, video processing module obtains initial data from memorizer to be carried out at a high speed
Reason, the data that finally will be disposed are encapsulated and return to upper PC by PCIe module and show and store.
Described high performance video processes and transmission system, and described video input module includes:
Video input interface module, for receiving the real time video data of external image sensor acquisition；
Time-series rules submodule, for receiving the real time data of video input interface module collection and detecting real-time video number
According to row field signal, judge the resolution of video image according to these signals, and extract effective on-screen data；
Form transform subblock, is converted to easily carry out image procossing by the effective on-screen data extracted by yuv format
RGB data form.
Described high performance video processes and transmission system, and described VDMA module includes:
Write access S2MM, for being written to video signal in system storage；
Read channel MM2S, for reading video signal from system storage；
Data carrier subelement, performs concrete DMA video data under the control controlling logical subunit and migrates behaviour
Make；
Controlling logical subunit, the configuration signal that reception PS processing system sends is to control the work of whole VDMA module.
Described high performance video processes and transmission system, and described video processing module includes:
DPC subelement, for detecting and revise the defect pixel of input video；
CFA subelement, by remaining two kinds of color component of pixel each in demosaicing frame of video, optimizes image thin
The acutance of joint；
CCM subelement, carries out color correction operation to RGB image, including regulation white balance, colour cast, brightness, contrast；
Gamma subelement, carries out Gamma correction to frame of video, reduces video distortion degree；
RGB2YUV subelement, is converted into YUV color gamut space signal by RGB color domain space signal；
Enhance submodule, performs video image edge and strengthens and noise reduction process, finally export.
Described high performance video processes and transmission system, and described PCIe module includes:
Integrated PCIe submodule, for video signal, control signal are encapsulated as PCIe message format, receives upper PC
Machine send transaction layer packet and decode；
PCIe DMA submodule, provides for high-speed transferring data between system and upper PC and controls logic and data transmission
Passage, including:
Receiver module, receives the original video data that upper PC sends over, and is parsed and is sent to FIFO mould afterwards
In block；Sending module, receives the processed complete data that fifo module sends over, and sends it to upper PC；DMA is controlled
System, block of state, receive the read-write control signal of PS processing system, controls the specific works of delivery and reception module.
Described high performance video processes and transmission system, and described PS processing system passes through AXI interconnection module to whole system
Remaining module of system is controlled and manages operation.
Described high performance video processes and transmission system, described performance monitoring unit, is respectively used to monitor three high property
HP0, HP1, HP2 port of energy and the data transmission throughput of PCIe module, calculate effective data especially by enumerator and pass
Defeated number of times calculates data volume per second, and is loaded in depositor by this numerical value for the reading of upper PC.
The method have technical effect that, beneficial effects of the present invention:
1. system structure is simple, i.e. can reach the treatment effect of conventional multi-chip expansion scheme based on single Zynq framework,
I.e. reduce holistic cost and power consumption, reduce system development and maintenance difficulties simultaneously；
2. system possesses online and two kinds of mode of operations of off-line, can tackle different working environments；
3. using modularized design, make full use of the motility of PL FPGA, the extension of system is the simplest；
4. using PCIe bus protocol to transmit high-definition video signal with dma mode, efficiency of transmission is high, the bit error rate is low, real-time
Property is good.
Below in conjunction with embodiment and Figure of description, the present invention will be further described.
Accompanying drawing explanation
Fig. 1 is the overall structure schematic diagram of native system；
Fig. 2 is the concrete module diagram of native system；
Fig. 3 is the video processing module schematic diagram in native system.
Fig. 4 is the VDMA module diagram in native system；
Fig. 5 is the PCIe DMA submodule schematic diagram in native system.
Detailed description of the invention
The present embodiment is arranged between external video source and upper PC, specifically includes: PS processing system: for control and
Manage whole high performance video processing system；Memory module, keeping in for video image；PL programmed logical module；Institute
The PS processing system stated is connected with PL programmed logical module and memory communication respectively；PL programmed logical module includes: regard
Frequently input module, for gathering the effective on-screen data in external video source signal；VDMA module, is completed by PS processing system
High-speed video data between PL programmed logical module and memorizer is mutual；AXI interconnection module, for PL programmed logical module
Interconnection with PS processing system；Video processing module, completes video processing function；PCIe module, for sealing video requency frame data
Dress decodes for corresponding PCIe message or by PCIe message, and is passed at a high speed between system and upper PC by PCIe bus
Send data；Performance monitoring module, for monitoring the data transmission throughput of VDMA module, memorizer and PCIe module.
Native system video-processing steps is as follows:
Step 1, obtains high definition original video data from external video source or upper PC, and by VDMA module transmission
In system storage；Step 2, video processing module reads high definition from memorizer by the VDMA module being attached thereto and regards
Frequently, and carry out series of complex Computer Vision operation；Step 3, processed complete data pass through PCIe module with DMA
Mode high-speed transfer carries out showing and storing to upper PC.
The present embodiment is to tackle different working environments to have possessed line model and the place processing Real-time Collection video signal
Managing the off-line mode from upper PC historical data, concrete data flow is as follows:
Under line model, video input interface module enter time-series rules submodule after gathering outside real-time video source
Carry out detecting, judge and extracting effective on-screen data, by form transform subblock, original video data is converted into more subsequently
After adding the data form easily carrying out Computer Vision, VDMA module it is responsible for the data collected to transmit,
In rear arrival system storage.After video processing module reads the initial data of collection from system storage, carrying out one is
The Computer Vision operation of row, and be sent in memorizer, finally by PCIe mould by the VDMA module data that will be disposed
Block encapsulate accordingly after High Speed Transfer to upper PC.
Under off-line mode, PCIe module receives the original video data bag that upper PC sends over, after resolving,
Send it in fifo module, be finally sent in system storage by VDMA module.Video processing module is from memorizer
Read after carrying out respective handling after initial data, finally by PCIe module, reduced data passed back to upper PC.
Wherein video input module includes: video input interface module, for receiving the reality of external image sensor acquisition
Time video data；Time-series rules submodule, regards in real time for the real time data detection receiving video input interface module collection
The row field signal of frequency evidence, judges the resolution of video image, and extracts effective on-screen data according to these signals；Form turns
Change submodule, the effective on-screen data extracted is converted to easily carry out the RGB data form of image procossing by yuv format.
Wherein VDMA module includes: write access S2MM, for being written in system storage by video signal；Read channel
MM2S, for reading video signal from system storage；Data carrier subelement, in the control controlling logical subunit
The DMA video data migration operation that lower execution is concrete；Controlling logical subunit, the configuration signal that reception PS processing system sends is come
Control the work of whole VDMA module.
Wherein video processing module includes: DPC subelement, for detecting and revise the defect pixel of input video；CFA
Unit, by remaining two kinds of color component of pixel each in demosaicing frame of video, optimizes the acutance of image detail；
CCM subelement, carries out color correction operation to RGB image, including regulation white balance, colour cast, brightness, contrast；Gamma list
Unit, carries out Gamma correction to frame of video, reduces video distortion degree；RGB2YUV subelement, converts RGB color domain space signal
For YUV color gamut space signal；Enhance submodule, performs video image edge and strengthens and noise reduction process, finally export.
Wherein PCIe module includes: integrated PCIe submodule, for video signal, control signal are encapsulated as PCIe report
Literary composition form, receives the transaction layer packet of upper PC transmission and decodes；PCIe DMA submodule, for system and upper PC it
Between high-speed transferring data provide and control logic and data transmission channel, including receiver module, receive what upper PC sended over
Original video data, is parsed and is sent to afterwards in fifo module；Sending module, receives the place that fifo module sends over
Manage complete data, and send it to upper PC；DMA controls, block of state, receives the Read-write Catrol letter of PS processing system
Number, control the specific works of delivery and reception module.
Wherein remaining module of whole system is controlled and manages operation by AXI interconnection module by PS processing system.
In order to ensure to monitor system in real time, the present embodiment is also provided with performance monitoring unit, is respectively used to monitoring
The data transmission throughput of three high performance HP0, HP1, HP2 ports and PCIe module, calculates effectively especially by enumerator
Data transmission times calculate data volume per second, and this numerical value be loaded in depositor read for upper PC.
Claims (8)
1. high performance video based on Zynq platform processes and a transmission system, be arranged at external video source and upper PC it
Between, it is characterised in that described high performance video processing system includes:
PS processing system: be used for controlling and manage whole high performance video processing system；
Memory module, keeping in for video image；
PL programmed logical module；
Described PS processing system is connected with PL programmed logical module and memory communication respectively；
PL programmed logical module includes:
Video input module, for gathering the effective on-screen data in external video source signal；
VDMA module, the high-speed video data completed between PL programmed logical module and memorizer by PS processing system is mutual；
AXI interconnection module, for PL programmed logical module and the interconnection of PS processing system；
Video processing module, completes video processing function；
PCIe module, for video requency frame data being encapsulated as corresponding PCIe message or being decoded by PCIe message, and passes through
PCIe bus is high-speed transferring data between system and upper PC；
Performance monitoring module, for monitoring the data transmission throughput of VDMA module, memorizer and PCIe module.
2. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described system possesses two kinds not
Same mode of operation: process the line model of Real-time Collection video signal and process the off-line mould from upper PC historical data
Formula, wherein:
Described line model, video input module gathers effective on-screen data, the row of detection video data from external video source
Field signal also judges resolution, and is sent in memorizer at a high speed the video collected for Video processing mould by VDMA module
Block processes, and the data that finally will be disposed are encapsulated by PCIe module again, and uploads to upper PC and show and deposit
Storage；
Described off-line mode, PCIe module directly receives the original video data that upper PC sends over, passes through after decoding
VDMA module sends it in memorizer, and video processing module obtains initial data from memorizer and carries out high speed processing,
After the data that will be disposed encapsulated and return to upper PC by PCIe module and show and store.
3. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described video input module bag
Include:
Video input interface module, for receiving the real time video data of external image sensor acquisition；
Time-series rules submodule, for receiving the real time data of video input interface module collection and detecting real time video data
Row field signal, judges the resolution of video image, and extracts effective on-screen data according to these signals；
Form transform subblock, is converted to easily carry out the RGB of image procossing by the effective on-screen data extracted by yuv format
Data form.
4. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described VDMA module includes:
Write access S2MM, for being written to video signal in system storage；
Read channel MM2S, for reading video signal from system storage；
Data carrier subelement, performs concrete DMA video data migration operation under the control controlling logical subunit；
Controlling logical subunit, the configuration signal that reception PS processing system sends is to control the work of whole VDMA module.
5. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described video processing module bag
Include:
DPC subelement, for detecting and revise the defect pixel of input video；
CFA subelement, by remaining two kinds of color component of pixel each in demosaicing frame of video, optimizes image detail
Acutance；
CCM subelement, carries out color correction operation to RGB image, including regulation white balance, colour cast, brightness, contrast；
Gamma subelement, carries out Gamma correction to frame of video, reduces video distortion degree；
RGB2YUV subelement, is converted into YUV color gamut space signal by RGB color domain space signal；
Enhance submodule, performs video image edge and strengthens and noise reduction process, finally export.
6. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described PCIe module includes:
Integrated PCIe submodule, for video signal, control signal are encapsulated as PCIe message format, receive upper PC and sends out
The transaction layer packet that send also decodes；
PCIe DMA submodule, provides control logic and data transmission logical for high-speed transferring data between system and upper PC
Road, including:
Receiver module, receives the original video data that upper PC sends over, and is parsed and is sent to afterwards in fifo module；
Sending module, receives the processed complete data that fifo module sends over, and sends it to upper PC；DMA controls, shape
Morphotype block, receives the read-write control signal of PS processing system, controls the specific works of delivery and reception module.
7. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described PS processing system is passed through
Remaining module of whole system is controlled and manages operation by AXI interconnection module.
8. high performance video as claimed in claim 1 processes and transmission system, it is characterised in that described performance monitoring unit,
It is respectively used to monitor the data transmission throughput of three high performance HP0, HP1, HP2 ports and PCIe module, especially by meter
Number device calculates effective data transmission times and calculates data volume per second, and is loaded in depositor by this numerical value for upper PC
Read.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610399581X | 2016-06-07 | ||
| CN201610399581 | 2016-06-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106060462A true CN106060462A (en) | 2016-10-26 |
| CN106060462B CN106060462B (en) | 2019-09-17 |
Family
ID=57169980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610413861.1A Active CN106060462B (en) | 2016-06-07 | 2016-06-13 | A kind of high performance video processing and Transmission system based on Zynq platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106060462B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN108107827A (en) * | 2017-12-13 | 2018-06-01 | 天津津航计算技术研究所 | A kind of SRIO control methods based on the soft core of ZYNQ platforms |
| WO2018209889A1 (en) * | 2017-05-16 | 2018-11-22 | 杭州海康威视数字技术股份有限公司 | Extended storage device based on pcie bus |
| CN109167966A (en) * | 2018-09-29 | 2019-01-08 | 南京邮电大学南通研究院有限公司 | Image dynamic detection system and method based on FPGA+ARM |
| CN110049294A (en) * | 2019-05-29 | 2019-07-23 | 郑晓宇 | Based on the aloof from politics and material pursuits image frame grabber of Zynq high and processing system |
| CN110519497A (en) * | 2019-08-28 | 2019-11-29 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | A kind of zero-copy triggering collection device and method based on VDMA |
| CN111917974A (en) * | 2020-06-24 | 2020-11-10 | 济南浪潮高新科技投资发展有限公司 | FPGA-based video processing system, method, device and medium |
| CN113038138A (en) * | 2021-04-09 | 2021-06-25 | 成都理工大学 | Embedded image processing and returning system |
| CN113596356A (en) * | 2021-06-21 | 2021-11-02 | 中国科学院新疆生态与地理研究所 | Grassland mouse damage field monitoring method |
| CN114615537A (en) * | 2020-11-24 | 2022-06-10 | 深圳市奥拓电子股份有限公司 | Zero-frame-delay video control system and method and LED display system |
| CN114760414A (en) * | 2022-04-12 | 2022-07-15 | 上海航天电子通讯设备研究所 | Image acquisition and processing system for CMV4000 camera |
| CN114999192A (en) * | 2022-04-11 | 2022-09-02 | 华东师范大学 | Traffic signal lamp intelligent recognition device based on Zynq7020 |
| CN114760414B (en) * | 2022-04-12 | 2024-04-16 | 上海航天电子通讯设备研究所 | Image acquisition and processing system for CMV4000 camera |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636301A (en) * | 2015-02-15 | 2015-05-20 | 中南大学 | Large-scale PLC (programmable logic controller) high-speed backplane bus system on basis of PCI-E (peripheral component interconnect-express) interface |
| WO2015112103A1 (en) * | 2014-01-22 | 2015-07-30 | Durukan Coşkun | Training and experiment system supported by an animation based full simulation method |
| CN105260339A (en) * | 2015-08-17 | 2016-01-20 | 中南大学 | Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology |
-
2016
- 2016-06-13 CN CN201610413861.1A patent/CN106060462B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015112103A1 (en) * | 2014-01-22 | 2015-07-30 | Durukan Coşkun | Training and experiment system supported by an animation based full simulation method |
| CN104636301A (en) * | 2015-02-15 | 2015-05-20 | 中南大学 | Large-scale PLC (programmable logic controller) high-speed backplane bus system on basis of PCI-E (peripheral component interconnect-express) interface |
| CN105260339A (en) * | 2015-08-17 | 2016-01-20 | 中南大学 | Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology |
Non-Patent Citations (3)
| Title |
|---|
| HANAA M. ABDELGAWAD等: "High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform", 《NTERNATIONAL JOURNAL OF COMPUTER, ELECTRICAL, AUTOMATION, CONTROL AND INFORMATION ENGINEERING》 * |
| PANKAI KUMBHARE等: "Designing High-performance Video Systems in 7 Series FPGAs with the AXI interconnect", 《WWW.XILINX.COM》 * |
| XILINX: "Zynq-7000 All Programmable SoC ZC706 Evaluation Kit(ISE Design Suite 14.4) Getting Started Guide", 《WWW.XILINX.COM》 * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| WO2018209889A1 (en) * | 2017-05-16 | 2018-11-22 | 杭州海康威视数字技术股份有限公司 | Extended storage device based on pcie bus |
| US11100037B2 (en) | 2017-05-16 | 2021-08-24 | Hangzhou Hikvision Digital Technology Co., Ltd. | Extended storage device based on PCIe bus |
| CN108107827A (en) * | 2017-12-13 | 2018-06-01 | 天津津航计算技术研究所 | A kind of SRIO control methods based on the soft core of ZYNQ platforms |
| CN109167966A (en) * | 2018-09-29 | 2019-01-08 | 南京邮电大学南通研究院有限公司 | Image dynamic detection system and method based on FPGA+ARM |
| CN110049294A (en) * | 2019-05-29 | 2019-07-23 | 郑晓宇 | Based on the aloof from politics and material pursuits image frame grabber of Zynq high and processing system |
| CN110519497A (en) * | 2019-08-28 | 2019-11-29 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | A kind of zero-copy triggering collection device and method based on VDMA |
| CN110519497B (en) * | 2019-08-28 | 2020-11-17 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | Zero-copy trigger acquisition device and method based on VDMA |
| CN111917974B (en) * | 2020-06-24 | 2022-04-15 | 山东浪潮科学研究院有限公司 | FPGA-based video processing system, method, device and medium |
| CN111917974A (en) * | 2020-06-24 | 2020-11-10 | 济南浪潮高新科技投资发展有限公司 | FPGA-based video processing system, method, device and medium |
| CN114615537A (en) * | 2020-11-24 | 2022-06-10 | 深圳市奥拓电子股份有限公司 | Zero-frame-delay video control system and method and LED display system |
| CN114615537B (en) * | 2020-11-24 | 2024-03-29 | 深圳市奥拓电子股份有限公司 | Zero-frame-delay video control system and method and LED display system |
| CN113038138A (en) * | 2021-04-09 | 2021-06-25 | 成都理工大学 | Embedded image processing and returning system |
| CN113596356A (en) * | 2021-06-21 | 2021-11-02 | 中国科学院新疆生态与地理研究所 | Grassland mouse damage field monitoring method |
| CN114999192A (en) * | 2022-04-11 | 2022-09-02 | 华东师范大学 | Traffic signal lamp intelligent recognition device based on Zynq7020 |
| CN114760414A (en) * | 2022-04-12 | 2022-07-15 | 上海航天电子通讯设备研究所 | Image acquisition and processing system for CMV4000 camera |
| CN114760414B (en) * | 2022-04-12 | 2024-04-16 | 上海航天电子通讯设备研究所 | Image acquisition and processing system for CMV4000 camera |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106060462B (en) | 2019-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106060462A (en) | High-performance video processing and transmitting system based on Zynq platform | |
| CN104427218B (en) | Ultra high-definition ccd image multichannel collecting and RTTS and method | |
| CN101309430A (en) | Video image preprocessor on basis of FPGA | |
| CN107249101A (en) | A kind of sample of high-resolution image and processing unit | |
| CN105993177A (en) | Image capture accelerator | |
| CN103379266A (en) | High-definition web camera with video semantic analysis function | |
| CN105208342B (en) | A kind of two-way video compression storage and network switching transmission circuit | |
| CN201249721Y (en) | Vehicle lane departure prewarning device | |
| CN103188479A (en) | Video monitoring system and video monitoring method based on optical fiber interface | |
| CN105677283A (en) | Video signal transmitting method and device for multi-screen splicing display | |
| CN112995465B (en) | Image transmission system and method based on ZYNQ | |
| CN107220208A (en) | A kind of image processing system and method | |
| CN207560231U (en) | A kind of LED display network controller | |
| CN102118289B (en) | Real-time image segmentation processing system and high-speed intelligent unified bus interface method based on Institute of Electrical and Electronic Engineers (IEEE) 1394 interface | |
| CN108134782A (en) | A kind of method based on 10,000,000,000 network transmission high-bandwidth video of FCoE protocol realizations | |
| CN205754597U (en) | A kind of multi-channel video splicing apparatus based on FPGA | |
| CN109429043B (en) | System and method for acquiring traffic sign video images based on FPGA | |
| CN102387348B (en) | Dual-code stream high-definition camera applied to intelligent transportation | |
| CN104883518A (en) | Low-cost small-sized thermal infrared imager | |
| CN105430297B (en) | The automatic control system that more video formats are changed to IIDC protocol videos form | |
| CN201238361Y (en) | Video collection apparatus | |
| CN103414898B (en) | A kind of high-resolution video acquisition method and system | |
| CN202334758U (en) | Wireless image collecting system based on FPGA (Field Programmable Gate Array) | |
| CN205385561U (en) | Tiled display systems of shielding more | |
| CN207039793U (en) | A kind of NI Vision Builder for Automated Inspection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |