CN106060462B - A kind of high performance video processing and Transmission system based on Zynq platform - Google Patents

A kind of high performance video processing and Transmission system based on Zynq platform Download PDF

Info

Publication number
CN106060462B
CN106060462B CN201610413861.1A CN201610413861A CN106060462B CN 106060462 B CN106060462 B CN 106060462B CN 201610413861 A CN201610413861 A CN 201610413861A CN 106060462 B CN106060462 B CN 106060462B
Authority
CN
China
Prior art keywords
video
module
data
processing
pcie
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610413861.1A
Other languages
Chinese (zh)
Other versions
CN106060462A (en
Inventor
徐德刚
刘育峰
蔡海明
谢攀攀
阳春华
谢永芳
桂卫华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Central South University
Original Assignee
Central South University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Central South University filed Critical Central South University
Publication of CN106060462A publication Critical patent/CN106060462A/en
Application granted granted Critical
Publication of CN106060462B publication Critical patent/CN106060462B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/18Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/76Television signal recording

Abstract

The high performance video processing and Transmission system, system that the invention discloses a kind of based on Zynq platform are set between external video source and upper PC machine, video input module are specifically included that, for acquiring the valid data in external video source signal;VDMA module, by the vision signal high-speed transfer in PL programmed logical module into memory;Video processing module completes complicated video processing function;AXI interconnection module connects PL programmable logic and PS processing system;PS processing system modules, control and management whole system;PCIe module for video requency frame data to be encapsulated as corresponding PCIe message, and passes through PCIe bus high-speed transferring data between system and upper PC machine.The present invention integrates high speed acquisition, processing and transmission HD video ability, system and has the advantages that processing capacity is strong, video quality is high, transmission speed is fast.

Description

A kind of high performance video processing and Transmission system based on Zynq platform
Technical field
The present invention relates to video processing techniques and the communication technology, and in particular at a kind of HD video based on Zynq platform Reason and Transmission system.
Background technique
With the development and social progress of national economy, radio and television, intelligent transportation, immersion are shown, security protection is supervised The fields such as control are higher and higher to the clarity, stability and requirement of real-time of video, while the bandwidth of high-definition video signal is high, number The acquisition of high-definition image, processing and transmission are also resulted in the features such as big according to handling capacity becomes problem, thus to high performance video at The demand of reason and Transmission system is also constantly increasing.
On the one hand, the video processing schemes of early stage mostly use ARM, DSP, and FPGA single architecture is realized, due to video processing It is required that the requirement of data bandwidth and processing speed is all not achieved for most of arm processors in high concurrency.And it is right For DSP and FPGA, although data-handling capacity has a degree of promotion compared to ARM, it is difficult to run complicated figure Picture, video processnig algorithms.The expansion scheme of subsequent ARM+FPGA, ARM+DSP, the multi-chips such as DSP+FPGA then have system knot The disadvantages of structure is complicated, and exploitation is difficult in maintenance, and power consumption is high, at high cost.
Zynq is to expand processing platform based on the full programmable A ll Programmable of Xilinx, in single-chip Processing system Processing System (PS) of the perfect integration based on high-performance ARM Cortex-A9 processor and Xilinx 28nm programmable logic Programmable Logic (PL), top flexibility, configurability are provided for user And performance.Compared with other independent arm processors or Xilinx FPGA are on veneer, Zynq framework has overall performance The advantages that promotion, overall power reduce, design cost reduces, design flexibility enhancing.
On the other hand, previous scheme mostly uses Ethernet to the transmission of HD video to realize, in the transmitting terminal of data It carries out compression and decompression processing respectively with receiving end, is lacking in terms of system real time.And PCIe technology is third generation height The I/O bus of performance provides high-speed, stabilization, reliable transmission link, the real-time biography especially suitable for high-definition video signal It is defeated.
Summary of the invention
The purpose of the present invention is to provide a kind of high performance video processing and Transmission systems, so that the system is provided simultaneously with The advantages that powerful video processing capabilities, the data transmission capabilities and strong real-time of high speed.
In order to achieve the above technical purposes, the technical scheme is that, a kind of high performance video based on Zynq platform Processing and Transmission system, are set between external video source and upper PC machine, the high performance video processing system includes:
PS processing system: for controlling and managing entire high performance video processing system;
Memory module, for the temporary of video image;
PL programmed logical module;
The PS processing system is communicated to connect with PL programmed logical module and memory respectively;
PL programmed logical module includes:
Video input module, for acquiring effective screen data in external video source signal;
VDMA module is completed the high-speed video data between PL programmed logical module and memory by PS processing system and is handed over Mutually;
AXI interconnection module, the interconnection for PL programmed logical module and PS processing system;
Video processing module completes video processing function;
PCIe module for video requency frame data to be encapsulated as corresponding PCIe message or decodes PCIe message, and is led to Cross PCIe bus high-speed transferring data between system and upper PC machine;
Performance monitoring module, the data for monitoring VDMA module, memory and PCIe module transmit throughput.
The high performance video processing and Transmission system, the system have two different operating modes: processing is real When acquisition vision signal on-line mode and processing the off-line mode from upper PC machine historical data, in which:
The on-line mode, video input module acquire effective screen data from external video source, detect video data Row field signal and judge resolution ratio, and sent collected video high speed in memory at for video by VDMA module Reason module is handled, and the data that will finally be disposed pass through PCIe module again and encapsulate, and upload to upper PC machine and shown And storage;
The off-line mode, PCIe module directly receives the original video data that upper PC machine sends over, after decoding It is sent it in memory by VDMA module, video processing module carries out from high speed from acquisition initial data in memory Reason, the data that will finally be disposed are encapsulated by PCIe module and return to upper PC machine and shown and store.
The high performance video processing and Transmission system, the video input module include:
Video input interface module, for receiving the real time video data of external image sensor acquisition;
Time-series rules submodule, for receiving the real time data of video input interface module acquisition and detecting real-time video number According to row field signal, the resolution ratio of video image is judged according to these signals, and extract effective screen data;
The effective screen data of extraction is converted to by yuv format and is easy to carry out image procossing by format transform subblock RGB data format.
The high performance video processing and Transmission system, the VDMA module include:
Write access S2MM, for video signal to be written in system storage;
Read channel MM2S, for reading video signal from system storage;
Data carrier subelement executes specific DMA video data migration behaviour under the control of control logic subelement Make;
Control logic subelement receives the configuration signal that PS processing system issues to control the work of entire VDMA module.
The high performance video processing and Transmission system, the video processing module include:
DPC subelement, for detecting and correcting the defect pixel of input video;
It is thin to optimize image by remaining two kinds of color component of each pixel in demosaicing video frame for CFA subelement The acutance of section;
CCM subelement carries out color correction operation to RGB image, including adjusts white balance, colour cast, brightness, contrast;
Gamma subelement carries out Gamma correction to video frame, reduces video distortion degree;
RGB color domain space signal is converted YUV color gamut space signal by RGB2YUV subelement;
Enhance submodule executes the enhancing of video image edge and noise reduction process, is finally exported.
The high performance video processing and Transmission system, the PCIe module include:
Integrated PCIe submodule receives upper PC for being PCIe message format by video signal, control signal assemble The transaction layer data packet of machine transmission simultaneously decodes;
PCIe DMA submodule, high-speed transferring data provides control logic and data transmission between system and upper PC machine Channel, comprising:
Receiving module receives the original video data that upper PC machine sends over, and FIFO mould is sent to after being parsed In block;Sending module, receive that fifo module sends over it is processed finish data, and send it to upper PC machine;DMA control System, block of state receive the read-write control signal of PS processing system, control the specific works of delivery and reception module.
The high performance video processing and Transmission system, the PS processing system is by AXI interconnection module to entire system Remaining module of system is controlled and is managed operation.
The high performance video processing and Transmission system, the performance monitoring unit are respectively used to the three high property of monitoring The port HP0, HP1, HP2 of energy and the data of PCIe module transmit throughput, calculate effective data especially by counter and pass The numerical value is loaded into register for the reading of upper PC machine by defeated number to calculate data volume per second.
The technical effects of the invention are that beneficial effects of the present invention:
It is the treatment effect that can reach previous multi-chip expansion scheme based on single Zynq framework 1. system structure is simple, Overall cost and power consumption are reduced, while reducing system development and maintenance difficulties;
2. system has online and offline two kinds of operating modes, different working environments can be coped with;
3. using modularized design, the flexibility of PL programmable logic is made full use of, the extension of system is very simple;
4. PCIe bus protocol is used to transmit high-definition video signal with dma mode, efficiency of transmission is high, the bit error rate is low, real-time Property is good.
Below with reference to embodiment and Figure of description, the present invention will be further described.
Detailed description of the invention
Fig. 1 is the overall structure diagram of this system;
Fig. 2 is the specific module diagram of this system;
Fig. 3 is the video processing module schematic diagram in this system.
Fig. 4 is the VDMA module diagram in this system;
Fig. 5 is the PCIe DMA submodule schematic diagram in this system.
Specific embodiment
The present embodiment is set between external video source and upper PC machine, is specifically included: PS processing system: for control and Manage entire high performance video processing system;Memory module, for the temporary of video image;PL programmed logical module;Institute The PS processing system stated is communicated to connect with PL programmed logical module and memory respectively;PL programmed logical module includes: view Frequency input module, for acquiring effective screen data in external video source signal;VDMA module is completed by PS processing system High-speed video data interaction between PL programmed logical module and memory;AXI interconnection module is used for PL programmed logical module With the interconnection of PS processing system;Video processing module completes video processing function;PCIe module, for sealing video requency frame data Dress is corresponding PCIe message or decodes PCIe message, and is passed at a high speed between system and upper PC machine by PCIe bus Send data;Performance monitoring module, the data for monitoring VDMA module, memory and PCIe module transmit throughput.
This system video-processing steps are as follows:
Step 1, high definition original video data is obtained from external video source or upper PC machine, and is transmitted by VDMA module Into system storage;Step 2, video processing module reads high definition view by the VDMA module being attached thereto from memory Frequently, and carry out a series of complex video image processing operation;Step 3, the processed data finished are by PCIe module with DMA Mode high-speed transfer is shown and is stored to upper PC machine.
The present embodiment is that the different working environment of reply has the processing on-line mode of acquisition vision signal and place in real time The off-line mode from upper PC machine historical data is managed, specific data flow is as follows:
Under on-line mode, enter time-series rules submodule after acquiring external real-time video source by video input interface module Effective screen data is detected, judged and extracted, is then converted into original video data more by format transform subblock After adding the data format for being easy to carry out video image processing, collected data is responsible for be transmitted by VDMA module, most It reaches in system storage afterwards.Video processing module carries out a system after the initial data for reading acquisition in system storage The video image processings of column operates, and is sent in memory by the VDMA module data that will be disposed, finally by PCIe mould Block carries out after encapsulating accordingly High Speed Transfer to upper PC machine.
Under off-line mode, PCIe module receives the original video data packet that upper PC machine sends over, after being parsed, It sends it in fifo module, is finally transmitted in system storage by VDMA module.Video processing module is from memory After carrying out respective handling after reading initial data, reduced data is finally passed back into upper PC machine by PCIe module.
Wherein video input module includes: video input interface module, for receiving the reality of external image sensor acquisition When video data;Time-series rules submodule, for receiving the real time data of video input interface module acquisition and detecting view in real time The row field signal of frequency evidence, the resolution ratio of video image is judged according to these signals, and extracts effective screen data;Format turns Submodule is changed, the effective screen data of extraction is converted into the RGB data format for being easy to carry out image procossing by yuv format.
Wherein VDMA module includes: write access S2MM, for video signal to be written in system storage;Read channel MM2S, for reading video signal from system storage;Data carrier subelement, in the control of control logic subelement It is lower to execute specific DMA video data migration operation;Control logic subelement receives the configuration signal that PS processing system issues Control the work of entire VDMA module.
Wherein video processing module includes: DPC subelement, for detecting and correcting the defect pixel of input video;CFA Unit optimizes the acutance of image detail by remaining two kinds of color component of each pixel in demosaicing video frame; CCM subelement carries out color correction operation to RGB image, including adjusts white balance, colour cast, brightness, contrast;Gamma is single Member carries out Gamma correction to video frame, reduces video distortion degree;RGB2YUV subelement converts RGB color domain space signal For YUV color gamut space signal;Enhance submodule executes the enhancing of video image edge and noise reduction process, is finally exported.
Wherein PCIe module includes: integrated PCIe submodule, for being PCIe report by video signal, control signal assemble Literary format receives the transaction layer data packet that upper PC machine is sent and decodes;PCIe DMA submodule, be system and upper PC machine it Between high-speed transferring data control logic and data transmission channel are provided, comprising: receiving module receives what upper PC machine sended over Original video data is sent in fifo module after being parsed;Sending module receives the place that fifo module sends over Reason finishes data, and sends it to upper PC machine;DMA control, block of state receive the Read-write Catrol letter of PS processing system Number, control the specific works of delivery and reception module.
Wherein PS processing system is controlled and is managed operation by remaining module of AXI interconnection module to whole system.
In order to guarantee to monitor in real time to system, the present embodiment is also provided with performance monitoring unit, is respectively used to monitor The data of three high performance ports HP0, HP1, HP2 and PCIe module transmit throughput, calculate especially by counter effective Data transmission times calculate data volume per second, and the numerical value be loaded into register read for upper PC machine.

Claims (7)

1. a kind of high performance video processing and Transmission system based on Zynq platform, be set to external video source and upper PC machine it Between, which is characterized in that the high performance video processing system includes:
PS processing system: for controlling and managing entire high performance video processing system;
Memory, for the temporary of video image;
PL programmed logical module;
The PS processing system is communicated to connect with PL programmed logical module and memory respectively;
PL programmed logical module includes:
Video input module, for acquiring effective screen data in external video source signal;
VDMA module completes the high-speed video data interaction between PL programmed logical module and memory by PS processing system;
AXI interconnection module, the interconnection for PL programmed logical module and PS processing system;
Video processing module completes video processing function;
PCIe module for video requency frame data to be encapsulated as corresponding PCIe message or decodes PCIe message, and passes through PCIe bus high-speed transferring data between system and upper PC machine;
Performance monitoring module, the data for monitoring VDMA module, memory and PCIe module transmit throughput;
The system has two different operating modes: the processing on-line mode of acquisition vision signal and processing in real time is from upper The off-line mode of position PC machine historical data, in which:
The on-line mode, video input module acquire effective screen data from external video source, detect the row of video data Field signal simultaneously judges resolution ratio, and is sent collected video high speed in memory by VDMA module and handle mould for video Block is handled, and the data that will finally be disposed pass through PCIe module again and encapsulate, and upload to upper PC machine and shown and deposited Storage;
The off-line mode, PCIe module directly receive the original video data that upper PC machine sends over, pass through after decoding VDMA module is sent it in memory, and video processing module obtains initial data from memory and carries out high speed processing, most After the data that will be disposed encapsulated by PCIe module and return to upper PC machine and show and store.
2. high performance video processing as described in claim 1 and Transmission system, which is characterized in that the video input module packet It includes:
Video input interface module, for receiving the real time video data of external image sensor acquisition;
Time-series rules submodule, for receiving the real time video data of video input interface module acquisition and detecting real-time video number According to row field signal, the resolution ratio of video image is judged according to these signals, and extract effective screen data;
The effective screen data of extraction is converted to the RGB for being easy to carry out image procossing by yuv format by format transform subblock Data format.
3. high performance video as described in claim 1 processing and Transmission system, which is characterized in that the VDMA module includes:
Write access S2MM, for video signal to be written in memory;
Read channel MM2S, for reading video signal from memory;
Data carrier subelement executes specific DMA video data migration operation under the control of control logic subelement;
Control logic subelement receives the configuration signal that PS processing system issues to control the work of entire VDMA module.
4. high performance video processing as described in claim 1 and Transmission system, which is characterized in that the video processing module packet It includes:
DPC subelement, for detecting and correcting the defect pixel of input video;
CFA subelement optimizes image detail by remaining two kinds of color component of each pixel in demosaicing video frame Acutance;
CCM subelement carries out color correction operation to RGB image, including adjusts white balance, colour cast, brightness, contrast;
Gamma subelement carries out Gamma correction to video frame, reduces video distortion degree;
RGB color domain space signal is converted YUV color gamut space signal by RGB2YUV subelement;
Enhance submodule executes the enhancing of video image edge and noise reduction process, is finally exported.
5. high performance video as described in claim 1 processing and Transmission system, which is characterized in that the PCIe module includes:
Integrated PCIe submodule receives upper PC machine hair for being PCIe message format by video signal, control signal assemble The transaction layer data packet sent simultaneously decodes;
PCIe DMA submodule, high-speed transferring data provides control logic between system and upper PC machine and data transmission is logical Road, comprising:
Receiving module receives the original video data that upper PC machine sends over, and is sent in fifo module after being parsed; Sending module, receive that fifo module sends over it is processed finish data, and send it to upper PC machine;DMA control, shape Morphotype block receives the read-write control signal of PS processing system, controls the specific works of delivery and reception module.
6. high performance video processing as described in claim 1 and Transmission system, which is characterized in that the PS processing system passes through AXI interconnection module is controlled and is managed operation to remaining module of whole system.
7. high performance video processing as described in claim 1 and Transmission system, which is characterized in that the performance monitoring module, It is respectively used to the data transmission throughput of three high performance ports HP0, HP1, HP2 of monitoring and PCIe module, especially by meter Number device calculates effective data transmission times to calculate data volume per second, and the numerical value is loaded into register for upper PC machine It reads.
CN201610413861.1A 2016-06-07 2016-06-13 A kind of high performance video processing and Transmission system based on Zynq platform Active CN106060462B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610399581 2016-06-07
CN201610399581X 2016-06-07

Publications (2)

Publication Number Publication Date
CN106060462A CN106060462A (en) 2016-10-26
CN106060462B true CN106060462B (en) 2019-09-17

Family

ID=57169980

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610413861.1A Active CN106060462B (en) 2016-06-07 2016-06-13 A kind of high performance video processing and Transmission system based on Zynq platform

Country Status (1)

Country Link
CN (1) CN106060462B (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107196695A (en) * 2017-04-07 2017-09-22 西安电子科技大学 Inter-satellite Links test system based on Zynq
CN108874719B (en) * 2017-05-16 2020-10-20 杭州海康威视数字技术股份有限公司 PCIe bus-based expansion storage device
CN108107827B (en) * 2017-12-13 2021-04-27 天津津航计算技术研究所 SRIO control method based on ZYNQ platform soft core
CN109167966A (en) * 2018-09-29 2019-01-08 南京邮电大学南通研究院有限公司 Image dynamic detection system and method based on FPGA+ARM
CN110049294A (en) * 2019-05-29 2019-07-23 郑晓宇 Based on the aloof from politics and material pursuits image frame grabber of Zynq high and processing system
CN110519497B (en) * 2019-08-28 2020-11-17 中国大恒(集团)有限公司北京图像视觉技术分公司 Zero-copy trigger acquisition device and method based on VDMA
CN111917974B (en) * 2020-06-24 2022-04-15 山东浪潮科学研究院有限公司 FPGA-based video processing system, method, device and medium
CN114615537B (en) * 2020-11-24 2024-03-29 深圳市奥拓电子股份有限公司 Zero-frame-delay video control system and method and LED display system
CN113038138A (en) * 2021-04-09 2021-06-25 成都理工大学 Embedded image processing and returning system
CN113596356A (en) * 2021-06-21 2021-11-02 中国科学院新疆生态与地理研究所 Grassland mouse damage field monitoring method
CN114999192A (en) * 2022-04-11 2022-09-02 华东师范大学 Traffic signal lamp intelligent recognition device based on Zynq7020
CN114760414B (en) * 2022-04-12 2024-04-16 上海航天电子通讯设备研究所 Image acquisition and processing system for CMV4000 camera

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104636301A (en) * 2015-02-15 2015-05-20 中南大学 Large-scale PLC (programmable logic controller) high-speed backplane bus system on basis of PCI-E (peripheral component interconnect-express) interface
CN105260339A (en) * 2015-08-17 2016-01-20 中南大学 Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015112103A1 (en) * 2014-01-22 2015-07-30 Durukan Coşkun Training and experiment system supported by an animation based full simulation method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104636301A (en) * 2015-02-15 2015-05-20 中南大学 Large-scale PLC (programmable logic controller) high-speed backplane bus system on basis of PCI-E (peripheral component interconnect-express) interface
CN105260339A (en) * 2015-08-17 2016-01-20 中南大学 Large-scale PLC (Programmable logic Controller) system based on Xilinx Zynq technology

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Designing High-performance Video Systems in 7 Series FPGAs with the AXI interconnect;Pankai kumbhare等;《www.xilinx.com》;20140414;正文第6,9页
High Level Synthesis of Canny Edge Detection Algorithm on Zynq Platform;Hanaa M. Abdelgawad等;《nternational Journal of Computer, Electrical, Automation, Control and Information Engineering》;20150131;第9卷(第1期);B. Zynq Architecture、图3
Zynq-7000 All Programmable SoC ZC706 Evaluation Kit(ISE Design Suite 14.4) Getting Started Guide;xilinx;《www.xilinx.com》;20130123;正文第15-34页、图3-1

Also Published As

Publication number Publication date
CN106060462A (en) 2016-10-26

Similar Documents

Publication Publication Date Title
CN106060462B (en) A kind of high performance video processing and Transmission system based on Zynq platform
CN104427218B (en) Ultra high-definition ccd image multichannel collecting and RTTS and method
CN101309430A (en) Video image preprocessor on basis of FPGA
CN105993177A (en) Image capture accelerator
CN104270570A (en) Binocular video camera and image processing method thereof
CN102413320A (en) Method for realizing wireless network intelligent video monitoring system
CN103379266A (en) High-definition web camera with video semantic analysis function
CN105208342B (en) A kind of two-way video compression storage and network switching transmission circuit
CN104780374B (en) A kind of frame buffer compression method and device based on luminance coding
CN201249721Y (en) Vehicle lane departure prewarning device
CN103780819B (en) Intelligent industrial camera
CN108134782A (en) A kind of method based on 10,000,000,000 network transmission high-bandwidth video of FCoE protocol realizations
CN205754597U (en) A kind of multi-channel video splicing apparatus based on FPGA
CN109429043B (en) System and method for acquiring traffic sign video images based on FPGA
CN104883518A (en) Low-cost small-sized thermal infrared imager
CN204598150U (en) A kind of 3 × 3 high-definition video matrix switching device shifters based on FPGA
CN102387348B (en) Dual-code stream high-definition camera applied to intelligent transportation
CN100586179C (en) Intelligent domestic gateway presentation video control method and system thereof
WO2023156900A1 (en) Local generation of commands to a vehicle sensor
CN107707921B (en) Dynamic image processing system
CN105611211B (en) Video format switch and display device
CN205385561U (en) Tiled display systems of shielding more
CN207039793U (en) A kind of NI Vision Builder for Automated Inspection
CN103414898B (en) A kind of high-resolution video acquisition method and system
CN108848285A (en) A kind of high-definition camera processing system for video and method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant