CN103414898B - A kind of high-resolution video acquisition method and system - Google Patents
A kind of high-resolution video acquisition method and system Download PDFInfo
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Abstract
The present invention relates to video acquisition field, specifically disclose a kind of high-resolution video acquisition method and system, the method includes: by ADV7619 decoding chip, the HD video code stream that resolution is 4K is converted to YUV422 format signal, and two output channels of ADV7619 decoding chip export odd pixel point signal and even pixel point signal respectively；It is single pass YUV422 format signal by the signal syntheses of two passage outputs of ADV7619 decoding chip；YUV422 format signal is converted to YUV420 format signal, YUV420 format signal is carried out frame rate reduction processing, and the YUV420 format signal after frame rate reduction processing is re-packaged into YUV422 format signal；Sending the YUV422 format signal after encapsulation to DM8168 chip, the YUV422 format signal after encapsulation is compressed, encodes and stores by DM8168 chip.Relative to existing PCIE acquisition scheme, power consumption of the present invention is relatively low, it is simple to realize.
Description
Technical field
The present invention relates to video acquisition field, be specifically related to a kind of high-resolution video acquisition method and system.
Background technology
2K resolution (1920 × 1080) video of current popular can not meet the demand of certain customers
, some leading manufacturers have been proposed 4K resolution ((4096 × 2160,3840 × 2160)) video
Product.On whole video industry chain, a critically important part is exactly the collection to video, compresses, stores.
Wherein compressing and storing mainly has two kinds of more common devices to complete, and one is with universal cpu (Central
Processing Unit, central processing unit)；Two is with high performance DSP(digital signal processing,
Digital signal processor).Video acquisition storage device to be developed, its key point is to adopt video signal
Collection, the video stream data collected needs the EBI realizing communicating with CPU or DSP.
4K resolution video to be realized gathers and transmits signal generally by PCIE EBI, logical
Cross FPGA(Field-Programmable Gate Array, i.e. field programmable gate array) buffered video,
And by PCIE EBI with DMA(Direct Memory Access, direct memory access) side
Formula sends universal cpu to, universal cpu be compressed, storage process.Use PCIE transfer scheme,
Specifying according to its bus standard, PCIE communication speed is up to 5Gbps, so the FPGA selected must be
With high-performance stone serializer/de-serializers, its cost is higher than common FPGA.4K can be differentiated by employing
Rate video is compressed the universal cpu of coding, and its price is also far above high performance special DSP.
Using PCIE acquisition scheme, its circuit board and complete machine are the hugest, and cost is the highest.And by
In employing high performance serializer/de-serializers, so making circuit board when, needing to ensure up to
The data of 5Gbps are effectively transmitted, and the difficulty keeping signal integrity is bigger.PCIE bus protocol also compares
Complexity, PCIE bus protocol to be realized, from the data encoding of the bottom, to data packing, data route,
Arriving the DMA of application layer, interrupt management, power management, flow-control etc. again is all extremely complex operation,
Its construction cycle and debugging cycle all can be long, and this can not meet the demand that electronic equipment quickly lists.
PCIE device, with high performance serial device/deserializer, adds the biggest power consumption.The power consumption of universal cpu is also
Power consumption higher than DSP.
Summary of the invention
A kind of high-resolution video acquisition method of present invention offer and system, it realizes simple, and power consumption
Relatively low.
For reaching object above, the present invention provides a kind of high-resolution video acquisition method, including:
By ADV7619 decoding chip, the HD video code stream that resolution is 4K is converted to YUV422
Format signal, two output channels of ADV7619 decoding chip export odd pixel point signal and idol respectively
Number pixel signal；
It is single pass by the signal syntheses of two passage outputs of described ADV7619 decoding chip
YUV422 format signal；
Described YUV422 format signal is converted to YUV420 format signal, by described YUV420 lattice
Formula signal carries out frame rate reduction processing, and is re-packaged into by the YUV420 format signal after frame rate reduction processing
YUV422 format signal；
YUV422 format signal after described encapsulation is sent to DM8168 chip, described DM8168
YUV422 format signal after encapsulation is compressed, encodes and stores by chip.
High-resolution video acquisition method according to the present invention, by ADV7619 decoding chip by resolution
Be converted in the step of YUV422 format signal for the HD video code stream of 4K,
Described YUV422 format signal include brightness value and chromatic value, corresponding one of the most each pixel
Brightness value and a chromatic value.
High-resolution video acquisition method according to the present invention, is converted to described YUV422 format signal
In the step of YUV420 format signal,
Described YUV420 format signal includes brightness value and chromatic value, and the most each pixel correspondence one is bright
Angle value, two corresponding same chromatic values of pixel up and down of same frame of video.
High-resolution video acquisition method according to the present invention, by two of described ADV7619 decoding chip
The step that signal syntheses is single pass YUV422 format signal of passage output includes:
Define one 32 bit variables, by 16 letters of two passage outputs of described ADV7619 decoding chip
Number deposit to described 32 bit variables in the way of high 16 and low 16.
High-resolution video acquisition method according to the present invention, is converted to described YUV422 format signal
The step of YUV420 format signal includes:
Using the brightness value in described YUV422 format signal as the brightness of described YUV420 format signal
Value；
The chromatic value of two neighbors upper and lower in described YUV422 format signal is averaged after computing
Result as two adjacent image points upper and lower in described YUV420 format signal share chromatic value.
High-resolution video acquisition method according to the present invention, drops described YUV420 format signal
The step that frame processes includes:
Described YUV420 format signal is stored to buffer in units of frame of video, and according to 15 frames
Speed per second reads.
High-resolution video acquisition method according to the present invention, believes the YUV420 form after frame rate reduction processing
The step number being re-packaged into YUV422 format signal includes:
Using the brightness value of YUV420 format signal in each frame of video as the YUV422 form after encapsulation
The brightness value of signal；
Using the chromatic value of YUV420 format signal in each frame of video as the YUV422 form after encapsulation
The front portion of the chromatic value of signal, another part of the YUV422 format signal chromatic value after encapsulation is defeated
Go out to fix invalid data.
High-resolution video acquisition method according to the present invention, described method also includes:
Produce and meet the timing control signal of described DM8168 chip collection port and send to the most described
DM8168 chip, described timing control signal includes row signal, field signal and clock signal.
The present invention provides a kind of high-resolution video acquisition system accordingly, including:
ADV7619 decoding chip, for being converted to YUV422 by the HD video code stream that resolution is 4K
Format signal, two output channels of ADV7619 decoding chip export odd pixel point signal and idol respectively
Number pixel signal；
Signal synthesizing module, for closing the signal of two passage outputs of described ADV7619 decoding chip
Become single pass YUV422 format signal；
Format converting module, for being converted to YUV420 format signal by described YUV422 format signal；
Fall frame and package module, for described YUV420 format signal being carried out frame rate reduction processing, and will fall
YUV420 format signal after frame process is re-packaged into YUV422 format signal and sends to DM8168
Chip；
Described DM8168 chip, for being compressed the YUV422 format signal after encapsulation, encode
And storage.
High-resolution video acquisition system according to the present invention, including of described YUV422 format signal is bright
Angle value and chromatic value, the corresponding brightness value of the most each pixel and a chromatic value.
High-resolution video acquisition system according to the present invention, described YUV420 format signal includes brightness
Value and chromatic value, the corresponding brightness value of the most each pixel, two pixel correspondences up and down of same frame of video
Same chromatic value.
High-resolution video acquisition system according to the present invention, described signal synthesizing module is for definition 1
Bit variable, and by 16 signals of two passage outputs of described ADV7619 decoding chip with high 16
Deposit to described 32 bit variables with the mode of low 16.
High-resolution video acquisition system according to the present invention, described format converting module is additionally operable to described
Brightness value in YUV422 format signal is as the brightness value of described YUV420 format signal；And by institute
State the result after computing that is averaged of the chromatic value of upper and lower two neighbors in YUV422 format signal to make
The chromatic value shared for two adjacent image points upper and lower in described YUV420 format signal.
High-resolution video acquisition system according to the present invention, described fall frame and package module are additionally operable to described
YUV420 format signal stores to buffer in units of frame of video, and according to 15 frames speed per second
Read.
High-resolution video acquisition system according to the present invention, described fall frame and package module are additionally operable to each
In frame of video, the brightness value of YUV420 format signal is as the brightness of the YUV422 format signal after encapsulation
Value；And using the chromatic value of YUV420 format signal in each frame of video as encapsulation after YUV422
The front portion of the chromatic value of format signal, another portion of the YUV422 format signal chromatic value after encapsulation
Output one is divided to fix invalid data.
High-resolution video acquisition system according to the present invention, described system also includes that timing control signal produces
Module, for producing the timing control signal meeting described DM8168 chip collection port and sending to the most described
DM8168 chip, described timing control signal includes row signal, field signal and clock signal.
The HD video code stream that resolution is 4K is converted to by the present invention by ADV7619 decoding chip
YUV422 format signal, then by signal synthesizing module by defeated for two passages of ADV7619 decoding chip
The signal syntheses gone out is single pass YUV422 format signal, and signal format modular converter is by YUV422
Format signal is converted to YUV420 format signal, and YUV420 format signal is entered by fall frame and package module
Row frame rate reduction processing, and the YUV420 format signal after frame rate reduction processing is re-packaged into YUV422 form
Signal sends to DM8168 chip；YUV422 format signal after encapsulation is carried out by DM8168 chip
Compress, encode and store.Wherein signal synthesizing module, signal format modular converter, fall frame and package module
Realized by FPGA, and FPGA need not, with high-performance stone serializer/de-serializers, reduce merit
Consumption.In the present invention, due to the limitation of dsp processor part DM8168 chip, its video acquisition connects
Mouthful only support YUV422 formatted data, but its compression, coding need YUV420 data.Generally DM8168
Chip is all completed from video acquisition mouth by one coprocessor processing high-resolution data when
YUV422 changes to the YUV420 required for compression, coding, but the present invention do not supported by this coprocessor
4K resolution to be solved, so using signal format modular converter by YUV422 lattice in the present invention
Formula signal is converted to YUV420 format signal, and uses fall frame and package module by YUV420 form
Signal is re-packaged into meeting the YUV422 format signal of DM8168 chip video acquisition interface, encapsulation
After signal can be transmitted by DM8168 chip video acquisition interface, and the signal after this encapsulation
Include the compression of DM8168 chip, coding needs YUV420 data so that DM8168 chip can
Input signal is compressed coding, relative to the realization of PCIE bus protocol, the present invention in prior art
Realize the simplest.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to be briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the system construction drawing of the present invention a kind of high-resolution video acquisition system；
Fig. 2 is the flow chart of the present invention a kind of high-resolution video acquisition method.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
The every other embodiment obtained under property work premise, broadly falls into the scope of protection of the invention.
As it is shown in figure 1, one high-resolution video acquisition system 100 of the present invention, solve including ADV7619
Code chip 10, signal synthesizing module 20, format converting module 30, fall frame and package module 40 and
DM8168 chip 50.During high-resolution video gathers, due to the signal format of front-end camera
Do not meet the call format of memorizer, it is therefore desirable to the video signal of video camera picked-up is carried out a series of lattice
After formula conversion (process decode, compress, encoded), just can store.The present invention passes through ADV7619
The signal of front-end camera is decoded by decoding chip 10, is carried out signal by DM8168 chip 50
Compress, encode and store.The decoded video signal format of ADV7619 decoding chip 10 is YUV422
Form, and owing to the video acquisition interface of DM8168 chip 50 only supports YUV422 formatted data, but
DM8168 chip 50 is compressed, coded treatment needs YUV420 data, usual DM8168 chip
All completed from video acquisition mouth by one coprocessor processing high-resolution data when
YUV422 changes to the YUV420 required for compression, coding, but the present invention do not supported by this coprocessor
4K resolution to be solved, therefore can not by the decoded video signal of ADV7619 decoding chip 10
It is sent directly to DM8168 chip 50 and is compressed coding, need to be changed by a series of form.This
Invention is passed through signal synthesizing module 20, format converting module 30, fall frame and package module 40 right
The decoded video signal of ADV7619 decoding chip 10 carries out a series of format conversion and frame rate reduction processing,
Decoded video signal is converted to meet the YUV422 of the video acquisition interface of DM8168 chip 50
YUV422 format signal after format signal, and this conversion includes YUV420 data, it is possible to use
It is compressed coding in DM8168 chip 50.Wherein, signal synthesizing module 20, format converting module 30,
Fall frame and package module 40 are all realized by FPGA.
ADV7619 decoding chip 10, for being converted to the HD video code stream that resolution is 4K
YUV422 format signal, two output channels of ADV7619 decoding chip export odd pixel point respectively
Signal and even pixel point signal.Owing to the output of most 4K resolution video source (such as camera signal) is
With HDMI(High Definition Multimedia Interface, HDMI) form is defeated
Go out, so before processing video data signal, needing to use decoding chip that HDMI signal is decoded.
Support at present is not the most a lot of to the front-end chip of 4K resolution, and the ADV7619 chip of ADI company is
The more commonly used is a, and its Main Function is responsible for decoding the 4K resolution video of HDMI.Aobvious and
It is clear to, if 4K resolution video source is output as other high-definition formats, then may be used without other decoding core
Sheet is decoded.ADV7619 decoding chip 10 is output as dual pathways output in 4K resolution,
One passage output odd pixel point signal, a passage output even pixel point signal.
Signal synthesizing module 20, for the signal syntheses by two passage outputs of ADV7619 decoding chip
For single pass YUV422 format signal.Letter due to two passage outputs of ADV7619 decoding chip
Number being the synchronizing signal under same clock, each channel signal is 16, and the dual pathways is converted to list
The simplest way of passage defines one 32 bit variables exactly, and by two of ADV7619 decoding chip 10
16 signals of passage output are deposited to 32 bit variables in the way of high 16 and low 16.So single-pass
The synchronised clock of road signal does not changes, and simply storage bit wide has expanded one times.
Format converting module 30, for being converted to YUV420 format signal by YUV422 format signal.
Owing to rear end DM8168 chip 50 compresses, encodes and need YUV420 format signal, therefore the present invention adopts
By format converting module 30, decoded YUV422 format signal is converted to YUV420 format signal.
YUV422 format signal include brightness value and chromatic value, the corresponding brightness of the most each picture element
Value and a chromatic value.YUV420 format signal includes brightness value and chromatic value, the most each picture element pair
Answer a brightness value, two corresponding same chromatic values of picture element up and down of same frame of video.Therefore, at this
In bright, the algorithm that YUV422 form turns YUV420 form is to use brightness value to keep constant, up and down
Two adjacent chromatic values do one new chromatic value of average generation, thus complete conversion.Namely form turns
Die change block 30 is additionally operable to bright as YUV420 format signal of the brightness value in YUV422 format signal
Angle value；And computing that the chromatic value of two neighbors upper and lower in YUV422 format signal is averaged
After result as two adjacent image points upper and lower in YUV420 format signal share chromatic value.Concrete,
One RAM can be set in FPGA, by the chromatic value caching of odd-numbered line in same frame of video, then to even
Read the when of several rows, done averagely with the chromatic value of the pixel of current even number line, after being changed
Data.
Fall frame and package module 40, for YUV420 format signal carries out frame rate reduction processing, and will drop frame
YUV420 format signal after process is re-packaged into YUV422 format signal and sends to DM8168 core
Sheet.The work that fall frame and package module 40 are made includes two parts, and a part is to YUV420 form
Signal carries out frame rate reduction processing, concrete, YUV420 format signal can be stored in units of frame of video to
In one buffer, and read according to the speed that 15 frames are per second；Another part is by after frame rate reduction processing
YUV420 format signal is re-packaged into YUV422 format signal, concrete, by each frame of video
The brightness value of YUV420 format signal is as the brightness value of the YUV422 format signal after encapsulation；By each
In frame of video, the chromatic value of YUV420 format signal is as the colourity of the YUV422 format signal after encapsulation
The front portion of value, nothing is fixed in another part output one of the YUV422 format signal chromatic value after encapsulation
Effect data.
In one embodiment of the invention, fall frame and encapsulation work can be by 4K video signal in units of frames
Storage is to buffer (can be selected for DDR2), then reads on request.The reason doing frame buffer is needed to have two,
One is that the signal of YUV420 form after format converting module 30 conversion can not be directly by DM8168 core
The video acquisition mouth of sheet 50 gathers, it is necessary to the data of YUV420 be encapsulated in the data of YUV422,
Output is to the video acquisition mouth of DM8168 chip 50 again, needs to do frame buffer to realize data syn-chronization；Two
It is to do fall frame operation, owing to the performance of DM8168 chip 50 limits, the compression of 15 frames, volume can only be realized
Code, so needing caching frame to drop frame.It is required for a FIFO(First before the write and reading of depositor
Input First Output, First Input First Output) carry out speed and bit width conversion with cache controller mutually
Joining, cache controller mainly completes the Read-write Catrol to buffer.The present invention uses read-write frame to realize at fall frame
Reason, i.e. arranges three cachings, and write and read circulates between these three caches, by three read-write states cached
Do parameter and form a table, indicate the caching frame that currently should operate according to this table.Due to frame rate reduction processing
Detailed process the emphasis of non-invention, therefore do not retouch the detailed process of frame rate reduction processing in detail at this
State, refer to prior art.
It addition, YUV422 form is with the difference of YUV420 form: YUV422 form be one bright
The corresponding chromatic value of angle value, and YUV420 form is corresponding one of the brightness value of upper and lower two picture elements
Chromatic value.So the chromatic value data volume of YUV420 format signal is the half of YUV422 format signal.
So when being stored in the 4K frame of video inside DDR2 with the reading of YUV422 data form, chromatic value
Above half from DDR2 read, after half output one fixing invalid data " 128 " the most permissible.
Which achieves data form is YUV422, and data content further comprises complete YUV420 form.
DM8168 chip 50, for encapsulation after YUV422 format signal be compressed, encode and
Storage.The video acquisition mouth of DM8168 chip 50 is to be by bright by the YUV422 format signal collected
Degree and colourity are deposited respectively, so its YUV422 format signal processed through above-mentioned way of adopting
It it is the chrominance section of complete luminance part and the complete YUV420 fixing invalid data that adds other half
" 128 ", it is possible to these data as YUV420 data to DM8168 compression, coding and
Storage.DM8168 chip 50 has the ability simultaneously encoding two-way 4K resolution 15 frame video.But
DM8168 chip 50 also has its limitation, and one, the coding 4K resolution of DM8168 chip 50 can only
Reach 15 frames, but in actual video security protection, the application of monitoring field, to the storage frame per second of video not
Extremely value, though cost, the power dissipation ratio of equipment is relatively valued；Two, DM8168 chip 50 can not
Completing to be converted to by YUV422 YUV420 in 4K resolution, this point is changed by form of the present invention
Module 30, fall frame and package module 40 can ingenious be avoided.
Preferably, high-resolution video acquisition system 100 also includes timing control signal generation module 60,
Timing control signal generation module 60 meets DM8168 chip 50 for generation and gathers the sequencing contro of port
Signal also sends to DM8168 chip 50, and timing control signal includes row signal, field signal and clock
Signal.
The signal synthesizing module 20 of the present invention, signal format modular converter 30, fall frame and package module 40
Realized by FPGA, and FPGA need not, with high-performance stone serializer/de-serializers, reduce merit
Consumption.The present invention use signal format modular converter 30 YUV422 format signal is converted to YUV420
Format signal, and use fall frame and package module 40 to be re-packaged into meeting by YUV420 format signal
The YUV422 format signal of DM8168 chip video acquisition interface, the signal after encapsulation can pass through
DM8168 chip video acquisition interface transmits, and the signal after this encapsulation includes DM8168 core
Sheet compression, coding need YUV420 data so that input signal can be pressed by DM8168 chip
Reducing the staff code, relative to the realization of PCIE bus protocol in prior art, the present invention realizes the simplest.
As in figure 2 it is shown, the present invention provides a kind of high-resolution video acquisition method accordingly, it is by such as Fig. 1
Shown system realizes, and the method comprises the steps:
Step S201, is changed the HD video code stream that resolution is 4K by ADV7619 decoding chip
For YUV422 format signal, two output channels of ADV7619 decoding chip export odd pixel respectively
Point signal and even pixel point signal.This step is realized by ADV7619 decoding chip 10.
Step S202, is single pass by the signal syntheses of two passage outputs of ADV7619 decoding chip
YUV422 format signal.This step is realized by signal synthesizing module 20.YUV422 format signal
Including brightness value and chromatic value, the corresponding brightness value of the most each pixel and a chromatic value.
Step S203, is converted to YUV420 format signal by YUV422 format signal, by YUV420
Format signal carries out frame rate reduction processing, and is re-packaged into by the YUV420 format signal after frame rate reduction processing
YUV422 format signal.This step realizes reality by format converting module 30, fall frame and package module 40
Existing.YUV420 format signal includes brightness value and chromatic value, the corresponding brightness value of the most each pixel,
Two corresponding same chromatic values of pixel up and down of same frame of video.
Step S204, sends the YUV422 format signal after encapsulation to DM8168 chip, DM8168
YUV422 format signal after encapsulation is compressed, encodes and stores by chip.This step is passed through
DM8168 chip 50 realizes.
Preferably, step S202 includes: definition one 32 bit variables, and described ADV7619 is decoded core
16 signals of two passage outputs of sheet are deposited to described 32 changes in the way of high 16 and low 16
Amount.
Preferably, in step S203, YUV422 format signal is converted to YUV420 form letter
Number step include: using bright as YUV420 format signal of the brightness value in YUV422 format signal
Angle value；The chromatic value of two neighbors upper and lower in YUV422 format signal is averaged after computing
The chromatic value that result shares as two adjacent image points upper and lower in YUV420 format signal.
Preferably, in step S203, described YUV420 format signal is carried out the step of frame rate reduction processing
Suddenly include: YUV420 format signal is stored to buffer in units of frame of video, and according to 15 frames
Speed per second reads.
Preferably, in step S203, by the YUV420 format signal Reseal after frame rate reduction processing
Step for YUV422 format signal includes: by the brightness of YUV420 format signal in each frame of video
The brightness value of the YUV422 format signal after being worth as encapsulation；By YUV420 form in each frame of video
The chromatic value of signal is as the front portion of the chromatic value of the YUV422 format signal after encapsulation, after encapsulation
Another part output of YUV422 format signal chromatic value one fix invalid data.
Preferably, high-resolution video acquisition method method also includes: produces and meets described DM8168
Chip gathers the timing control signal of port and sends to described DM8168 chip, described timing control signal
Including row signal, field signal and clock signal.
In sum, the present invention by ADV7619 decoding chip by HD video code that resolution is 4K
Circulation is changed to YUV422 format signal, then by signal synthesizing module by the two of ADV7619 decoding chip
The signal syntheses of individual passage output is single pass YUV422 format signal, and signal format modular converter will
YUV422 format signal is converted to YUV420 format signal, and fall frame and package module are by YUV420 lattice
Formula signal carries out frame rate reduction processing, and is re-packaged into by the YUV420 format signal after frame rate reduction processing
YUV422 format signal sends to DM8168 chip；DM8168 chip is to the YUV422 after encapsulation
Format signal is compressed, encodes and stores.Wherein signal synthesizing module, signal format modular converter, fall
Frame and package module are realized by FPGA, and FPGA need not with high-performance stone serializer/unstring
Device, reduces power consumption.In the present invention, due to the limitation of dsp processor part DM8168 chip,
Its video acquisition interface only supports YUV422 formatted data, but its compression, coding need YUV420 number
According to.Generally DM8168 chip is all to be completed by one coprocessor processing high-resolution data when
From the YUV420 conversion required for the YUV422 of video acquisition mouth to compression, coding, but this association processes
4K resolution to be solved by this invention do not supported by device, so using signal format conversion in the present invention
YUV422 format signal is converted to YUV420 format signal by module, and uses fall frame and Encapsulation Moulds
YUV420 format signal is re-packaged into meeting the YUV422 of DM8168 chip video acquisition interface by block
Format signal, the signal after encapsulation can be transmitted by DM8168 chip video acquisition interface, and
Signal after this encapsulation includes the compression of DM8168 chip, coding needs YUV420 data so that
DM8168 chip can be compressed coding to input signal, assists relative to PCIE bus in prior art
The realization of view, the present invention realizes the simplest.
Principle and the embodiment of the present invention are set forth by specific case used herein, above enforcement
The explanation of example is only intended to help to understand the core concept of the present invention；General technology simultaneously for this area
Personnel, according to the thought of the present invention, the most all will change, and combine
Upper described, this specification content should not be construed as limitation of the present invention.
Claims (14)
1. a high-resolution video acquisition method, it is characterised in that including:
By ADV7619 decoding chip, the HD video code stream that resolution is 4K is converted to YUV422
Format signal, two output channels of ADV7619 decoding chip export odd pixel point signal and even number respectively
Pixel signal；
It is single pass by the signal syntheses of two passage outputs of described ADV7619 decoding chip
YUV422 format signal, the described signal by two passage outputs of described ADV7619 decoding chip closes
Become single pass YUV422 format signal to include: definition one 32 bit variables, described ADV7619 is solved
16 signals of two passage outputs of code chip are deposited to described 32 in the way of high 16 and low 16
Bit variable；
Described YUV422 format signal is converted to YUV420 format signal, by described YUV420 form
Signal carries out frame rate reduction processing, and the YUV420 format signal after frame rate reduction processing is re-packaged into YUV422
Format signal；
YUV422 format signal after described encapsulation is sent to DM8168 chip, described DM8168 core
YUV422 format signal after encapsulation is compressed, encodes and stores by sheet.
High-resolution video acquisition method the most according to claim 1, it is characterised in that pass through
The HD video code stream that resolution is 4K is converted to YUV422 format signal by ADV7619 decoding chip
In step,
Described YUV422 format signal include brightness value and chromatic value, the most each pixel corresponding one bright
Angle value and a chromatic value.
High-resolution video acquisition method the most according to claim 2, it is characterised in that by described
YUV422 format signal is converted in the step of YUV420 format signal,
Described YUV420 format signal includes brightness value and chromatic value, the corresponding brightness of the most each pixel
Value, two corresponding same chromatic values of pixel up and down of same frame of video.
High-resolution video acquisition method the most according to claim 3, it is characterised in that by described
YUV422 format signal is converted to the step of YUV420 format signal and includes:
Using the brightness value in described YUV422 format signal as the brightness of described YUV420 format signal
Value；
The chromatic value of two neighbors upper and lower in described YUV422 format signal is averaged after computing
The chromatic value that result shares as two adjacent image points upper and lower in described YUV420 format signal.
High-resolution video acquisition method the most according to claim 1, it is characterised in that by described
YUV420 format signal carries out the step of frame rate reduction processing and includes:
Described YUV420 format signal is stored to buffer in units of frame of video, and according to 15 frames
Speed per second reads.
High-resolution video acquisition method the most according to claim 3, it is characterised in that will drop at frame
YUV420 format signal after reason is re-packaged into the step of YUV422 format signal and includes:
Using the brightness value of YUV420 format signal in each frame of video as the YUV422 form letter after encapsulation
Number brightness value；
Using the chromatic value of YUV420 format signal in each frame of video as the YUV422 form letter after encapsulation
Number the front portion of chromatic value, another part output one of the YUV422 format signal chromatic value after encapsulation
Fixing invalid data.
High-resolution video acquisition method the most according to claim 1, it is characterised in that described method
Also include:
Produce and meet the timing control signal of described DM8168 chip collection port and send to the most described
DM8168 chip, described timing control signal includes row signal, field signal and clock signal.
8. a high-resolution video acquisition system, it is characterised in that including:
ADV7619 decoding chip, for being converted to YUV422 by the HD video code stream that resolution is 4K
Format signal, two output channels of ADV7619 decoding chip export odd pixel point signal and even number respectively
Pixel signal；
Signal synthesizing module, for closing the signal of two passage outputs of described ADV7619 decoding chip
Become single pass YUV422 format signal, described by two passages of described ADV7619 decoding chip
The signal syntheses of output is that single pass YUV422 format signal includes: definition one 32 bit variables, by institute
State 16 signals of two passage outputs of ADV7619 decoding chip in the way of high 16 and low 16
Deposit to described 32 bit variables；
Format converting module, for being converted to YUV420 format signal by described YUV422 format signal；
Fall frame and package module, for described YUV420 format signal is carried out frame rate reduction processing, and will drop frame
YUV420 format signal after process is re-packaged into YUV422 format signal and sends to DM8168 core
Sheet；
Described DM8168 chip, for encapsulation after YUV422 format signal be compressed, encode and
Storage.
High-resolution video acquisition system the most according to claim 8, it is characterised in that described
YUV422 format signal include brightness value and chromatic value, the corresponding brightness value and of the most each pixel
Individual chromatic value.
High-resolution video acquisition system the most according to claim 9, it is characterised in that described
YUV420 format signal includes brightness value and chromatic value, the corresponding brightness value of the most each pixel, same
Two corresponding same chromatic values of pixel up and down of frame of video.
11. high-resolution video acquisition systems according to claim 10, it is characterised in that described lattice
Formula modular converter is additionally operable to the brightness value in described YUV422 format signal as described YUV420 form
The brightness value of signal；And the chromatic value of two neighbors upper and lower in described YUV422 format signal is entered
The color that result after row average calculating operation shares as two adjacent image points upper and lower in described YUV420 format signal
Angle value.
12. high-resolution video acquisition systems according to claim 8, it is characterised in that described fall
Frame and package module are additionally operable to store to buffer described YUV420 format signal in units of frame of video
In, and read according to the speed that 15 frames are per second.
13. high-resolution video acquisition systems according to claim 10, it is characterised in that described fall
Frame and package module be additionally operable to using the brightness value of YUV420 format signal in each frame of video as encapsulation after
The brightness value of YUV422 format signal；And by the chromatic value of YUV420 format signal in each frame of video
As the front portion of the chromatic value of the YUV422 format signal after encapsulation, the YUV422 form after encapsulation
Invalid data is fixed in another part output one of signal colouration angle value.
14. high-resolution video acquisition systems according to claim 8, it is characterised in that described system
System also includes timing control signal generation module, meets described DM8168 chip collection port for producing
Timing control signal also sends to described DM8168 chip, and described timing control signal includes row signal, field
Signal and clock signal.
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| CN101296303A (en) * | 2008-03-06 | 2008-10-29 | 麦克奥迪实业集团有限公司 | High-definition picture processing method and device |
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