CN107707921B - Dynamic image processing system - Google Patents
Dynamic image processing system Download PDFInfo
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- CN107707921B CN107707921B CN201710576462.1A CN201710576462A CN107707921B CN 107707921 B CN107707921 B CN 107707921B CN 201710576462 A CN201710576462 A CN 201710576462A CN 107707921 B CN107707921 B CN 107707921B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/172—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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Abstract
The invention discloses a dynamic image processing system, comprising: the system comprises 2 image acquisition modules, 1 image routing and analog-to-digital conversion module, 1 image compression module, 1 image network output module, 1 image cache RS485 output module, a power supply conversion unit and an upper computer, wherein key coding frames with large data volume generated after image compression are unpacked, packages of key frames and packages of common frames are packed, the data volume of each sending package is ensured to be fixed, bandwidth resources occupied at each moment during data output are fixed, and H.265 image compression coding transmission can be carried out under the conditions of aerospace vehicles, carriers, satellite telemetry bandwidth resources and tension of the data full bandwidth output.
Description
Technical Field
The invention relates to the technical field of narrow-band video monitoring of aerospace vehicles, carriers, satellite telemetering and the like, in particular to a dynamic image processing system.
Background
At present, the main mode for processing video images is based on compression coding of MPEG-2, MPEG-4 and H.264, but with the requirement of high definition of video images in the image field, the H.265 compression coding mode is generated. In terms of coding performance, the coding efficiency of h.265 is doubled compared with that of h.264, i.e. the bit rate is reduced by 50% on the premise of ensuring the same video image quality. However, under the condition of extremely limited bandwidth resources, especially under the condition of telemetry bandwidth resources of aircrafts, carriers and satellites and under the tense use condition of the bandwidth resources, the image coded by H.265 still has a frame clamping or unclear phenomenon, and the actual use requirement cannot be met.
Most of domestic video compression devices perform compression coding based on H.264, and some video compression devices perform compression coding based on H.265, but all the video compression devices perform simple image compression coding according to the H.265 protocol, the utilization rate of bandwidth resources is not high for image data transmission after compression coding, and under the condition of limited bandwidth resources, the transmission can be performed only by reducing the image quality, so that the image quality cannot meet the use requirement.
Disclosure of Invention
The invention mainly solves the technical problem of providing a dynamic image processing system which can carry out H.265 image compression coding transmission under the conditions of aerospace vehicles, carriers, satellite telemetry bandwidth resources and tension thereof.
The invention discloses a dynamic image processing system technical scheme, which comprises the following steps: comprises 2 image acquisition modules, 1 image routing and analog-to-digital conversion module, 1 image compression module, 1 image network output module and 1 image buffer RS485 output module,
wherein: the image routing and analog-to-digital conversion module comprises an image routing unit and an analog-to-digital conversion unit, wherein the routing chip selects a high-speed video routing chip, and the analog-to-digital conversion chip selects an 8-bit analog image sampling converter;
the image compression module comprises a main controller and a memory, wherein the main controller adopts a Unix-based embedded H.265 high-definition video coding and decoding chip, and the memory adopts a low-power-consumption high-efficiency DDR3L chip;
the image acquisition module comprises an image sensor and a sensor interface, wherein the image sensor is a 700-line CCD sensor component with high signal-to-noise ratio;
the image network output module selects a gigabit network chip supporting the IEEE802.3 standard;
and the image cache RS485 output module selects a programmable logic device FPGA chip with programs running in parallel.
The image acquisition module is connected with the image routing and analog-to-digital conversion module through a cvbs bus, and the image routing and analog-to-digital conversion module is connected with the image compression module through a parallel data bus; the image acquisition module acquires images in real time, transmits the acquired analog images to the image routing and analog-to-digital conversion module in a cvbs interface mode, converts one path of analog images into digital images after routing and analog-to-digital conversion, and transmits the digital images to the image compression module in a parallel data bus mode, image compression coding is realized in the image compression module, the image compression module can output the digital images in real time in an RPST protocol mode through an image network output module, and can also perform data interaction with an upper computer in an RS485 bus mode after being cached through an image cache RS485 output module.
The invention also comprises a power supply conversion unit, wherein the input end of the power supply conversion unit is connected with an external power supply, the output end of the power supply conversion unit is respectively connected with the image acquisition module, the image routing and analog-to-digital conversion module, the image compression module, the image network output module and the image cache RS485 output module, and the external power supply supplies power to each unit through the power supply conversion unit.
In the invention, data interaction is carried out with the upper computer and the image compression module through the programming of the image cache RS485 output module, so that the contradiction between the non-real-time property of a Unix embedded operating system in the image compression module and the real-time property of the request of the upper computer for responding can be solved.
In the invention, the H.265 compression coding unpacks the key coding frame with large data volume generated after image compression, and packs the key frame packet and the common frame packet, so that the data volume of each sending packet is fixed, the occupied bandwidth resource is fixed at each moment when data is output, and the full bandwidth output of the data can be ensured.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a schematic diagram of the operation of the improved H.265 compression encoding;
fig. 3 is a flowchart of the operation of the image buffer RS485 output module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
A dynamic image processing system is shown in figure 1 and comprises 2 image acquisition modules, 1 image routing and analog-to-digital conversion module, 1 image compression module, 1 image network output module, 1 image cache RS485 output module and an upper computer. The image acquisition module is used for acquiring images in real time; the image routing and analog-to-digital conversion module is used for converting one path of analog image into a digital image according to requirements; the image compression module is used for carrying out compression coding on the digital image; the image network output module is used for outputting the coded image in real time through a network; and the image buffer RS485 output module is used for buffering the encoded image data and outputting the image data through RS 485.
The image acquisition module comprises an image sensor and a sensor interface. Due to the reliability of long-distance transmission of analog signals, a CCD camera for outputting analog images is selected as the image sensor. In order to facilitate the subsequent processing of the image, a corresponding image sensor interface circuit is generally used at the output part of the image sensor for taking out the image acquired by the image sensor from the inside of the sensor. In this embodiment, the image sensor employs a 700-line Effio-series CCD device manufactured by SONY corporation, and the sensor interface employs a CVBS interface.
The image routing and analog-to-digital conversion module comprises an image routing unit and an analog-to-digital conversion unit. The image routing unit selects MAX4310 produced by MAXIM company, is suitable for high-speed video signal switching, and has the characteristics of low delay, low power consumption and low error switching. The analog-to-digital conversion unit selects ADV7180 produced by AD company, ADV7180 is an analog-to-digital conversion chip produced by AD company for video signals, can automatically detect analog television signals of NTSC, PAL, SECAM and the like, and converts video data into YUV422 format compatible with 8-bit ITU-R.656 interface standard.
The image compression module comprises an image compression main controller unit and a memory unit. The image compression main controller unit adopts a Unix-based embedded H.265 high-definition video coding and decoding chip, such as Hi3516A, and is a high-performance communication media processor based on an ARM Cortex A9 processor core and a video hardware acceleration engine. The memory unit adopts a DDR3L chip with low power consumption and high efficiency.
1. Media processing platform programming interface (MPI) of system control module
The system control module is an internal software module used for controlling the whole system in the Hi3516A, and the media processing platform programming interface (MPI) is a program calling interface and can be used for calling all the internal software modules in the Hi3516A to complete corresponding software functions.
2. The VI module (fully referred to as Video Input) is a Video Input software module in Hi 3516A.
3. The VPSS module (collectively referred to as Video Process Sub-System) is a Video preprocessing software module in Hi 3516A.
4. The VENC module (fully known as Video Encoder) is a Video coding software module in Hi 3516A.
5. The IO port (all called Input-Output) is a pin for Input and Output in the chip, and can be used for signal Input and signal Output.
In the embodiment of the invention, the system also comprises a power supply conversion unit, wherein the input end of the power supply conversion unit is connected with an external power supply, the output end of the power supply conversion unit is respectively connected with the image acquisition module, the image routing and analog-to-digital conversion module, the image compression module, the image network output module and the image cache RS485 output module, and the external power supply supplies power to each unit through the power supply conversion unit.
The image compression flow shown in fig. 2 is as follows:
the method comprises the following steps: calling a media processing platform programming interface (MPI) of a system control module to finish hardware and MPP initialization, wherein the main function is to allocate a video cache pool;
step two: calling MPI of the VI module to create video input equipment and a video physical channel and set parameters;
step three: calling MPI of a VPSS module to create a group and a channel, setting parameters of the group and the channel, and outputting video data with expected resolution;
step four: calling MPI of a VENC module to perform H.265 compression coding on the YUV original image to obtain an H265 format code stream;
step five: obtaining the information of each frame of image according to the H.265 format code stream, wherein the information comprises the size of one frame of image (not more than 65535) and a key frame identifier (1 or 0);
step six: unpacking the image frame according to the frame information, and specifying the size of each packet (not more than 61), the number of packets in each image (not more than 255), the serial number of each packet (not more than 255) and compressed image data to ensure that the amount of the compressed image data sent by each packet is constant;
step seven: and after unpacking, grouping the key frame packet and the common frame packet, and then putting the key frame packet and the common frame packet into a cache for output.
The image network output module selects a gigabit network chip supporting IEEE802.3 standard, such as RTL8211 chip produced by Realtek company, supports 10/100/1000Mbps network transmission rate self-adaptation, and can determine the working mode through the detection of the level state of a specific IO port.
The image cache RS485 output module selects a programmable logic device FPGA chip with programs running in parallel, and communicates with the upper computer through FPGA cache data, so that the defect of poor real-time performance of an embedded Unix operating system in the image compression module is effectively overcome, and the real-time performance of communication with the upper computer is improved.
The image buffer RS485 output module shown in fig. 3 has the following working flow:
the method comprises the following steps: after receiving the request instruction of the upper computer, the FPGA of the programmable logic device checks whether video compression data exist in a cache or not; if the cache has video compression data, sending the video compression data to the upper computer through RS485 according to a telemetry protocol, and if the cache does not have the video compression data, sending the effective data bits to the upper computer through RS485 after zero padding according to the protocol requirement;
step two: after the data is sent, analyzing routing information according to the request instruction of the upper computer, and outputting the routing information of the image acquisition module to the image compression module through the IO port;
step three: after receiving the route selection information of the image acquisition module, the image compression module performs image compression on the image output by one of the image acquisition modules;
step four: the image compression module sends the video compression data in the cache to an image cache RS485 output module in an SPI bus mode;
step five: the image cache RS485 output module receives the video compression data in an SPI bus mode, stores the video compression data into a cache, and outputs the video compression data to an upper computer through an RS485 bus after waiting for an instruction requested by the upper computer.
And circulating the steps from the first step to the fifth step, and outputting the compressed image data to an upper computer through an image cache RS485 output module.
Because the response time of the embedded Unix operating system is millisecond level, the FPGA firstly responds to the request and then sends the request information to the image compression module, so that the embedded Unix operating system in the image compression module has enough response time, and the real-time performance of the communication between the FPGA and an upper computer is ensured.
Claims (1)
1. A dynamic image processing system comprising: 2 image acquisition modules, 1 image routing and analog-to-digital conversion module, 1 image compression module, 1 image network output module, 1 image cache RS485 output module and a power supply conversion unit; wherein: the image routing and analog-to-digital conversion module comprises an image routing unit and an analog/digital conversion unit, and consists of a high-speed video routing chip and an 8-bit analog image sampling converter, automatically detects analog television signals of NTSC, PAL and SECAM modes, and converts video data into YUV422 format compatible with 8-bit ITU-R.656 interface standard; the image compression module comprises a Unix-based embedded H.265 high-definition video coding and decoding chip and a low-power-consumption high-efficiency DDR3L chip, and consists of a system control module, a media processing platform programming interface MPI, a video input module VI, a video pre-processing module VPSS, a video coding software module VENC and a signal input/output IO port; the image acquisition module comprises a 700-line CCD sensor component with high signal-to-noise ratio, the image network output module comprises a gigabit network chip supporting the IEEE802.3 standard, and the image cache RS485 output module comprises a programmable logic device FPGA chip with programs running in parallel;
the image acquisition module is connected with the image routing and analog/digital conversion module through a cvbs bus, and the image routing and analog/digital conversion module is connected with the image compression module through a parallel data bus; the image acquisition module acquires images in real time, transmits the acquired analog images to the image routing and analog/digital conversion module in a cvbs interface mode, converts one path of analog images into digital images after routing and analog/digital conversion, transmits the digital images to the image compression module in a parallel data bus mode, realizes image compression coding in the image compression module, and performs data interaction with an upper computer in an RS485 bus mode after the image compression module outputs data in real time in an RPST protocol mode through an image network output module and caches the data through an image cache RS485 output module;
the input end of the power supply conversion unit is connected with an external power supply, the output end of the power supply conversion unit is respectively connected with the image acquisition module, the image routing and analog/digital conversion module, the image compression module, the image network output module and the image cache RS485 output module, and the external power supply supplies power to all the units through the power supply conversion unit;
the image processing flow based on the Unix embedded H.265 high-definition video coding and decoding chip and the low-power-consumption high-efficiency DDR3L chip is as follows:
the method comprises the following steps: calling a media processing platform programming interface (MPI) of a system control module to complete hardware initialization and allocate a video cache pool;
step two: calling a VI module to create video input equipment and a video physical channel and setting parameters;
step three: calling a VPSS module to create a group and a channel, setting parameters of the group and the channel, and outputting video data with expected resolution;
step four: calling a VENC module to perform H.265 compression coding on the YUV original image to obtain an H.265 format code stream;
step five: obtaining the information of each frame of image according to the H.265 format code stream, wherein the size of one frame of image does not exceed 65535, and the key frame identifier is 1 or 0;
step six: unpacking the image frame according to the frame information, and specifying that the size of each packet is not more than 61, the number of the packets in each image is not more than 255, the serial number of each packet is not more than 255 and compressing image data, so as to ensure that the quantity of the compressed image data sent by each packet is constant;
step seven: after unpacking, grouping the key frame packet and the common frame packet, and then putting the key frame packet and the common frame packet into a cache for output;
the working process of the image cache RS485 output module is as follows:
the method comprises the following steps: after receiving the request instruction of the upper computer, the FPGA of the programmable logic device checks whether video compression data exist in a cache or not and judges and processes: if the cache has video compression data, sending the video compression data to the upper computer through RS485, and if the cache does not have the video compression data, sending the effective data bits to the upper computer through RS485 after zero padding;
step two: after the data are sent, analyzing routing information according to the request instruction of the upper computer, and outputting the routing information of the image acquisition module to the image compression module through an IO port of the FPGA chip;
step three: after receiving the route selection information of the image acquisition module, the image compression module performs image compression on the image output by one of the image acquisition modules;
step four: the image compression module sends the video compression data in the cache to an image cache RS485 output module in an SPI bus mode;
step five: the image cache RS485 output module receives the video compression data in an SPI bus mode, stores the video compression data into a cache, and outputs the video compression data to an upper computer through an RS485 bus after waiting for a request instruction of the upper computer;
and circulating the steps from the first step to the fifth step, and outputting the compressed image data to an upper computer through an image cache RS485 output module.
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