CN201238361Y

CN201238361Y - Video collection apparatus

Info

Publication number: CN201238361Y
Application number: CN 200820059958
Authority: CN
Inventors: 秦国锋
Original assignee: Tongji University
Current assignee: Tongji University
Priority date: 2008-06-19
Filing date: 2008-06-19
Publication date: 2009-05-13
Anticipated expiration: 2018-06-19

Abstract

The utility model pertains to a video capture device, comprising an analog-to-digital conversion chip, an EMS memory, an FPGA codec chip, and a CANBUS interface chip. The analog-to-digital conversion chip is connected with the FPGA codec chip through an I<2>C bus; the EMS memory is connected with the FPGA codec chip through a data bus and an address bus, and the CANBUS interface chip is connected with the FPGA codec chip through a CANBUS bus. Compared with the prior art, the utility model is better suitable for the wireless mobile real-time monitoring in intelligent transportation and other industries.

Description

A kind of video acquisition device

Technical field

The utility model relates to collection of video signal, particularly relates to a kind of video acquisition device.

Background technology

At present, the video camera head unit is arranged on the market, can be connected with television set by the Video interface and carry out the fixing wired supervision of short distance, do not possess the data communication interface of CANBUS bus, thereby can not be applicable to wireless mobile real-time monitoring of industries such as intelligent transportation.

Summary of the invention

Technical problem to be solved in the utility model is exactly to provide a kind of video acquisition device for the defective that overcomes above-mentioned prior art existence.

The purpose of this utility model can be achieved through the following technical solutions: a kind of video acquisition device is characterized in that comprise modulus conversion chip, internal memory, FPGA codec chip, CANBUS interface chip, described modulus conversion chip passes through I ²The C bus is connected with the FPGA codec chip, and described internal memory is connected with the FPGA codec chip by data/address bus and address bus, and described CANBUS interface chip is connected with the FPGA codec chip by the CANBUS bus.

Described modulus conversion chip is the SAA7713H chip.

Save as asynchronous static memory in described.

Described FPGA codec chip is the EP2C20 chip.

Described CANBUS interface chip is the SN65HVD2 chip.

Compared with prior art, the utility model can well be applicable to wireless mobile real-time monitoring of industries such as intelligent transportation.

Description of drawings

Fig. 1 is a structural representation of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing.

As shown in Figure 1, a kind of video acquisition device comprises modulus conversion chip 1, internal memory 2, FPGA codec chip 3, CANBUS interface chip 4, and described modulus conversion chip 1 passes through I ²The C bus is connected with FPGA codec chip 3, and described internal memory 2 is connected with FPGA codec chip 3 by data/address bus and address bus, and described CANBUS interface chip 4 is connected with FPGA codec chip 3 by the CANBUS bus.

I ²C (Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus by the exploitation of PHILIPS company, is used to connect microcontroller and ancillary equipment thereof; FPGA (Field-Programmable Gate Array) is a field programmable gate array; CANBUS (ControllerAreaNetwork-BUS) is the LAN bussing technique.

Described modulus conversion chip 1 adopts the SAA7713H chip; Described internal memory 2 adopts asynchronous static memory; Described FPGA codec chip 3 adopts the EP2C20 chip; Described CANBUS interface chip 4 adopts the SN65HVD2 chip.

Video frequency pick-up head is connected with modulus conversion chip 1 of the present utility model through the Video interface, video frequency pick-up head is gathered video information with the resolution of 300K pixel and the speed of 5 frames/s, signal is adopted into harvester of the present utility model by A V interface, modulus conversion chip 1 is converted to nine position digital signals with the video analog signal of gathering, FPGA codec chip 3 inner nine position digital signals that use interface module to gather 1 output of progressive die number conversion chip, carry out JPEG or MPEG4 compression by FPGA codec chip 3 then, form the compressed encoding stream of 16 system vision signals, export 16 system compressed video streams in real time by CANBUS interface chip 4.MPEG4 is standby compression algorithm because: the compression ratio of JPEG roughly at 10:1 between the 40:1, and consider that practical application is in road monitoring, image change is fairly simple, compression ratio is higher, is feasible near compression ratio is taken at intermediate value, and we get 20:1 here.The per second data that should transmit are like this: 300K*8*5*0.05=0.6M less than the CAN bus width, meets the demands.Should suitably reduce resolution and frame per second if will insert more camera.

Wherein, outside modulus conversion chip 1 receives source data from video frequency pick-up head, therefrom extract luminance component, all luminance components are deposited in the internal memory 2 with the 8x8 block size, stop to extract after having deposited a two field picture, next will read from sram with the tactic brightness data of piece, the JPEG coding unit of delivering to FPGA codec chip 3 carries out the JPEG compression; After the data in the internal memory 2 are all read, again open and write internal memory 2 operations, repeat said process, in this course, when the unit of the coding unit in the FPGA codec chip 3 or its back has little time deal with data, to suspend reading of data from internal memory 2, up to allowing sense data just to begin to continue to read next data.

The basic demand of video signal collective and compressed video stream output interface is:

(1) video acquisition part: video signal collective uses the SAA7713H chip of NXP that video analog signal is converted to 9 position digital signals from the AV signal of camera output.In FPGA inside, use the interface module collection to advance 9 position digital signals of SAA7713H output.

(2) interface data transmission part: the data transfer mode of employing is by the CANBUS bus, and the bus protocol layer can realize that the outside only needs an electrical equipment isolating chip by can interface.Hardware circuit solution 1Mbps.

Claims

1. a video acquisition device is characterized in that, comprises modulus conversion chip, internal memory, FPGA codec chip, CANBUS interface chip, and described modulus conversion chip passes through I ²The C bus is connected with the FPGA codec chip, and described internal memory is connected with the FPGA codec chip by data/address bus and address bus, and described CANBUS interface chip is connected with the FPGA codec chip by the CANBUS bus.

2. a kind of video acquisition device according to claim 1 is characterized in that, described modulus conversion chip is the SAA7713H chip.

3. a kind of video acquisition device according to claim 1 is characterized in that, saves as asynchronous static memory in described.

4. a kind of video acquisition device according to claim 1 is characterized in that, described FPGA codec chip is the EP2C20 chip.

5. a kind of video acquisition device according to claim 1 is characterized in that, described CANBUS interface chip is the SN65HVD2 chip.