CN202334758U

CN202334758U - Wireless image collecting system based on FPGA (Field Programmable Gate Array)

Info

Publication number: CN202334758U
Application number: CN2011204760640U
Authority: CN
Inventors: 袁浩浩; 郭红霞; 周坚和
Original assignee: Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology
Priority date: 2011-11-25
Filing date: 2011-11-25
Publication date: 2012-07-11
Anticipated expiration: 2021-11-25

Abstract

The utility model provides a wireless image collecting system based on an FPGA (Field Programmable Gate Array) and relates to an image collecting system. The wireless image collecting system comprises an image collecting module and an FPGA control processing module, wherein the FPGA control processing module comprises a data input-output control module and a network data transmission module; the network data transmission module comprises an Ethernet interface controller and a JTAG (Joint Test Action Group) interface; the input interface of the data input-output control module is connected with the image collecting module, and the output interface of the data input-output control module is respectively connected with the input interfaces of the Ethernet interface controller, an SRAM (Static Random Access Memory) I and an STAM II; the output interfaces of the SRAM I and the SRAM II are connected with the input interface of the data input-output control module; and the Ethernet interface controller is connected with the input interfaces and output interfaces of the data input-output control module and a wireless local area network card. By utilizing the wireless image collecting system disclosed by the utility model, image data is received and transmitted completely, accurately, stably and rapidly in a wireless manner. The wireless image collecting system disclosed by the utility model is suitable for complex systems, such as an embedded type system, and further has the advantages of small volume and low power consumption.

Description

Radio image collecting system based on FPGA

Technical field

The utility model relates to a kind of image capturing system, particularly a kind of radio image collecting system based on FPGA.

Background technology

Along with developing rapidly of computer, network transmission technology and the communication technology, the transmission of wireless long-distance video has become a kind of trend, fields such as this technology has been used in remote monitoring gradually, takes photo by plane in the air, videoconference.The video monitoring system that adopts at present is generally: the imageing sensor camera that uses high imaging quality; Through S-VIDEO terminal real-time transmission data; This system needs camera and collecting device line, and Surveillance center also will have bigger memory space to come memory image and video segment simultaneously, and the real-time of this system is high; But energy consumption is big, cost is high, therefore only is suitable for the security protection and the monitoring of public place.And become suitable selection with characteristics such as its low-power consumption, restructurals based on the radio image collecting system of FPGA.Use under the ripe situation at wireless protocols; The center of gravity of research is the hardware platform that imageing sensor adopts and the processing of data flow; Present major programme has two kinds: 1. DSP+FPGA; Accomplish storage and preliminary treatment work by FPGA, utilize the high speed processing ability of dsp chip that image is compressed and relevant treatment, this scheme needing to be suitable for data parallel to handle and the jpeg data of more numerical operation flows; 2. FPGA+ coding and decoding video chip utilizes the parallel processing capability of FPGA to transmit and handle multiple series of images and video data simultaneously, because the hardware reconfigurability of FPGA, this scheme is suitable for the experimental stage.Therefore, above-mentioned two kinds of schemes all are not suitable for to network, data communication, Embedded complication system.

Summary of the invention

The technical problem that the utility model will solve is: a kind of radio image collecting system based on FPGA is provided, and the above-mentioned energy consumption that prior art exists is big, cost is high to solve, be not suitable for network, the weak point of data communication, embedded complication system.

The technical scheme that solves the problems of the technologies described above is: a kind of radio image collecting system based on FPGA; This system comprises that (FPGA is the abbreviation of Field-Programmable Gate Array for image capture module and FPGA control treatment module; Be field programmable gate array); Described FPGA control treatment module comprises data input/output control module and network data transmission module, and the network data transmission module comprises ethernet controller and jtag interface (JTAG is the abbreviation of Joint Test Action Group) again; The input interface of described data input/output control module is connected with image capture module with synchronous and control bus through image data bus; The output interface of data input/output control module is connected with the ethernet controller input interface of network data transmission module through data/address bus; Also be connected (abbreviation that SRAM is Static RAM) through the memory SRAM I outside address bus and control bus and the sheet and the input interface of memory SRAM II respectively, the output interface of memory SRAM I and memory SRAM II is connected through the input interface of data/address bus with the data input/output control module; The input/output interface of described ethernet controller is connected with the input/output interface of data input/output control module through control bus, also connects with the input/output interface of the wireless network card that is connected host computer.

The further technical scheme of the utility model is: the FPGA device that described FPGA control treatment module adopts is a Spartan-3 FPGA device.

The further technical scheme of the utility model is: described image capture module is cmos image sensor (CMOS is the abbreviation of Complementary Metal Oxide Semiconductor).

Owing to adopt said structure, the utility model based on the radio image collecting system of FPGA compared with prior art, have following beneficial effect:

1, power consumption is little, cost is low:

The utility model is a kind of radio image collecting system based on FPGA, because FPGA has characteristics such as low-power consumption, reconfigurability, therefore; The utility model with use the imageing sensor camera, compare through the video monitoring system of S-VIDEO terminal real-time transmission data; Do not need camera and collecting device line, and Surveillance center need not bigger memory space and comes memory image and video segment, therefore; The volume and the power consumption of the utility model are less, and cost is lower.

2, can realize the radio transmission-receiving function of view data complete, accurate, stable, apace:

Because the utility model is in the memory SRAM I and memory SRAM II that under based on the control of the input/output control module of FPGA, the data that collect is alternately deposited in outside the sheet; Therefore; Native system can be realized the continuous acquisition of view data, has guaranteed the integrality of view data; And the utility model also in the FPGA indoor design ethernet controller, realized the function of view data through the wireless network card transmission.

In addition; Because the FPGA device in the native system is the Spartan-3 series of products; Make die size dwindle 80% than existing FPGA device; Digitlization impedance match technique in the sheet and less output current able to programme (from 2 milliamperes to 24 milliamperes) make entire system power be merely 32 soft nuclears of flush bonding processor of MicroBlaze of the embedded IBM of the having internal bus technology of tens milliwatt Spartan-3 Series FPGA; This soft nuclear has the command system of 32 bit wides, supports that three operands and two kinds of addressing systems can be compatible fully with the OPB bus of IBM, and system passes through OPB bus and ethernet physical layer chip interconnect under the control of soft nuclear.

Therefore, the utility model under normal operation, wireless communication module can be realized the radio transmission-receiving function of view data complete, accurate, stable, apace, is very suitable for network, data communication, Embedded complication system.

Below, in conjunction with accompanying drawing and embodiment the technical characterictic based on the radio image collecting system of FPGA of the utility model is further described.

Description of drawings

Fig. 1: the system block diagram based on the radio image collecting system of FPGA of the utility model;

In above-mentioned accompanying drawing, each description of reference numerals is following:

The 1-image capture module, the 2-FPGA control treatment module, 21-data input/output control module,

22-network data transmission module, the 221-ethernet controller, the 222-JTAG interface,

The 3-wireless network card, 4-memory SRAM I, 5-memory SRAM II.

Embodiment

Embodiment one:

The disclosed radio image collecting system that is a kind of based on FPGA among Fig. 1, this system mainly is the collection site picture signal, and the view data that is collected is real-time transmitted to host computer through Ethernet, can receive the director data of host computer simultaneously.This system comprises image capture module 1 and FPGA control treatment module 2; Described image capture module 1 is a cmos image sensor; Described FPGA control treatment module 2 comprises data input/output control module 21 and network data transmission module 22, and network data transmission module 22 comprises ethernet controller 221 and jtag interface 222 again; The FPGA device that described FPGA control treatment module 2 adopts is a Spartan-3 FPGA device; The input interface of described data input/output control module 21 is connected with image capture module 1 with synchronous and control bus through image data bus; The output interface of data input/output control module 21 is connected with ethernet controller 221 input interfaces of network data transmission module 22 through data/address bus; Also be connected through the memory SRAM I 4 outside address bus and control bus and the sheet and the input interface of memory SRAM II 5 respectively, the output interface of memory SRAM I 4 and memory SRAM II 5 is connected through the input interface of data/address bus with data input/output control module 21; The input/output interface of described ethernet controller 221 is connected with the input/output interface of data input/output control module 21 through control bus, also connects with the input/output interface of the wireless network card that is connected host computer 3.

Native system is a requirement of real time; Storage adopts the high-speed SRAM switch mode; I.e. " ping pong scheme "; Idiographic flow is following: image data stream passes through the data input/output control module 21 equal time ground of FPGA control treatment module 2 with among distribution of flows to the two memory SRAM, in first cycle, will import metadata cache in memory SRAM I 4; Data are deposited in the memory SRAM II 5 through the input traffic selected cell at second period; Simultaneously the data in first cycle of buffer memory in the memory SRAM I 4 are delivered to subsequent module through output data selection unit, the 3rd cycle will be imported metadata cache in memory SRAM I 4 through the input traffic selected cell, will go up simultaneously that the data in the memory SRAM II 5 output to subsequent module through output data selection unit in one-period.So repeatedly, can realize the seamless buffering of data, guarantee the integrality of view data.

Claims

1. radio image collecting system based on FPGA; It is characterized in that: this system comprises image capture module (1) and FPGA control treatment module (2); Described FPGA control treatment module (2) comprises data input/output control module (21) and network data transmission module (22), and network data transmission module (22) comprises ethernet controller (221) and jtag interface (222) again; The input interface of described data input/output control module (21) is connected with image capture module (1) with synchronous and control bus through image data bus; The output interface of data input/output control module (21) is connected with ethernet controller (221) input interface of network data transmission module (22) through data/address bus; Also be connected through the memory SRAM I (4) outside address bus and control bus and the sheet and the input interface of memory SRAM II (5) respectively, the output interface of memory SRAM I (4) and memory SRAM II (5) is connected through the input interface of data/address bus with data input/output control module (21); The input/output interface of described ethernet controller (221) is connected with the input/output interface of data input/output control module (21) through control bus, also connects with the input/output interface of the wireless network card that is connected host computer (3).

2. the radio image collecting system based on FPGA according to claim 1 is characterized in that: the FPGA device that described FPGA control treatment module (2) is adopted is a Spartan-3 FPGA device.

3. the radio image collecting system based on FPGA according to claim 1 and 2 is characterized in that: described image capture module (1) is a cmos image sensor.