CN202940909U

CN202940909U - Double-transmission mode monitoring device based on DSP and FPGA

Info

Publication number: CN202940909U
Application number: CN 201220599094
Authority: CN
Inventors: 郭峻因
Original assignee: CHENGDU JIANGFA TECHNOLOGY Co Ltd
Current assignee: CHENGDU JIANGFA TECHNOLOGY Co Ltd
Priority date: 2012-11-14
Filing date: 2012-11-14
Publication date: 2013-05-15
Anticipated expiration: 2022-11-14

Abstract

The utility model relates to the field of security and protection technology and provides a double-transmission mode monitoring device based on DSP and FPGA. The device comprises a COMS digital image sensor, an FPGA chip, a DSP processing chip, a video D/A output chip, a first GPRS module, a second GPRS module, a monitoring and displaying terminal and a dual-port RAM, wherein the COMS digital image sensor, the FPGA chip, the video D/A output chip and the first GPRS module are successively connected, the second GPRS module is connected with the monitoring and displaying terminal, the first GPRS module and the second GPRS module exchange data through a GPRS network, and a DSP processor is connected with the FPGA chip through the dual-port RAM; and the device further comprises a CAN bus controller SHA1000 and a CAN bus, wherein the CAN bus controller is connected with the FPGA chip and the CAN bus, and the CAN bus is connected with the monitoring and displaying terminal.

Description

A kind of two transmission means supervising devices based on DSP and FPGA

Technical field

The utility model relates to safety-security area, and a kind of two transmission means supervising devices based on DSP and FPGA are provided.

Background technology

At home and abroad on market, video monitoring apparatus will have two kinds: a kind of is analog video at present, and a kind of is digital video.The former technology maturation is widely used, and owing to being analog signal, is unfavorable for that therefore doing follow-up image/video processes, and is not inconsistent with the direction of national digital development; The latter is developed rapidly, and flexibility is high, owing to being digital signal, being very beneficial for doing all kinds of image/videos and processing, as motion detection, recognition of face, target following etc.The quality of video acquisition quality will directly affect the operation of whole system, be the precondition of carrying out follow-up Digital Image Processing.Therefore, high performance hardware device and high-quality algorithm must be arranged as the basis, real time video collection just becomes possibility.The utility model provides a kind of embedded video monitoring system device based on FPGA+DSP.This system has that volume is little, and cost is low, and is low in energy consumption, and speed is fast, and adaptable characteristics can be completed the collection of video, real-time Video processing, and the transmission of data.

The utility model content

The purpose of this utility model is to provide that a kind of real-time is good, volume is little, cost is low, low in energy consumption, strong adaptability, can realize a kind of two transmission means supervising devices based on DSP and FPGA of the function that video acquisition, transmission of video, video show.

The utility model is for achieving the above object by the following technical solutions:

a kind of two transmission means supervising devices based on DSP and FPGA, it is characterized in that: comprise the COMS digital image sensor, fpga chip DSP process chip, the video d/a pio chip, the one GPRS module, the 2nd GPRS module, the monitoring display terminal, dual port RAM, described COMS digital image sensor, fpga chip, the D/A pio chip, the one GPRS sequence of modules connects, the 2nd GPRS module connects the monitoring display terminal, the one GPRS module and the 2nd GPRS module are carried out data interaction by GPRS network, described dsp processor connects fpga chip by dual port RAM, described fpga chip is connected with frame and deposits DRAM, data storage SD card, described DSP process chip is connected with SDRAM, Flash, jtag interface, also comprise CAN bus control unit SHA1000, the CAN bus, described CAN bus control unit connects fpga chip and CAN bus, described CAN bus connects the monitoring display terminal.

Described fpga chip adopts the EPIC12Q240C8 model.

Described DSP process chip adopts model TMS320V5502.

Because the utility model adopts above technical scheme, so possess following beneficial effect, real-time is good, volume is little, cost is low, low in energy consumption, strong adaptability, can realize the function that video acquisition, transmission of video, video show, and the utility model adopts the wire and wireless transmission means, and reliability is strong.

Description of drawings

Fig. 1 is system block diagram of the present utility model.

Embodiment

the utility model provides a kind of two transmission means supervising devices based on DSP and FPGA, comprises that its model is MT9M011 for the COMS digital image sensor that gathers video data, the fpga chip EPIC12Q240C8 of the speed buffering of the collection of responsible image, image demonstration, image storage, data and the logic control of whole circuit, frame as data storage is deposited DRAM, and its model is HY57V643220DT-7, its model of video d/a pio chip is ADV7123KSTl40, adopt the Y7C025AV-15AI chip, as the dual port RAM of fpga chip EPIC12Q240C8 to the buffering of the high-speed data of dsp chip TMS320V5502, be used for the data storages SD card of storing image data, mainly be responsible for carrying out the dsp chip TMS320V5502 of the compression of still image, adopt the FLASH of ST39VF400A chip, as data storage, its model is the DRAM of HY57V643220DT-7, be used for the data storages SD card of storing image data, be used for the video data that collects is arrived the GPRS module of monitoring display terminal by wireless network transmissions, the overall work process of system is as follows: at first image capture module is controlled COMS, with the speed of 25 frames/s to FPGA transport picture data, control by FPGA makes in the SDRAM that is buffered in outside sheet, and control ADV7123 has accomplished the demonstration of real-time image.Then, after selecting compact model by the user, FPGA opens the data high-speed buffer channel by logic control, and view data is moved to the speed buffering module from the frame storing module, DSP reads the view data in dual port RAM efficiently by the mode of EMIF interface outer extension memory.At last, view data is carried out compression in DSP inside, in an identical manner by the speed buffering module, data is passed to the storage control module of FPGA, the SD card storage of compressing image data perhaps sends the video data that collects to the monitoring display terminal by GPRS module or CAN bus.

Claims

1. two transmission means supervising devices based on DSP and FPGA, it is characterized in that: comprise the COMS digital image sensor, fpga chip DSP process chip, the video d/a pio chip, the one GPRS module, the 2nd GPRS module, the monitoring display terminal, dual port RAM, described COMS digital image sensor, fpga chip, the D/A pio chip, the one GPRS sequence of modules connects, the 2nd GPRS module connects the monitoring display terminal, the one GPRS module and the 2nd GPRS module are carried out data interaction by GPRS network, described dsp processor connects fpga chip by dual port RAM, described fpga chip is connected with frame and deposits DRAM, data storage SD card, described DSP process chip is connected with SDRAM, Flash, jtag interface, also comprise CAN bus control unit SHA1000, the CAN bus, described CAN bus control unit connects fpga chip and CAN bus, described CAN bus connects the monitoring display terminal.

2. a kind of two transmission means supervising devices based on DSP and FPGA according to claim 1, is characterized in that: described fpga chip employing EPIC12Q240C8 model.

3. a kind of two transmission means supervising devices based on DSP and FPGA according to claim 1, is characterized in that: described DSP process chip employing model TMS320V5502.