CN105911454B - A kind of Modularized digital integrated circuit radiation effect Online Transaction Processing and test method - Google Patents
A kind of Modularized digital integrated circuit radiation effect Online Transaction Processing and test method Download PDFInfo
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- CN105911454B CN105911454B CN201610240286.XA CN201610240286A CN105911454B CN 105911454 B CN105911454 B CN 105911454B CN 201610240286 A CN201610240286 A CN 201610240286A CN 105911454 B CN105911454 B CN 105911454B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The present invention relates to a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing and test methods, on the basis of summarizing the existing digital integrated electronic circuit radiation effect Online Transaction Processing similarities and differences, by effect test needed for various functions circuit be divided into relatively independent module, the electrical and mechanical connection of each intermodule, design in module, mechanical structure of system board etc. uses existing industrial standard, to realize that commercial module or the module fast construction of independent development can be used in system, with better scalability, to save the design time and cost of hardware.It can be used for most of radiation effect on-line testings for playing star digital integrated electronic circuit.System is to promoting the standardization of this state's radiation effect Online Transaction Processing also to play an important roll.
Description
Technical field
The present invention relates to the test of digital integrated electronic circuit radiation effect more particularly to a kind of Modularized digital integrated circuit spokes
Penetrate effect Online Transaction Processing.
Background technology
The natural radiation environment and nuclear radiation environment in space can generate accumulated dose, single-particle, neutron position in electronic device
Move and moment dose rate effect, so as to cause electronic device electrical parameter degeneration even disabler, seriously affect spacecraft and
The service life of strategic arms and reliability, it is therefore necessary to the electrical parameter in the radiative process that ground accurately measures electronic device and work(
It can change, to provide data for the evaluation of the radiation resistance of electronic device.
The radiation effect test of electronic device is divided into online and offline two kinds of test.Wherein on-line testing is mainly used in real time
The transient-radiation effect (such as single-particle, dose rate effect) of monitoring devices, or for steady state irradiation process (such as accumulated dose,
Neutron displacement effect etc.) in provide Radiation bias.Due to the particularity of radiation effect, existing commercial test measuring apparatus is difficult straight
It scoops out and is used for on-line testing, need on the basis of studying device radiation failure phenomenon and mechanism, to develop required radiation effect
Online Transaction Processing.
Digital integrated electronic circuit includes mainly memory, programmable logic array (FPGA), central processing unit (CPU), center
Controller (MCU) etc. is the most widely used device in current spacecraft and weaponry, the test of radiation effect
Method and measuring system also become it is domestic in recent years pay close attention to object.
Domestic existing measuring system at present mainly aims at certain type or the device of model develops radiation effect on-line testing
System, each development for testing system are required to more by hardware principle design, pcb board making, hardware debugging, software programming etc.
A link, but digital integrated electronic circuit type is various, and device production and application unit can face a variety of digital integrated electronic circuits simultaneously
Radiation effect testing requirement needs system developer's exploitation to cover test system, development amount according to existing method
Greatly, the time is long, of high cost, and an urgent demand, which is replaced, develops thinking, develops the radiation effect Online Transaction Processing with versatility.
By analysis, the accumulated dose of all kinds of large-scale digital ics, single-particle, neutron displacement effect on-line testing have
Point same as below is mainly：
(1) testing requirement is essentially identical.The total dose effect of digital integrated electronic circuit, the experiment of neutron displacement effect mainly need
It is that measured device (DUT) provides dynamic or static radiation biasing, and the crucial electricity ginsengs of DUT are monitored in irradiation process to test system
Number, such as the situation of change of static current of lcd.And single particle effect experiment needs the single event latchup (SEL), the single-particle that monitor DUT to turn over
Turn section (SEU), single event function interrupt (SEFI) cross-section, the test in the wherein sections SEL is the base monitored in real time in electric current
On plinth, latch-up protection and locking number statistics are realized, and the test of SEU, SEFI are the tests to DUT major functions.Therefore
The single particle effect of device tests system after solving the problems, such as the long-line transmission between measured device and test circuit, so that it may be used for
The test of accumulated dose, single particle effect.
(2) basic principle of different circuit function tests is identical.Either DSP or SRAM type FPGA device, radiation effect
The functional test basic principle answered is that required pumping signal is provided for DUT, the difference of monitoring output and desired value.
When facing specific measured device, the difference between different components is mainly shown as：(1) number of power sources and voltage is not
Together；(2) quantity of pumping signal, sequential, frequency are different；(3) the radiation effect result processing method of difference DUT is different.
Therefore the radiation effect on-line testing of variety classes digital integrated electronic circuit is identical on the whole, but detail
Difference, these differences can be overcome with design of hardware and software, this allows for developing the integrated circuit spoke with stronger versatility
Penetrating effect Online Transaction Processing technically has very strong feasibility.
In addition, due to the country to the radiation effect test method of all kinds of digital integrated electronic circuits have not yet been formed unified understanding and
Specification, the measuring system of commensurate's exploitation is not far from each other, and acquired radiation resistance test data is caused without comparativity
The a large amount of wasting of resources proposes requirement to the standardization and standardization of testing system.In this case, radiation effect is online
The quantity of test system and classification are fewer, and the work of standardization is more conducive to carry out and promote, therefore radiation effect on-line testing
Also there is an urgent need to develop the radiation effect Online Transaction Processing with versatility for the standardization work of system.
Invention content
In order to solve the technical problem present in background technology, the present invention is in research digital integrated electronic circuit radiation effect damage
Mechanism is analysed in depth and summarizes all kinds of large-scale digital ic accumulated doses, single-particle, neutron displacement effect on-line testing
On the basis of the similarities and differences, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing and test method are provided.
The technical solution adopted by the present invention is as follows：
A kind of Modularized digital integrated circuit radiation effect Online Transaction Processing of present invention offer, including remote computer,
Local computer and irradiation plate, the local computer are not illuminated, are characterized in that：
The local computer is a kind of computer running embedded OS, including a main control module, extremely
A few analog I/O module and at least one power module；
The remote computer realizes the control to local computer, the main control module by Desktop Share and Ethernet
It is in communication with each other respectively with analog I/O module and power module by bus between plate, the analog I/O module passes through signal cable and quilt
It surveys device irradiation plate to be in communication with each other, the power module is connect by feed cable with irradiation plate；
The main control module undertakes following functions：
D. it is responsible for making the mutually coordinated work of modules in local computer, realizes and the radiation effect of measured device is surveyed
Examination；
E. it is responsible for the processing, preservation and display to radiation effect data；
F. it is responsible for realizing display interface, preserves data and the teleengineering support with host computer；
D. embedded OS is run；
The analog I/O module provides required multi-channel drive signal for circuit-under-test, and compare the output of circuit-under-test with
The difference of desired value, then generation system interrupts or caches detailed data when variant, waits for the reading of main control module；Multichannel
Direction, level, clock and the online real-time, tunable of sequential of drive signal；
The power module provides required voltage for circuit-under-test, the monitoring of line output voltage of going forward side by side, static current of lcd, and
Has current protecting function.
It is the basic structure of the present invention above, is based on the basic structure, the present invention also makes following optimization and limits：
Above-mentioned analog I/O module includes bus interface, clock circuit, test vector memory, program and data storage between plate
Device, I/O port level and direction adjustment circuit and master control FPGA；
The master control FPGA by the way that bus is in communication with each other between bus interface and plate between plate, the master control FPGA respectively with test
Vector memory, program and data storage are in communication with each other, and the master control FPGA passes through I/O port level and direction adjustment circuit
It is in communication with each other with measured device irradiation plate；The master control FPGA is connect with clock circuit；
Bus interface mainly realizes the conversion between local bus in intermodule transfer bus and analog I/O module between the plate,
The data exchange interface of one standard is provided for the communication of master control FPGA and intermodule bus；
The clock circuit is mainly made of local bus clock, FPGA master clocks and I/O signal clock three parts；It is described
Local bus clock is divided into two-way and is respectively supplied to bus interface between master control FPGA and plate；FPGA master clocks are supplied to master control
FPGA, master control FPGA access the clock of test vector memory, data and program storage with this clock；The I/O signal
The frequency of clock is adjustable online, the clock for adjusting I/O signal in real time, to meet the needs of different circuit-under-test test frequencies,
It controls signal and is generated by master control FPGA, in generated clock signal input to master control FPGA；
The test vector memory is mainly used for storing the test vector of I/O channel, is made of 2 RAM, a piece of conduct
The input vector memory of DUT, another is used as expected value vector memory；
Described program and data storage when Embeded CPU core in master control FPGA as program storage and data for depositing
Reservoir；
The level and direction of the I/O port level and direction adjustment circuit for the online I/O port of adjustment in real time, make number
The output I/O signal level of I/O module is consistent with the incoming level of circuit-under-test, and analog I/O module input signal is with master control FPGA's
Incoming level is consistent, to realize the compatibility to varying level measured device；
The master control FPGA is responsible for data exchange Bus Interface Chip between, receive order that main control module is sent out and
Data realize the test sequence of measured device, control other circuits on analog I/O module.
To realize the measurement of the radiation effect under different mode, three kinds of circuits are can configure in master control FPGA of the present invention：
(1) universal circuit：Include local bus interface in FPGA, IO clock controls, IO level controls, DUT is controlled and is surveyed
Swab circuit, it includes that DUT drivings generate, DUT outputs monitor, three portions of DUT signal distribution that the DUT controls are main with test
Point；Except DUT is controlled in addition to test sub-circuit, the designing user of other sub-circuits is inaccessible and changes；DUT is controlled and test
Circuit provides basic template, and interface can not be changed, and provides standard son electricity for SRAM, FLASH, SRAM type FPGA
Road；
The IO clock controls, the control of IO level, DUT drivings generate and DUT output monitorings are connect by local bus respectively
Mouth is connected bus interface between plate, and the output of the IO clock controls is connect with clock circuit, the input of the IO level control
Receive the measured power level signal from I/O port level and direction adjustment circuit, the output transmission level tune of the IO level control
Whole control signal is to I/O port level and direction adjustment circuit；The output that the DUT drivings generate is connected with DUT signal distribution,
The input of the DUT outputs monitoring is connected with DUT signal distribution；DUT signal distributes and I/O port level and direction adjustment circuit
Connection；
When configuring universal circuit, analog I/O module receives the data or life that main control module is issued from bus interface between plate
Enable, local bus in plate be converted to by the bus interface circuit in analog I/O module, in master control FPGA local bus interface then from
Local bus reception data or order, and these data or order are specified according to write-in after the address information decoding in bus
In trigger；The process that data are uploaded to main control module is opposite with this process；
(2) CPU core circuit：The circuit is the stone in FPGA is embedded in soft core or utilizes FPGA, and local bus connects
Mouth, IO clock controls, the control of IO level, program and data memory interface, DUT are controlled and the sub-circuits such as test are all with standard IP
The form of core is articulated in the bus of the CPU core；
When configuring the circuit, when local bus interface receives data or the order of main control module transmission, with interruption
CPU core is informed in formation, then data distribution is given to specified circuit by CPU core；The passback process of its data is in contrast；
(3) circuit based on test vector：The circuit has used the test vector memory on analog I/O module, surveys at this time
The two panels RAM in vector memory is tried, a piece of input vector memory, another conduct expected value vector as DUT stores
Device；The value of output vector memory comes from two kinds of situations, and one is being write direct by main control module, one is in radiation effect
Before experiment, the DUT output signals of actual samples are written；
Include local bus interface, IO clock controls, the control of IO level, wrong data buffer, output in master control FPGA
Comparator, DUT signal distribution, FIFO1 and FIFO2；The IO clock controls, the control of IO level, wrong data buffer pass through
Bus interface connects between local bus interface and plate, and the output end of the IO clock controls is connect with clock circuit, the IO electricity
The input of flat control receives the measured power level signal from I/O port level and direction adjustment circuit, and the IO level controls defeated
The whole control signal of power transmission of setting out Heibei provincial opera is to I/O port level and direction adjustment circuit；
The FIFO1 is connect with expected value vector memory, and the FIFO2 is connect with input vector memory, described
FIFO1 and FIFO2 are also connect with local bus interface；The FIFO1 and FIFO2 also receives the IO clocks from clock circuit；
The input of the output end and output comparator of the FIFO1 connects, output end and the DUT signal point of the FIFO2
The input connection matched, the output of DUT signal distribution and the input of comparator connect, DUT signal distribution and I/O port level and side
It is connected to adjustment circuit；
In use, user determines content, vector length and the output frequency of test vector memory before radiation effect is tested
Rate when experiment, test vector is sequential read out from test vector memory and is stored in FIFO, if output vector number reaches vector
When length, then returns to first vector and continue to output vector successively, until receiving test END instruction；FIFO receives data
Afterwards, then it is sequentially output according to set vectorial output frequency；
IO clock controls and IO level control circuits in master control FPGA for generate the outer I/O port level of master control FPGA and
Control sequential needed for the adjustment circuit of direction；It is mainly that DUT provides required input signal that DUT drivings, which generate,；DUT output monitorings
It is mainly used for comparing DUT output valves and desired value, when the two difference, statistics overturning number, and the details of mistake are pressed into
In fifo buffer, the access of main control module is waited for；DUT signal distribution setting DUT is inputted, output signal and specific IO are logical
The correspondence in road.Above-mentioned I/O port level adjusting circuit include export adjustable linear voltage regulator, digital regulation resistance, ADC and
Level translator, digital regulation resistance adjust resistance as the output voltage of linear voltage regulator, and the output voltage of linear voltage regulator is
Level translator connect the supply voltage surveyed with tested DUT；
When needing to adjust level, master control FPGA generates the control signal of digital regulation resistance, adjusts the resistance of digital regulation resistance,
To the output voltage of linear adjustment voltage-stablizer, ADC acquires output voltage values under master control FPGA controls, and master control FPGA passes through not
Disconnected adjustment digital regulation resistance resistance value, and measurement voltage value and desired voltage values are compared, realize the closed-loop control to output voltage.
Above-mentioned power module is made of power supply master control FPGA, electric current and electric voltage observation circuit and DUT power supplys,
The DUT power supplys include multiple identical power channels, and each channel includes linear voltage regulator, digital current potential
Device, current amplifier and power switch；
The output of the linear voltage regulator can pass through the adjustable realization output voltage of external digital regulation resistance resistance value
Adjustment；The current amplifier is that small resistance is concatenated on the output line of linear voltage regulator, and the electricity of high cmrr is used in combination
Stream amplifier converts electrical current into voltage；The power switch is for controlling whether power channel exports；
The electric current and electric voltage observation circuit core are analog-digital converter, for converting the voltage of every road power supply, electric current
For digital quantity；
The power supply master control FPGA has following function：
(1) it is used to adjust the resistance of digital regulation resistance；
(2) control sequential for providing ADC devices makes ADC devices that can recycle conversion user in DUT irradiation process specified logical
Voltage, the electric current in road, and transformation result is read at any time；
(3) compared with carrying out electric current transformation result in real time with the value in current threshold register, when conversion value is more than electric current
When threshold value, linear voltage regulator shutdown signal is exported, closes corresponding power channel, and after awaiting a specified time, is made linear
Voltage-stablizer shutdown signal is invalid, keeps power channel output effective.
The control software of above-mentioned local computer uses modularized design, including main interface, power module setting interface, number
Interface, DUT control interfaces and display and data processing interface is arranged in word I/O module；
The main interface can freely call power module that interface is arranged, interface is arranged in analog I/O module, measured device controls,
Display and data processing interface；
Power module setting interface, analog I/O module setting interface are two basic interfaces, can be by other interface tune
With；
Power module setting interface is used to be arranged the required power channel of circuit-under-test test, supply voltage, locking
Current threshold, latch-up protection time；Open or off power channel；
Analog I/O module setting interface be used to be arranged or display system local computer in existing analog I/O module
State；
The digital circuit of the DUT control interfaces, display from data processing interface for different types has different boundaries
Face, control, display and data processing method depend on the specific radiation effect test method of measurand.
In order to reduce the difficulty of secondary system exploitation, the control software of local computer is provided in the way of dynamic link library
More than 50 a basic functions, the basic function can quickly develop DUT controls, display and data processing for specific circuit-under-test
Interface.
The present invention also provides a kind of Modularized digital integrated circuit radiation effect on-line testing method, special character exists
In：Include the following steps：
1) secondary system exploitation is carried out, step is：
1.1) according to the testing requirement of DUT, the circuit class in the master control FPGA of analog I/O module is determined
Type；1.2) DUT controls and test sub-circuit in modification master control FPGA；
1.3) modified circuit is subjected to comprehensive and placement-and-routing, and downloaded in master control FPGA；
1.4) control and data processing, display software interface are write for circuit-under-test；
1.5) debugging and verification experimental verification；
2) it uses system to carry out radiation effect to test, step includes：
2.1) according to circuit-under-test classification, the difference of local computer existing module quantity and module number needed for test is checked
Not, when number of modules deficiency, it is inserted into new module, when enough, is updated in the configuration memory in analog I/O module in master control FPGA
Hold；
2.2) system is connected, and ensures that local computer is not irradiated directly；
2.3) it opens system and controls main interface, setting circuit-under-test tests supply voltage and the progress of required power channel
Calibration；The latching current threshold value in channel and latch-up protection time needed for being arranged；The power channel needed for test is opened, checks irradiation
Whether on board supply voltage is normal；
2.4) check whether the circuit configured in master control FPGA in analog I/O module is suitable for circuit-under-test, if uncomfortable
With then return to step (2.1)；If there is extra analog I/O module, the institute for closing extra analog I/O module is functional；
2.5) system main interface opens corresponding circuit spoke automatically according to analog I/O module and power module configuring condition
Penetrate effect test interface；
2.6) setting circuit-under-test effect tests required register and parameter；
2.7) while starting irradiation, the radiation effect parameter testing of start circuit, until off-test.
Good effect possessed by the present invention：
1. the present invention is both needed to for domestic existing radiation effect Online Transaction Processing poor universality, different types of integrated circuit
The problem of a large amount of human and material resources develop new system again is expended, using modular thinking, is had developed a kind of more general
Digital integrated electronic circuit radiation effect Online Transaction Processing.Modularization refers to online in the existing digital integrated electronic circuit radiation effect of summary
On the basis of the test system similarities and differences, by effect test needed for various functions circuit be divided into relatively independent module, often
Electrical and the mechanical connection, the design in module, the mechanical structure of system board etc. of a intermodule use existing industrial standard,
To realize that commercial module or the module fast construction of independent development can be used in system, with better scalability, from
And save the design time and cost of hardware.It can be used for most of radiation effect on-line testings for playing star digital integrated electronic circuit.
System is to promoting the standardization of this state's radiation effect Online Transaction Processing also to play an important roll.
2, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing that the present invention develops, it is embedding using that can run
Enter the local computer of formula Windows operating system instead of in traditional effect Online Transaction Processing (basic framework is shown in Fig. 9)
Microcontroller or microprocessor.In this case, the exploitation of system need to only develop control software on the local computer, keep away
Exempt from not only to develop upper computer software in traditional effect Online Transaction Processing, but also the problem of exploitation slave computer software.In addition, local meter
Calculation machine function powerful avoids high-volume effect data but also effect test data can be stored in local computer nearby
Long-line transmission problem makes effect test more efficient.
3, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing for developing of the present invention can be used for accumulated dose,
In a variety of effect tests such as single-particle and neutron displacement effect.The design of system local computer consider as far as possible miniaturization,
Low-power consumption and heat dissipation problem make system in accumulated dose and neutron experiment, it is easier to it shields, it can in heavy ion single particle experiment
It works normally in the vacuum chamber.
4, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing that the present invention develops is existing compared to domestic
Radiation effect tests system, has a clear superiority, is mainly shown as in terms of versatility：(1) global design of system uses work
Industry working standard,；(2) system digits I/O module and power module reusable；(3) the IO level of analog I/O module, direction, frequency
Online adjustable, the generations of DUT input signals and output relatively etc. provide a variety of realization methods and basic templates；(4) power supply mould
The voltage of block is adjustable online, can in real time monitoring current, voltage, have current protecting function etc..
Description of the drawings
Fig. 1 is overall system architecture；
Fig. 2 is system digits I/O module theory of constitution block diagram；
Fig. 3 is analog I/O module master control FPGA internal circuit schematic diagrams --- configuration universal circuit；
Fig. 4 is analog I/O module master control FPGA internal circuit schematic diagrams --- configuration has the soft nuclear power roads CPU；
Fig. 5 is analog I/O module master control FPGA internal circuit schematic diagrams --- circuit of the configuration based on test vector；
Fig. 6 is power module theory of constitution block diagram；
Fig. 7 is secondary system development process；
Fig. 8 is system process for using；
Fig. 9 is that conventional digital integrates radiation effect test overall system architecture；
Figure 10 is the circuit diagram of analog I/O module IO level adjustment；Figure 11 be power module realize each channel current and
The flow of voltage monitoring.
Specific implementation mode
It elaborates to the present invention below in conjunction with attached drawing.
As shown in Figure 1, Modularized digital integrated circuit radiation effect Online Transaction Processing provided by the present invention, system master
It to be made of remote computer, local computer and irradiation plate three parts.Remote computer is realized by Desktop Share to local
The control of computer is connected between local computer and irradiation plate with short-term.When radiation effect is tested, local computer is placed on radiation
Source periphery does not configure display, and ensures not to be illuminated.Local computer running the small-sized of embedded OS to be a kind of
Change, low-power consumption computer.The computer is made of main control module, analog I/O module, power module and four generic module of special module,
The electrical and mechanical connection of intermodule uses PC104+/PC104 agreements.Main control module mainly undertakes following functions：A. it is responsible for making
The mutually coordinated work of modules in system is realized and is tested the radiation effect of measured device；B. it is responsible for large quantities of graded effect numbers
According to processing, preservation, display etc.；C. it is responsible for the teleengineering support realized display interface, preserve data and host computer.It can only in system
There is 1 main control module.Module can run WinXP embedded systems, and analog I/O module mainly provides institute for tested integrated circuit
The drive signal needed, and compare the output of circuit-under-test and the difference of desired value, then generation system interrupts or will when variant
Detailed data caches, and waits for the reading of main control module.
Existing commercial product can be selected in main control module, it is desirable that while with PC104+/PC104 interfaces, must also have
There is following feature：(1) XPE operating systems can be run；(2) with 100,000,000 or more network interface, with plate more than 2GB capacity
Paste solid state disk；(3) small, small power consumption is not required to fan cooling.It is recommended that the single-borad computer CM- of selection Ling Hua science and technology production
745。
1~3 analog I/O module can be installed as needed in system.Power module is responsible for needed for circuit-under-test offer
Voltage, the monitoring of line output voltage of going forward side by side, static current of lcd, and have current protecting function.It can install 1 in system as needed~
2 power modules.Special module is mainly used for still meeting the test of tested integrated circuit when the function of above three module
When demand, separately increased module.Analog I/O module can provide 64 tunnel directions, level, the online real-time, tunable of clock Digital I/O
Signal.As shown in Fig. 2, the module mainly by PC104 Plus bus interface, clock circuit, test vector memory, program and
The circuits such as data storage, I/O port level and direction adjustment circuit, master control FPGA form.PC104+ bus interface is mainly real
Existing conversion between PC104+ buses and local bus, the data that a standard is provided between master control FPGA and PC104+ bus are handed over
Alias；Clock circuit is mainly made of PC104+ interface clocks, FPGA master clocks and I/O signal clock three parts.PC104+ connects
Mouth clock is mainly that PC104+ bus interface provides clock, frequency 33MHz.FPGA master clocks are major design circuits in FPGA
Clock used, FPGA access the clock of test vector memory, data and program storage with this clock, in the present invention
Middle FPGA master clock frequencies are 125MHz.The frequency of I/O signal clock is online adjustable, for adjusting 64 tunnel I/O signals in real time
Clock, to meet the needs of different circuit-under-test test frequencies, the adjusting range of frequency is 1kHZ~100MHz；Test to
Amount memory is made of two 32 SDRAM, each in such 64 I/O channels has just corresponded to each of SDRAM
Position datawire.Storage depth depends on the capacity of SDRAM, if the capacity of SDRAM is 8M × 32bit, the vector of each IO is deposited
The depth of reservoir is 8Mb.As program storage when program and data storage are mainly used for the Embeded CPU core in master control FPGA
And data storage.The level and direction of I/O port level and direction adjustment circuit for the online I/O port of adjustment in real time, make number
The output I/O signal level of word I/O module is consistent with the incoming level of circuit-under-test, analog I/O module input signal and master control FPGA
Incoming level it is consistent, to realize to the compatibility of varying level measured device.The adjusting range of level is 1.2~5.0V.
Master control FPGA is the core of analog I/O module, it is responsible for the data exchange between PC104+ interfaces, receives master control
The test sequence of existing measured device is tested in the order and data that module is sent out, and controls upper other circuits etc. on analog I/O module.This
Invention devises three kinds of circuits for the ease of the secondary development of user in master control FPGA：
(1) universal circuit.When using the circuit, the vector memory on analog I/O module does not use, main in FPGA
Control and test including local PC104+ interfaces, the adjustment of IO clocks, the adjustment of IO level, program and data memory interface, DUT etc.
Sub-circuit (see Fig. 3).For ease of secondary development, except DUT is controlled in addition to test sub-circuit, the designing user of other sub-circuits can not
Access and change, DUT controls and the interface of test sub-circuit can not be changed, inside provides basic template, and be directed to SRAM,
FLASH, SRAM type FPGA provide standard sub-circuit.Local PC104+ interfaces are mainly realized between FPGA and PC104+ interface chips
Data exchange, decoding and access of control register etc.；Main realize of IO clocks adjustment generates chip to external IO clocks
Control；The adjustment of IO level is mainly adjusted by the resistance value of the outer digital regulation resistances of FPGA, realizes the adjustment of the ends DUT IO power levels,
And the level after external ADC devices actual measurement adjustment is controlled, realize the closed loop adjustment of IO level；Program and data memory interface master
Realize the control to external SDRAM and access, when FPGA internal storage capacity is inadequate, external memory is as supplement；
It includes that DUT drivings generate, DUT outputs monitor, DUT signal three subprograms of distribution that DUT, which is controlled main with test,.DUT driving productions
Raw is mainly input signal of the DUT offers as needed for address, clock, Read-write Catrol etc.；DUT output monitorings are mainly used for comparing
DUT output valves and desired value, the statistics overturning number when the two difference, and the details of mistake are pressed into fifo buffer
(FIFO) in, the access of main control module is waited for；It is logical to state DUT signal distribution mainly setting DUT inputs, output signal and specific IO
The correspondence in road.Universal circuit can support the secondary development of most of digital integrated electronic circuit radiation effect on-line testing, but
It needs the secondary development person of system to write the controller of circuit-under-test using hardware program language such as VHDL or Verilog, develops
Period difficulty is larger, is suitable for the digital integrated electronic circuit test of complex time.
(2) there is the soft nuclear power roads CPU.When using the circuit, the vector memory on analog I/O module does not use.The circuit
It is to be embedded in the soft cores of MicroBlaze in FPGA, other circuits, such as local PC104+ interfaces, IO clocks adjust, IO level adjusts,
The sub-circuits such as program and data memory interface, DUT controls and test are all articulated in the OPB of the soft core in the form of OPB IP kernels
(see Fig. 4) in bus.At this point, the control of DUT had not only directly been write using C language with test, but also can write based on OPB buses
IP kernel is suitable for timing requirements are not stringent but logic control is relative complex digital circuit.
(3) circuit based on test vector.The circuit has used the test vector on analog I/O module to store (see Fig. 5)
Device, the two panels SDRAM in test vector memory at this time, a piece of input vector memory as DUT, another as it is expected
It is worth vector memory.The value of input vector memory is written by main control module by local PC104+ interfaces, output vector storage
The value of device may be from two kinds of situations, and one is being write direct by main control module, one is before radiation effect is tested, write-in is real
The DUT output signals of border sampling.In use, user determines content, the vector of test vector memory before radiation effect is tested
Length and output frequency when experiments, test vector are sequential read out from test vector memory and is stored in FIFO, if export to
When amount number reaches vector length, then returns to first vector and continue to output vector successively, until receiving test END instruction.
After FIFO receives data, then it is sequentially output according to set vectorial output frequency.The circuit based on test vector is only
User is needed simply to change the content in DUT signal distribution sub-circuit, the difficulty of secondary development is minimum, and it is simple to be suitable for sequential
Digital integrated electronic circuit is tested.
Master control FPGA should number of pins enough under the premise of, internal storage and resource are as abundant as possible, and PCB makes
Simply.The XC6SLX150-2FGG488C of the Spartan-6 series of Xilinx companies may be selected.
Special Interface Chip realization can be used electrically completely compatible with pci bus in PC104Plus bus interface.It can
Select the pci bus common interface chip PCI9054 of PLX companies of U.S. production.PCI9054 chips are in hardware annexation
Between pci bus and local bus, on the one hand which completes the information exchange with host module by pci bus, in addition
On the one hand the connection with local function circuit is realized by local bus, to logically realize pci bus operation and this
The function that ground bus operation is mutually converted.PCI9054 local bus can be operated in M, C, J Three models.It is local in the present invention
Bus selection C mode.
When clock adjusting circuitry in clock circuit mainly provides work for the I/O port and measured device of input and output
Clock.In order to increase the versatility of system, it is desirable that have the characteristics that adjust its output frequency in real time online.Its acp chip is that can compile
Journey clock generator CY22393FXC, input clock can be in 8~30MHz, and exports clock and can reach 200MHz.The tune of clock
Whole is by internal FLASH configuration memories, access interface I2C interface.The access of the device and control using FPGA come
It realizes.
Test vector memory circuit, which is mainly made of the SDRAM chips MT48LC8M32B4 of two panels 32, makees the device
Memory capacity is 256Mb, reaches 8Mb to which the test vector of each I/O port may finally be made to store concentration.
I/O port direction adjustment circuit mainly uses SN74LVC8T245 chips, the chip to divide the both ends A, B, the ends A and master control
FPGA's is connected, and the ends B are connected with measured device, and the determination of direction controlling pin is signal from A to B or from B to A, A and the ends B
There is respective operating voltage.The direction that pin can adjust I/O channel is controlled by control direction, it is adjustable to adjust the ends B operating voltage
The level of I/O channel.If the ends B operating voltage is indicated with IO_VOLT, IO_VOLT adjustable concrete principle figure such as Figure 10 online is realized
It is shown.TPS76801QD is an adjustable source of stable pressure in Fig. 8, its output concatenates a non-volatile resistance variable
Its resistance value can be arranged by the SPI interface of the device in MCP4162, master control FPGA, to reach on-line tuning
The purpose of TPS76801QD voltage outputs.The adc circuit that LTC2450CDC in Fig. 8 is a 16bit, to measure
The output voltage values of TPS76801QD, the foundation as the adjustment of voltage next time.
Power module is made of master control FPGA, electric current and electric voltage observation circuit and 8 road power supplys (see Fig. 6).8 road power supplys are each
Road is made of linear voltage regulator (LDO), digital regulation resistance, current amplifier and power switch etc..The linear voltage regulator
Output can pass through the adjustment of the adjustable realization output voltage of external digital regulation resistance resistance value；The current amplifier be
Small resistance is concatenated on the output line of LDO, and the current amplifier of high cmrr is used in combination to convert electrical current into voltage；The electricity
Source switch is for controlling whether power channel exports.Electric current and electric voltage observation circuit core are analog-digital converter (ADC), and being used for will
Digital quantity is converted to per voltage, the electric current of road power supply；Power supply master control FPGA has following function：(1) it is used to adjust digital electricity
The resistance of position device；(2) control sequential for providing ADC devices makes ADC devices that can recycle conversion user in DUT irradiation process and refers to
Voltage, the electric current of routing, and transformation result is read at any time；(3) by the value in electric current transformation result and current threshold register
Compared in real time, when conversion value is more than current threshold, exports LDO shutdown signals, close corresponding power channel, and wait
After the time to be specified, keep LDO shutdown signals invalid, keeps power channel output effective.
Power supply voltage stabilizing chip selects LT1764EQ and digital regulation resistance AD5292BRUZ-50.Tool may be selected in current amplifier
There is the high-side current amplifying device MAX4372 of high common mode interference rejection ability.Electromagnetic type relay can be selected in power switch.
The core of electric current and electric voltage observation circuit is D/A converting circuit.The simulation of 16 tunnels is shared on power module upper plate at present
Voltage signal, predominantly per electric current, the voltage signal of road power channel.The acquisition of 16 road analog voltage signals can be used 2
Piece MAX1168 is realized.
The key of master control FPGA design is to ensure overcurrent protection on the basis of ensureing electric current, voltage tester accuracy
Response time avoids the device caused by latch up effect from burning.In addition user select which channel using be it is random,
In this case idle channel should be without the test of electric current, voltage.Therefore master control FPGA is relatively complicated to MAX1168.
Its control flow is as follows (see Figure 11)：
(1) a two-dimentional register array is generated in master control FPGA, which there are 8 rows, correspond to 8 power channels, often
There are 9 registers in a line, respectively：Status register STT_R (2, it is read-only, respectively switching-on and switching-off state position PSTS, protect
Protect mode bit ProtSts), control register CTL_R (4, it is read-write, respectively current monitoring enable bit CurrEn, voltage prison
Survey enable bit VoltEn, power supply and off-position PSTS, locking monitoring enable bit SelEn), channel position register POS_R (8, only
Read, respectively electric current, voltage signal corresponding A DC device numbers, electric current, the corresponding ADC device simulations channel number of voltage), current threshold
Register CURRTH_R (16, only write), guard time setting register SETTIME_R (16, only write), locking number deposit
Device SELNUM_R (16, read-only), measured current value register CURR_R (16, read-only), measurement voltage value register VOLT_
R (16, read-only), guard time register PROTTIME_R (16, read-only).
(2) SELNUM_R, CURR_R, VOLT_R and PROTTIME_R in all power channels, acquiescence are resetted before radiation
Reset values are 0.CTL_R, CURRTH_R and SETTIME_R are set.
(3) it receives after starting test instruction, from small to large according to channel number, the sequence of voltage channel after first current channel
Cycle carries out the conversion of analog to digital amount successively.The current monitoring or voltage monitoring only worked as when conversion in inspection CTL_R make
Can position it is effective, and when guard mode position is invalid, just converted, otherwise enter the conversion in next channel.It, will after conversion end
Transformation result is updated to CURR_R and VOLT_R.
(4) check whether locking monitoring enable bit is effective, if effectively comparing the size of measured current value and current threshold, when
Shi Cezhi >When threshold value, the channel power source is disconnected, locking number register value adds 1, goes to step (3) and carries out next channel
Conversion.Start timer simultaneously, and by timing result update to guard time register, when timing time reaches guard time
When value in register is set, restores power supply output, keep guard mode position invalid.
(5) main control module step (3) with can be as needed in step (4), read locking number register, actual measurement at any time
Electric current value register, measurement voltage value register intermediate value.
(6) after receiving end test instruction, SELNUM_R intermediate values is read, measured device closing in irradiation process is obtained
Lock number.Off-test.
The control software of system uses modularized design, including main interface, power module setting interface, analog I/O module are set
Set interface, DUT controls, display and data processing interface etc..Main interface can freely call power module setting interface, Digital I/O mould
The interfaces such as interface, measured device control, display and data processing are arranged in block.Power module setting interface, analog I/O module
Setting interface is two basic interfaces, can be called by its interface.Power module setting interface is for being arranged circuit-under-test test institute
Power channel, supply voltage, latching current threshold value, the latch-up protection time etc. needed；Open or off power channel.Digital I/O mould
Block setting interface be used for be arranged or display system local computer in existing analog I/O module state, such as Contemporary Digital I/O module
Quantity, each module measurable part category, output and input level value, IO clock frequencies, module enabled state etc. at present.DUT
Control shows there is different interfaces, control, display and data for the digital circuit of different types from data processing interface
Processing method depends on the specific radiation effect test method of measurand.The control software of system is opened to reduce secondary system
The difficulty of hair provides a basic function more than 50 in the way of dynamic link library, and specific tested electricity can be directed to using these functions
DUT controls, display and data processing interface are quickly developed in road.
It is the flow chart of Modularized digital integrated circuit radiation effect on-line testing method as shown in Figure 7, Figure 8,：Including with
Lower step：
1) secondary system exploitation is carried out, step is：
1.1) according to the testing requirement of DUT, the circuit types in the master control FPGA of analog I/O module is determined；1.2) modification master
Control DUT controls and test sub-circuit in FPGA；
1.3) modified circuit is subjected to comprehensive and placement-and-routing, and downloaded in master control FPGA；
1.4) control and data processing, display software interface are write for circuit-under-test；
1.5) debugging and verification experimental verification；
2) it uses system to carry out radiation effect to test, step includes：
2.1) according to circuit-under-test classification, check the difference of local computer existing module quantity and module number needed for test
Not, when number of modules deficiency, it is inserted into new module, is updated when enough in configuration memory in analog I/O module in master control FPGA
Hold；
2.2) system is connected, and ensures that local computer is not irradiated directly；
2.3) it opens system and controls main interface, setting circuit-under-test tests supply voltage and the progress of required power channel
Calibration；The latching current threshold value in channel and latch-up protection time etc. needed for being arranged；The power channel needed for test is opened, checks spoke
It is whether normal according on board supply voltage；
2.4) check whether the circuit configured in master control FPGA in analog I/O module is suitable for circuit-under-test, if uncomfortable
With then return to step (2.1)；If there is extra analog I/O module, the institute for closing extra analog I/O module is functional；
2.5) system main interface opens corresponding circuit spoke automatically according to analog I/O module and power module configuring condition
Penetrate effect test interface；
2.6) setting circuit-under-test effect tests required register and parameter；
2.7) while starting irradiation, the radiation effect parameter testing of start circuit, until off-test.
Claims (7)
1. a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing, including remote computer, local computer and
Plate is irradiated, the local computer is not illuminated, it is characterised in that：
The local computer is a kind of computer running embedded OS, including a main control module, at least one
A analog I/O module and at least one power module；
The remote computer realizes that the control to local computer, the main control module pass through by Desktop Share and Ethernet
Bus is in communication with each other with analog I/O module and power module respectively between plate, and the analog I/O module passes through signal cable and tested device
Part irradiation plate is in communication with each other, and the power module is connect by feed cable with irradiation plate；
The main control module undertakes following functions：
A. it is responsible for making the mutually coordinated work of modules in local computer, realizes and the radiation effect of measured device is tested；
B. it is responsible for the processing, preservation and display to radiation effect data；
C. it is responsible for realizing display interface, preserves data and the teleengineering support with host computer；
D. embedded OS is run；
The analog I/O module provides required multi-channel drive signal for circuit-under-test, and compares the output and expectation of circuit-under-test
The difference of value, then generation system interrupts or caches detailed data when variant, waits for the reading of main control module；Multichannel drives
Direction, level, clock and the online real-time, tunable of sequential of signal；
The power module provides required voltage for circuit-under-test, the monitoring of line output voltage of going forward side by side, static current of lcd, and has
Current protecting function；
The analog I/O module include bus interface, clock circuit, test vector memory, program and data storage between plate,
I/O port level and direction adjustment circuit and master control FPGA；
The master control FPGA by the way that bus is in communication with each other between bus interface and plate between plate, the master control FPGA respectively with test vector
Memory, program and data storage are in communication with each other, and the master control FPGA passes through I/O port level and direction adjustment circuit and quilt
Device irradiation plate is surveyed to be in communication with each other；The master control FPGA is connect with clock circuit；
Bus interface mainly realizes the conversion between local bus in intermodule transfer bus and analog I/O module between the plate, based on
Control the data exchange interface that FPGA provides a standard with the communication of intermodule bus；
The clock circuit is mainly made of local bus clock, FPGA master clocks and I/O signal clock three parts；The part
Bus clock is divided into two-way and is respectively supplied to bus interface between master control FPGA and plate；FPGA master clocks are supplied to master control FPGA, main
It controls FPGA and accesses the clock of test vector memory, data and program storage with this clock；The I/O signal clock
Frequency is adjustable online, the clock for adjusting I/O signal in real time, to meet the needs of different circuit-under-test test frequencies, control
Signal is generated by master control FPGA, in generated clock signal input to master control FPGA；
The test vector memory is mainly used for storing the test vector of I/O channel, is made of 2 RAM, a piece of as DUT's
Input vector memory, another is used as expected value vector memory；
Described program and data storage are used to store as program storage and data when Embeded CPU core in master control FPGA
Device；
The level and direction of the I/O port level and direction adjustment circuit for the online I/O port of adjustment in real time, make Digital I/O mould
The output I/O signal level of block is consistent with the incoming level of circuit-under-test, the input of analog I/O module input signal and master control FPGA
Level is consistent, to realize the compatibility to varying level measured device；
The master control FPGA is responsible for the data exchange between Bus Interface Chip, receives order and number that main control module is sent out
According to realizing the test sequence of measured device, control other circuits on analog I/O module.
2. Modularized digital integrated circuit radiation effect Online Transaction Processing according to claim 1, it is characterised in that：
It can configure three kinds of circuits in master control FPGA：
(1) universal circuit：Include local bus interface, IO clock controls, the control of IO level, DUT controls and test in FPGA
Circuit, it includes that DUT drivings generate, DUT outputs monitor, three parts of DUT signal distribution that the DUT controls are main with test；It removes
DUT is controlled with outside test sub-circuit, and the designing user of other sub-circuits is inaccessible and changes；DUT is controlled and test sub-circuit
Basic template is provided, interface can not be changed, and provide standard sub-circuit for SRAM, FLASH, SRAM type FPGA；
The IO clock controls, IO level control, DUT driving generate and DUT output monitoring respectively by local bus interface with
Bus interface connects between plate, and the output of the IO clock controls is connect with clock circuit, and the input of the IO level control receives
Measured power level signal from I/O port level and direction adjustment circuit, the output transmission level adjustment control of the IO level control
Signal processed is to I/O port level and direction adjustment circuit；The output that the DUT drivings generate is connected with DUT signal distribution, described
The input of DUT output monitorings is connected with DUT signal distribution；DUT signal distribution is connect with I/O port level and direction adjustment circuit；
When configuring universal circuit, analog I/O module receives the data or order that main control module is issued from bus interface between plate, by
Bus interface circuit in analog I/O module is converted to local bus in plate, and local bus interface is then total from part in master control FPGA
Line receives data or order, and specified trigger is written after these data or order are decoded according to the address information in bus
In；The process that data are uploaded to main control module is opposite with this process；
(2) CPU core circuit：The circuit is the stone in FPGA is embedded in soft core or utilizes FPGA, local bus interface, IO
Clock control, the control of IO level, program and data memory interface, DUT are controlled and the sub-circuits such as test are all with standard IP kernel
Form is articulated in the bus of the CPU core；
When configuring the circuit, when local bus interface receives data or the order of main control module transmission, with the formation of interruption
It informs CPU core, then data distribution is given to specified circuit by CPU core；The passback process of its data is in contrast；
(3) circuit based on test vector：The circuit has used the test vector memory on analog I/O module, test at this time to
Measure the two panels RAM in memory, a piece of input vector memory, another conduct expected value vector memory as DUT；It is defeated
The value of outgoing vector memory comes from two kinds of situations, and one is being write direct by main control module, one is tested in radiation effect
Before, the DUT output signals of actual samples are written；
Include local bus interface in master control FPGA, IO clock controls, the control of IO level, wrong data buffer, export and compare
Device, DUT signal distribution, FIFO1 and FIFO2；The IO clock controls, the control of IO level, wrong data buffer pass through part
Bus interface connects between bus interface and plate, and the output end of the IO clock controls is connect with clock circuit, the IO level control
The input of system receives the measured power level signal from I/O port level and direction adjustment circuit, the output hair of the IO level control
The whole control signal of power transmission Heibei provincial opera is to I/O port level and direction adjustment circuit；
The FIFO1 is connect with expected value vector memory, and the FIFO2 is connect with input vector memory, the FIFO1 and
FIFO2 is also connect with local bus interface；The FIFO1 and FIFO2 also receives the IO clocks from clock circuit；
The input of the output end and output comparator of the FIFO1 connects, output end and the DUT signal distribution of the FIFO2
Input connection, the output of DUT signal distribution and the input of comparator connect, DUT signal distribution and I/O port level and direction tune
Whole circuit connection；
In use, user determines content, vector length and the output frequency of test vector memory, examination before radiation effect is tested
When testing, test vector is sequential read out from test vector memory and is stored in FIFO, if output vector number reaches vector length
When, then it returns to first vector and continues to output vector successively, until receiving test END instruction；After FIFO receives data,
Then it is sequentially output according to set vectorial output frequency；
IO clock controls and IO level control circuits in master control FPGA is for generating the outer I/O port level of master control FPGA and direction
Control sequential needed for adjustment circuit；It is mainly that DUT provides required input signal that DUT drivings, which generate,；DUT output monitorings are main
For comparing DUT output valves and desired value, when the two difference, statistics overturning number, and the indentation of the details of mistake is first entered
First go out in buffer, waits for the access of main control module；DUT signal distribution setting DUT inputs, output signal and specific I/O channel
Correspondence.
3. Modularized digital integrated circuit radiation effect Online Transaction Processing according to claim 2, it is characterised in that：
The I/O port level adjusting circuit includes exporting adjustable linear voltage regulator, digital regulation resistance, ADC and level conversion
Device, digital regulation resistance adjust resistance as the output voltage of linear voltage regulator, and the output voltage of linear voltage regulator is level conversion
Device connect the supply voltage surveyed with tested DUT；
When needing to adjust level, master control FPGA generates the control signal of digital regulation resistance, adjusts the resistance of digital regulation resistance, to
The output voltage of linear adjustment voltage-stablizer, ADC acquire output voltage values under master control FPGA controls, and master control FPGA is by constantly adjusting
Integer word potentiometer resistance, and measurement voltage value and desired voltage values are compared, realize the closed-loop control to output voltage.
4. a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing according to claim 1 or 2 or 3,
It is characterized in that：
The power module is made of power supply master control FPGA, electric current and electric voltage observation circuit and DUT power supplys,
The DUT power supplys include multiple identical power channels, and each channel includes linear voltage regulator, digital regulation resistance, electricity
Stream amplifier and power switch；
The output of the linear voltage regulator can pass through the adjustment of the adjustable realization output voltage of external digital regulation resistance resistance value；
The current amplifier is that small resistance is concatenated on the output line of linear voltage regulator, and the Current amplifier of high cmrr is used in combination
Device converts electrical current into voltage；The power switch is for controlling whether power channel exports；
The electric current and electric voltage observation circuit core are analog-digital converter, for voltage, the electric current of every road power supply to be converted to number
Word amount；
The power supply master control FPGA has following function：
(1) it is used to adjust the resistance of digital regulation resistance；
(2) control sequential for providing ADC devices makes ADC devices that can recycle conversion user's dedicated tunnel in DUT irradiation process
Voltage, electric current, and transformation result is read at any time；
(3) compared with carrying out electric current transformation result in real time with the value in current threshold register, when conversion value is more than current threshold
When, linear voltage regulator shutdown signal is exported, closes corresponding power channel, and after awaiting a specified time, make linear voltage stabilization
Device shutdown signal is invalid, keeps power channel output effective.
5. a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing according to claim 4, feature exist
In：
The control software of local computer uses modularized design, including main interface, power module setting interface, analog I/O module
Interface, DUT control interfaces and display and data processing interface are set；
The main interface can freely call power module setting interface, analog I/O module setting interface, measured device control, display
With data processing interface；
Power module setting interface, analog I/O module setting interface are two basic interfaces, can be called by other interfaces；
Power module setting interface is used to be arranged the required power channel of circuit-under-test test, supply voltage, latching current
Threshold value, latch-up protection time；Open or off power channel；
Analog I/O module setting interface be used to be arranged or display system local computer in existing analog I/O module state；
The digital circuit of the DUT control interfaces, display from data processing interface for different types has different interfaces,
Control, display and data processing method depend on the specific radiation effect test method of measurand.
6. a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing according to claim 5, feature exist
In：
The control software of local computer provides a basic function more than 50 in the way of dynamic link library, and the basic function can
DUT controls, display and data processing interface are quickly developed for specific circuit-under-test.
7. a kind of Modularized digital integrated circuit radiation effect on-line testing method, it is characterised in that：Include the following steps：
1) secondary system exploitation is carried out, step is：
1.1) according to the testing requirement of DUT, the circuit types in the master control FPGA of analog I/O module is determined；1.2) master control is changed
DUT controls and test sub-circuit in FPGA；
1.3) modified circuit is subjected to comprehensive and placement-and-routing, and downloaded in master control FPGA；
1.4) control and data processing, display software interface are write for circuit-under-test；
1.5) debugging and verification experimental verification；
2) it uses system to carry out radiation effect to test, step includes：
2.1) according to circuit-under-test classification, the difference of local computer existing module quantity and module number needed for test is checked,
When number of modules deficiency, it is inserted into new module, when enough, updates the configuration memory content in master control FPGA in analog I/O module；
2.2) system is connected, and ensures that local computer is not irradiated directly；
2.3) it opens system and controls main interface, setting circuit-under-test tests the supply voltage of required power channel and carries out school
It is accurate；The latching current threshold value in channel and latch-up protection time needed for being arranged；The power channel needed for test is opened, checks irradiation plate
Whether upper supply voltage is normal；
2.4) check whether the circuit configured in master control FPGA in analog I/O module is suitable for circuit-under-test, if not applicable,
Return to step (2.1)；If there is extra analog I/O module, the institute for closing extra analog I/O module is functional；
2.5) system main interface is opened corresponding channel radiation automatically according to analog I/O module and power module configuring condition and is imitated
Answer test interface；
2.6) setting circuit-under-test effect tests required register and parameter；
2.7) while starting irradiation, the radiation effect parameter testing of start circuit, until off-test.
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