CN105911454A - System and method for online testing of radiation effect of modular digital integrated circuit - Google Patents
System and method for online testing of radiation effect of modular digital integrated circuit Download PDFInfo
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- CN105911454A CN105911454A CN201610240286.XA CN201610240286A CN105911454A CN 105911454 A CN105911454 A CN 105911454A CN 201610240286 A CN201610240286 A CN 201610240286A CN 105911454 A CN105911454 A CN 105911454A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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Abstract
The invention relates to a system and method for the online testing of a radiation effect of a modular digital integrated circuit, and the system enables all needed function circuits in the effect testing to be divided into relatively independent modules on the basis of summarizing the similarities and differences of conventional digital integrated circuit radiation effect online testing systems. The electrical and mechanical connection among the modules, the design in the modules and the mechanical structure of a system board respectively employ conventional industrial standards, thereby achieving a purpose that a system can employ a commercial module or an independently developed modular for quick connection, enabling the system to be better in expandability, and saving the design time and cost of hardware. The method can be used for the majority of the online testing of the radiation effect of digital integrated circuits of bullets and satellites. The system plays an important role in standardizing a national radiation effect online testing system.
Description
Technical field
The present invention relates to the test of digital integrated electronic circuit radiation effect, particularly relate to a kind of Modularized digital integrated
Channel radiation effect Online Transaction Processing.
Background technology
The natural radiation environment in space and nuclear radiation environment, can in electronic device produce accumulated dose, single-particle,
Neutron displacement and moment dose rate effect, thus cause the degeneration even disabler of electronic device electrical quantity,
Have a strong impact on spacecraft and the life-span of strategic arms and reliability, it is therefore necessary to accurately measure electronics device on ground
Electrical quantity in the radiative process of part and changes of function, think that the radiation resistance evaluation of electronic device provides number
According to.
The radiation effect test of electronic device is divided into online and off-line test two kinds.Wherein on-line testing is mainly used in
The transient-radiation effect (such as single-particle, dose rate effect etc.) of real-time monitor part, or at steady state irradiation
Process (such as accumulated dose, neutron displacement effect etc.) provides Radiation bias.Due to the particularity of radiation effect,
Existing commercial test measurement equipment is difficult to directly apply to on-line testing, needs to lose efficacy existing in research device radiation
As with mechanism on the basis of, the radiation effect Online Transaction Processing needed for development.
Digital integrated electronic circuit mainly includes memorizer, programmable logic array (FPGA), central processing unit
(CPU), central controller (MCU) etc., be current spacecraft and weaponry use the widest
General device, the method for testing of its radiation effect and measurement system also become domestic in recent years pay close attention to right
As.
The device development radiation effect that domestic current existing measurement system mainly aims at certain type or model is online
Test system, the development of each test system is required to through hardware principle design, pcb board making, hardware
Multiple links such as debugging, software programming, but digital integrated electronic circuit is of a great variety, device production and application unit
Can be simultaneously in the face of the radiation effect testing requirement of multiple digital integrated electronic circuit, according to existing method, need be
System developer develops many set test systems, and development amount is big, time length, cost are high, and an urgent demand is more
Changing development thinking, development has the radiation effect Online Transaction Processing of versatility.
By analyzing, the accumulated dose of all kinds of large-scale digital ics, single-particle, neutron displacement effect exist
Line test has following identical point predominantly:
(1) testing requirement is essentially identical.The total dose effect of digital integrated electronic circuit, neutron displacement effect are tested
Mainly needing test system is that measured device (DUT) provides dynamically or static radiation biasing, and at irradiation
During monitor DUT key electrical, such as the situation of change of static current of lcd.And single particle effect test needs
The monitoring single event latchup (SEL) of DUT, SEU cross section (SEU), single event function interrupt (SEFI)
Uiform section, wherein the test in SEL cross section is on the basis of electric current is monitored in real time, it is achieved latch-up protection and closing
Lock number of times statistics, and the test of SEU, SEFI is all the test to DUT major function.Therefore device
Single particle effect test system is after the Long line transmission problem solved between measured device and test circuit, so that it may
For accumulated dose, the test of single particle effect.
(2) ultimate principle of different circuit function tests is identical.Either DSP or SRAM type FPGA
Device, the functional test ultimate principle of its radiation effect is all the pumping signal needed for providing for DUT, monitoring
Export different from expected value.
When facing concrete measured device, the difference between different components mainly shows themselves in that (1) number of power sources
And voltage is different；(2) quantity of pumping signal, sequential, frequency difference；(3) the radiation effect of different DUT
Answer result processing method different.
Therefore the radiation effect on-line testing of variety classes digital integrated electronic circuit is identical on the whole, but tool
Body details is different, and these differences can overcome by design of hardware and software, and this allows for development has and lead to more by force
With the integrated circuit radiation effect Online Transaction Processing of property, there is the strongest feasibility technically.
Further, since the domestic radiation effect method of testing to all kinds of digital integrated electronic circuits has not yet been formed unified
Understanding and specification, the measurement system of commensurate's exploitation is not far from each other, acquired radiation resistance test number
According to without comparability, causing the substantial amounts of wasting of resources, standardization and standardization to test system propose and want
Ask.In this case, the quantity of radiation effect Online Transaction Processing is the fewest with classification, its normalized work
Making to be more conducive to carry out and advance, therefore the standardization work of radiation effect Online Transaction Processing is also in the urgent need to sending out
Exhibition has the radiation effect Online Transaction Processing of versatility.
Summary of the invention
In order to solve the technical problem existing for background technology, the present invention is in research digital integrated electronic circuit radiation effect
Answer micromechanism of damage, analyse in depth and summarize all kinds of large-scale digital ic accumulated dose, single-particle, neutron
On the basis of the similarities and differences of displacement effect on-line testing, it is provided that a kind of Modularized digital integrated circuit radiation effect
Answer Online Transaction Processing and method of testing.
The technical solution used in the present invention is as follows:
The present invention provides a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing, including remote computation
Machine, local computer and irradiation plate, described local computer is not illuminated, and it is characterized in that
Described local computer is a kind of computer running embedded OS, including a master control mould
Block, at least one analog I/O module and at least one power module；
Described remote computer realizes the control to local computer, described master control by Desktop Share and Ethernet
Module is in communication with each other with analog I/O module and power module respectively by bus between plate, described analog I/O module
Being in communication with each other with measured device irradiation plate by signal cable, described power module passes through feed cable and irradiation
Plate connects；
Described main control module undertakes following functions:
D. it is responsible for making the mutually coordinated work of modules in local computer, it is achieved the radiation to measured device is imitated
Should test；
E. it is responsible for the process to radiation effect data, preserves and show；
F. it is responsible for realizing display interface, preserving data and the teleengineering support with host computer；
D. embedded OS is run；
Described analog I/O module is the multi-channel drive signal needed for circuit-under-test offer, and compares circuit-under-test
Output and the difference of expected value, then produce system break when variant or detailed data cached, waiting main
The reading of control module；The online real-time, tunable of the direction of multi-channel drive signal, level, clock and sequential；
Described power module is the voltage needed for circuit-under-test offer, line output voltage of going forward side by side, the prison of static current of lcd
Survey, and possess current protecting function.
Being more than the basic structure of the present invention, based on this basic structure, the present invention also makes following optimization and limits:
Above-mentioned I/O module includes EBI between plate, clock circuit, test vector memorizer, program and data
Memorizer, I/O port level and direction adjust circuit and master control FPGA；
Described master control FPGA by between plate between EBI and plate bus be in communication with each other, described master control FPGA divides
Not being in communication with each other with test vector memorizer, program and data storage, described master control FPGA passes through IO end
Mouth level and direction adjust circuit and are in communication with each other with measured device irradiation plate；Described master control FPGA and clock electricity
Road connects；
Turning between local bus in EBI mainly realizes intermodule transfer bus and I/O module between described plate
Change, for the data exchange interface of master control FPGA with communication one standard of offer of intermodule bus；
Described clock circuit is mainly by local bus clock, FPGA master clock and I/O signal clock three part group
Become；Described local bus clock is divided into two-way to be respectively supplied to EBI between master control FPGA and plate；FPGA
Master clock is supplied to master control FPGA, master control FPGA and accesses test vector memorizer, data and program storage
Clock all use this clock；The frequency of described I/O signal clock is the most adjustable, adjusts IO letter in real time
Number clock, with the demand of satisfied different circuit-under-tests test frequencies, its control signal is produced by master control FPGA
Raw, produced clock signal is input in master control FPGA；
Described test vector memorizer is mainly used in storing the test vector of I/O channel, is made up of 2 RAM,
The a piece of input vector memorizer as DUT, another sheet is as expected value vector memorizer；
Described program and data storage in master control FPGA during Embeded CPU core as program storage
And data storage；
Described I/O port level and direction adjust circuit and are used for the online level adjusting I/O port in real time and direction,
The output I/O signal level making I/O module is consistent with the incoming level of circuit-under-test, I/O module input signal with
The incoming level of master control FPGA is consistent, thus realizes the compatibility to varying level measured device；
The data exchange that described master control FPGA is responsible between Bus Interface Chip, receives what main control module sent
Order and data, it is achieved the test sequence of measured device, control other circuit in I/O module.
For realizing the measurement of the radiation effect under different mode, configurable three kinds of electricity in master control FPGA of the present invention
Road:
(1) universal circuit: include in FPGA local bus interface, IO clock control, IO Automatic level control,
DUT controls and tests electronic circuit, and described DUT controls mainly to comprise DUT with test and drives generation, DUT
Output monitoring, DUT signal three parts of distribution；In addition to DUT controls with test electronic circuit, other electronic circuit
Designing user inaccessible and change；DUT controls to provide basic template, interface with test electronic circuit
Can not change, and provide standard electronic circuit for SRAM, FLASH, SRAM type FPGA；
Described IO clock control, IO Automatic level control, DUT drive generation and DUT output monitoring to pass through respectively
Between local bus interface with plate, EBI is connected, and the output of described IO clock control is connected with clock circuit,
The input of described IO Automatic level control receives the measured power level signal adjusting circuit from I/O port level and direction,
The output transmission level of described IO Automatic level control adjusts control signal and adjusts circuit to I/O port level and direction；
Described DUT drives the distribution of the output and the DUT signal that produce to be connected, input that described DUT output is monitored and
DUT signal distribution connects；DUT signal distribution adjusts circuit with I/O port level and direction and is connected；
When configuring universal circuit, I/O module EBI between plate receives data or the life that main control module is issued
Order, is converted to local bus in plate, local bus in master control FPGA by the bus interface circuit in I/O module
Interface then receives data or order from local bus, and these data or order is believed according to the address in bus
Write in the trigger specified after breath decoding；The process that data are uploaded to main control module is contrary with this process；
(2) CPU core circuit: this circuit is to be embedded in soft core at FPGA or utilize the stone in FPGA,
Local bus interface, IO clock control, IO Automatic level control, program and data memory interface, DUT control
All it is articulated in the bus of this CPU core with the form of standard IP kernel with electronic circuits such as tests；
Configure this circuit time, local bus interface receive main control module send data or order time, with in
CPU core is informed in disconnected formation, then data are distributed to the circuit specified by CPU core；The passback of its data
Journey is in contrast；
(3) circuit based on test vector: this circuit employs the test vector memorizer in I/O module, this
Time test vector memorizer in two panels RAM, a piece of input vector memorizer as DUT, another sheet
As expected value vector memorizer；The value of output vector memorizer comes from two kinds of situations, and one is by master control
Module is write direct, and one is before radiation effect is tested, the DUT output signal of write actual samples；
Include in master control FPGA that local bus interface, IO clock control, IO Automatic level control, wrong data are delayed
The distribution of storage, output comparator, DUT signal, FIFO1 and FIFO2；Described IO clock control, IO
Automatic level control, wrong data buffer are connected, during described IO by EBI between local bus interface with plate
The outfan of clock is connected with clock circuit, and the input of described IO Automatic level control receives from I/O port electricity
Flat and direction adjusts the measured power level signal of circuit, and the output transmission level of described IO Automatic level control adjusts and controls
Signal adjusts circuit to I/O port level and direction；
Described FIFO1 is connected with expected value vector memorizer, and described FIFO2 is connected with input vector memorizer,
Described FIFO1 and FIFO2 is also connected with local bus interface；Described FIFO1 and FIFO2 also receives
From the IO clock of clock circuit；
The outfan of described FIFO1 is connected with the input of output comparator, the outfan of described FIFO2 and DUT
The input of signal distribution connects, and the output of DUT signal distribution is connected with the input of comparator, and DUT signal divides
Join and be connected with I/O port level and direction adjustment circuit；
During use, user determines the content of test vector memorizer, vector length and defeated before radiation effect is tested
Go out frequency, during test, from test vector memorizer, sequential read out test vector and be stored in FIFO, if defeated
When outgoing vector number reaches vector length, then return first vector and continue to put out vector successively, until receiving
Test END instruction；After FIFO receives data, then it is sequentially output according to set vectorial output frequency；
IO clock control and IO level control circuit in master control FPGA are used for producing the outer IO of master control FPGA
Port level and direction adjust the control sequential needed for circuit；DUT drives generation predominantly DUT to provide institute
The input signal needed；DUT output monitoring be mainly used in comparing DUT output valve and expected value, when both not
Meanwhile, statistics upset number, and by the details press-in fifo buffer of mistake, wait master control mould
The access of block；DUT signal distribution arranges DUT input, output signal and the corresponding relation of concrete I/O channel.
Above-mentioned I/O port level adjusting circuit includes exporting adjustable linear voltage regulator, digital regulation resistance, ADC and electricity
Flat turn parallel operation, digital regulation resistance adjusts resistance, linear voltage regulator defeated as the output voltage of linear voltage regulator
Going out voltage is that level translator is connected the supply voltage surveyed with tested DUT；
When needing to adjust level, master control FPGA produces the control signal of digital regulation resistance, regulates digital regulation resistance
Resistance, thus the output voltage of linear adjustment manostat, ADC gathers output under master control FPGA controls
Magnitude of voltage, master control FPGA is by constantly adjusting digital regulation resistance resistance, and magnitude of voltage and expectation are surveyed in comparison
Magnitude of voltage, it is achieved the closed loop control to output voltage.
Above-mentioned power module is made up of power supply master control FPGA, electric current and voltage monitoring and DUT power supply,
Described DUT power supply comprises multiple identical power channel, and each passage all includes linear voltage regulator, number
Word potentiometer, current amplifier and on and off switch；
The output of described linear voltage regulator can be by the adjustable realization output electricity of external digital regulation resistance resistance value
The adjustment of pressure；Described current amplifier is to concatenate little resistance on the output lead of linear voltage regulator, and with high
The current amplifier of common mode rejection ratio converts electrical current into voltage；Described on and off switch is used for controlling power channel
Whether export；
Described electric current and electric voltage observation circuit core are analog-digital converter, for by the voltage of every road power supply, electricity
Circulation is changed to digital quantity；
Described power supply master control FPGA has a following function:
(1) for regulating the resistance of digital regulation resistance；
(2) the control sequential of ADC device is provided, makes ADC device can circulate in DUT irradiation process
The conversion voltage of user's dedicated tunnel, electric current, and read transformation result at any time；
(3) electric current transformation result is compared in real time with the value in current threshold register, when conversion value is big
When current threshold, output linearity manostat shutdown signal, the power channel corresponding to closedown, and wait refer to
After the fixed time, make linear voltage regulator shutdown signal invalid, make power channel output effectively.
The control software of above-mentioned local computer uses modularized design, comprises main interface, power module setting
Interface, I/O module arrange interface, DUT controls interface and display processes interface with data；
Described main interface can freely call that power module arranges interface, I/O module arranges interface, measured device control
System, display process interface with data；
Described power module arranges interface, to arrange interface be two basic interfaces to I/O module, can be by other interface
Call；
Described power module arrange interface for arrange circuit-under-test test needed for power channel, supply voltage,
Latching current threshold value, latch-up protection time；Open or off power channel；
Described I/O module arranges interface for arranging or the shape of existing I/O module in display system local computer
State；
Described DUT controls interface, display has not for the digital circuit of different types from data process interface
Same interface, its control, display and data processing method depend on the concrete radiation effect test of measurand
Method.
In order to reduce the difficulty of secondary system exploitation, the control software of local computer utilizes dynamic link library mode
Providing more than 50 basic function, described basic function can quickly develop DUT control for concrete circuit-under-test
System, display process interface with data.
The present invention also provides for a kind of Modularized digital integrated circuit radiation effect on-line testing method, its special it
Place is: comprise the following steps:
1) carrying out secondary system exploitation, step is:
1.1) according to the testing requirement of DUT, the circuit types in the master control FPGA of I/O module is determined；
1.2) in amendment master control FPGA, DUT controls and test electronic circuit；
1.3) amended circuit is carried out comprehensive and placement-and-routing, and download in master control FPGA；
1.4) write control for circuit-under-test and data process, display software interface；
1.5) debugging verification experimental verification；
2) use system carries out radiation effect test, and step includes:
2.1) according to circuit-under-test classification, the required number of modules of the existing module number of local computer and test is checked
The difference of amount, during number of modules deficiency, inserts new module, time enough, updates master control FPGA in I/O module
Interior configuration memory content；
2.2) connection system, and ensure that local computer is not by direct irradiation；
2.3) system of opening controls main interface, arranges the supply voltage of power channel needed for circuit-under-test test
And calibrate；Latching current threshold value and the latch-up protection time of required passage are set；Needed for opening test
Power channel, checks that irradiation on board supply voltage is the most normal；
2.4) check whether the circuit configured in master control FPGA in I/O module is applicable to circuit-under-test, if
Inapplicable, then return step (2.1)；If there being unnecessary I/O module, then close all of unnecessary I/O module
Function；
2.5) corresponding circuit is opened automatically according to I/O module and power module configuring condition in the main interface of system
Radiation effect test interface；
2.6) the required depositor of circuit-under-test effect test and parameter are set；
2.7) while starting irradiation, the radiation effect parameter testing of circuit is started, until off-test.
The good effect that the present invention is had:
1. the present invention is directed to domestic existing radiation effect Online Transaction Processing poor universality, dissimilar integrated electricity
Road is both needed to expend a large amount of human and material resources and again develops the problem of new system, utilizes modular thinking, grinds
Make the most general a kind of digital integrated electronic circuit radiation effect Online Transaction Processing.Modularity refers to summing up
On the basis of the existing digital integrated electronic circuit radiation effect Online Transaction Processing similarities and differences, required during effect is tested
Various functional circuits be divided into relatively independent module, each intermodule electrically and be mechanically connected, module
Interior design, the frame for movement etc. of system board all use existing industrial standard, thus realize system and can use
Commercial module or the module fast construction of independent development, be allowed to have more preferable extensibility, thus saves hard
The design time of part and cost.Can be used for great majority and play the radiation effect on-line testing of star digital integrated electronic circuit.
System also has important function to the standardization promoting this state's radiation effect Online Transaction Processing.
2, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing that the present invention develops, utilization can
The local computer running embedded Windows operating system instead of traditional effect Online Transaction Processing (base
This framework is shown in Fig. 9) in microcontroller or microprocessor.In this case, the exploitation of system only need to be in this locality
On computer, exploitation controls software, it is to avoid both developed host computer in traditional effect Online Transaction Processing soft
Part, the problem developing again slave computer software.It addition, the powerful of local computer function also makes effect test
Data can be saved in local computer nearby, it is to avoid the Long line transmission problem of high-volume effect data, make effect
That should test is in hgher efficiency.
3, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing that the present invention develops can be used for
In the multiple effect tests such as accumulated dose, single-particle and neutron displacement effect.The design of system local computer is to the greatest extent
Miniaturization, low-power consumption and heat dissipation problem may be considered, make system in accumulated dose and neutron are tested, be more easy to
In shielding, can the most normally work in heavy ion single particle experiment.
4, a kind of Modularized digital integrated circuit radiation effect Online Transaction Processing that the present invention develops is compared domestic
Existing radiation effect test system, has clear superiority in terms of versatility, mainly shows themselves in that (1) system
Global design use industry working standard,；(2) system I/O module and power module reusable；(3)
The IO level of I/O module, direction, frequency is the most adjustable, and the generation of DUT input signal is compared with output
Provide multiple implementation and basic templates；(4) voltage of power module is the most adjustable, can monitor in real time
Electric current, voltage, possess current protecting function etc..
Accompanying drawing explanation
Fig. 1 is overall system architecture；
Fig. 2 is system I/O module theory of constitution block diagram；
Fig. 3 is that I/O module master control FPGA internal circuit schematic diagram configures universal circuit；
Fig. 4 is that the configuration of I/O module master control FPGA internal circuit schematic diagram has CPU soft nuclear power road；
Fig. 5 is that I/O module master control FPGA internal circuit schematic diagram configures circuit based on test vector；
Fig. 6 is power module theory of constitution block diagram；
Fig. 7 is secondary system development process；
Fig. 8 is that system uses flow process；
Fig. 9 is that the integrated radiation effect of conventional digital tests overall system architecture；
Figure 10 is the circuit theory diagrams that I/O module IO level adjusts；Figure 11 is that power module realizes each passage
Electric current and the flow process of voltage monitoring.
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is elaborated.
As it is shown in figure 1, Modularized digital integrated circuit radiation effect Online Transaction Processing provided by the present invention,
System is mainly made up of remote computer, local computer and irradiation plate three part.Remote computer passes through table
The control realized local computer is shared in face, is connected with short-term between local computer with irradiation plate.Radiation effect
When should test, local computer is placed on radiation source periphery, does not configure display, and ensures not to be illuminated.This
Ground computer is a kind of to run the miniaturization of embedded OS, low-power consumption computer.This computer by
Main control module, analog I/O module, power module and special module four generic module composition, intermodule electrically with
It is mechanically connected and uses PC104+/PC104 agreement.Main control module mainly undertakes following functions: A. to be responsible for making system
The mutually coordinated work of middle modules, it is achieved the radiation effect of measured device is tested；B. it is responsible for large quantities of dose-effects
Answer data process, preserve, display etc.；C. it is responsible for realizing display interface, preserves the long-range of data and host computer
Share.System can only have 1 main control module.Module can run WinXP embedded system, Digital I/O
Module is mainly the driving signal needed for providing for tested integrated circuit, and compares output and the phase of circuit-under-test
The difference of prestige value, then produces system break when variant or detailed data is cached, waiting main control module
Read.
Main control module can be selected for existing commercial product, it is desirable to while having PC104+/PC104 interface, also
Must have the feature that (1) can run XPE operating system；(2) there is the network interface of more than 100,000,000,
There is the plate patch solid state hard disc of more than 2GB capacity；(3) volume is little, and power consumption is little, is not required to fan cooling.Build
View selects the single-borad computer CM-745 that Ling Hua science and technology produces.
System can be installed 1～3 analog I/O module as required.Power module is responsible for circuit-under-test to be provided
Required voltage, line output voltage of going forward side by side, the monitoring of static current of lcd, and possess current protecting function.System
In 1～2 power module can be installed as required.Special module is mainly used in when the function of above three module
When still can not meet the testing requirement of tested integrated circuit, the module increased separately.I/O module can provide 64
Direction, road, level, the digital I/O signal of the online real-time, tunable of clock.As in figure 2 it is shown, this module mainly by
PC104Plus EBI, clock circuit, test vector memorizer, program and data storage, IO end
Mouth level and direction adjust the circuit such as circuit, master control FPGA composition.PC104+ EBI mainly realizes
Conversion between PC104+ bus and local bus, for providing a mark between master control FPGA and PC104+ bus
Accurate data exchange interface；Clock circuit is mainly by PC104+ interface clock, FPGA master clock and I/O signal
Clock three part forms.PC104+ interface clock is mainly PC104+ EBI and provides clock, and frequency is
33MHz.FPGA master clock is the clock in FPGA used by major design circuit, FPGA access test to
The clock of amount memorizer, data and program storage all uses this clock, in the present invention FPGA master clock
Frequency is 125MHz.The frequency of I/O signal clock is the most adjustable, adjusts 64 road IO letters in real time
Number clock, with the demand of satisfied different circuit-under-tests test frequencies, the adjusting range of its frequency is
1kHZ～100MHz；Test vector memorizer is made up of the SDRAM of two 32, such 64 IO
Each in passage is just corresponding each data wire of SDRAM.Storage depth depends on SDRAM
Capacity, if the capacity of SDRAM is 8M × 32bit, the degree of depth of the vector memory of the most each IO is 8Mb.
As program storage and number when program and data storage are mainly used in Embeded CPU core in master control FPGA
According to memorizer.I/O port level and direction adjust circuit for the online level adjusting I/O port in real time and side
To, the output I/O signal level making I/O module is consistent with the incoming level of circuit-under-test, I/O module input letter
Number consistent with the incoming level of master control FPGA, thus realize the compatibility to varying level measured device.Level
Adjusting range be 1.2～5.0V.
Master control FPGA is the core of I/O module, the data exchange that it is responsible between PC104+ interface, connects
Receive order and data that main control module sends, the test sequence of the existing measured device of experiment, control in I/O module
Other circuit etc..The present invention, for the ease of the secondary development of user, devises three kinds of electricity in master control FPGA
Road:
(1) universal circuit.When using this circuit, the vector memory in I/O module does not uses, FPGA
Mainly include local PC104+ interface, the adjustment of IO clock, the adjustment of IO level, program and data storage
The electronic circuits (see Fig. 3) such as interface, DUT control and test.For ease of secondary development, except DUT control with
Outside test electronic circuit, the designing user inaccessible of other electronic circuit and change, DUT controls and test son electricity
The interface on road can not be changed, and inside provides basic template, and for SRAM, FLASH, SRAM
Type FPGA provides standard electronic circuit.Local PC104+ interface mainly realizes FPGA Yu PC104+ interface
The data exchange of chip chamber, controls decoding and the access etc. of depositor；IO clock adjusts and mainly realizes outside
IO clock produces the control of chip；IO level adjusts the resistance being mainly adjusted by the outer digital regulation resistance of FPGA
Value, it is achieved the adjustment of DUT end IO power level, and control the level after outside ADC device actual measurement adjusts,
The closed loop realizing IO level adjusts；Program and data memory interface mainly realize the control to outside SDRAM
System and access, when FPGA internal storage capacity is inadequate, external memory storage is as supplementing；DUT controls
Mainly comprise DUT with test and drive generation, DUT output monitoring, DUT signal three subprograms of distribution.
DUT drives and produces predominantly DUT offer such as the input signal needed for address, clock, Read-write Catrol etc.；
DUT output monitoring is mainly used in comparing DUT output valve and expected value, the statistics upset number when both are different,
And by details press-in fifo buffer (FIFO) of mistake, wait the access of main control module；
State DUT signal distribution and DUT input, output signal and the corresponding relation of concrete I/O channel are mainly set.
Universal circuit can support the secondary development of most digital integrated electronic circuit radiation effect on-line testing, but needs
The secondary development person of system utilizes hardware program language such as VHDL or Verilog to write the control of circuit-under-test
Device, construction cycle difficulty is relatively big, is suitable for the digital integrated electronic circuit test of complex time.
(2) there is CPU soft nuclear power road.When using this circuit, the vector memory in I/O module does not uses.
This circuit is to be embedded in the soft core of MicroBlaze at FPGA, and other circuit, such as local PC104+ interface, IO
The electronic circuits such as clock adjustment, the adjustment of IO level, program and data memory interface, DUT control and test are all
It is articulated in the OPB bus of this soft core (see Fig. 4) with the form of OPB IP kernel.Now, the control of DUT
System both may utilize C language with test and directly write, and can write again IP kernel based on OPB bus, it is adaptable to
To timing requirements is strict but digital circuit that logic control is relative complex.
(3) circuit based on test vector.This circuit (see Fig. 5) employs the test vector in I/O module
Memorizer, now two panels SDRAM in test vector memorizer, a piece of input vector as DUT is deposited
Reservoir, another sheet are as expected value vector memorizer.The value of input vector memorizer is passed through this by main control module
Ground PC104+ interface write, the value of output vector memorizer may be from two kinds of situations, and one is by master control mould
Block writes direct, and one is before radiation effect is tested, the DUT output signal of write actual samples.Use
Time, user determines the content of test vector memorizer, vector length and output frequency before radiation effect is tested,
During test, from test vector memorizer, sequential read out test vector and be stored in FIFO, if output vector number
When reaching vector length, then returning first vector and continue to put out vector successively, terminating until receiving test
Instruction.After FIFO receives data, then it is sequentially output according to set vectorial output frequency.Described based on
The circuit of test vector only needs the content in user's simple modification DUT signal distribution electronic circuit, its secondary development
Difficulty minimum, it is adaptable to the simple digital integrated electronic circuit of sequential is tested.
Master control FPGA should be under number of pins enough premise, and internal storage and resource are the abundantest, and
PCB makes simple.The XC6SLX150-2FGG488C of the Spartan-6 series of optional Xilinx company.
PC104Plus EBI, electrically completely compatible with pci bus, can use Special Interface Chip real
Existing.Can be selected for the pci bus common interface chip PCI9054 that PLX company of the U.S. produces.PCI9054 core
Sheet is between pci bus and local bus in hardware annexation, and this chip is on the one hand total by PCI
It is mutual that line completes the information with host module, and still further aspect is realized and local function circuit by local bus
Connection, thus logically realize the function of pci bus operation with local bus operation mutually conversion.
PCI9054 local bus can be operated in M, C, J Three models.Local bus selects C mould in the present invention
Formula.
Clock adjusting circuitry in clock circuit is mainly for I/O port and the measured device offer work of input and output
Make clock.In order to increase the versatility of system, it is desirable to have the online feature adjusting its output frequency in real time.
Its acp chip is programmable clock generator CY22393FXC, its input clock can 8～30MHz, and
Output clock can reach 200MHz.The adjustment of clock is to configure memorizer by internal FLASH, accesses
Interface is I2C interface.The access of this device and control utilize FPGA to realize.
Test vector memory circuitry is mainly by the SDRAM chip MT48LC8M32B4 group of two panels 32
The memory capacity becoming to make this device is 256Mb, thus the test vector of each I/O port may finally be made to store
Concentration reaches 8Mb.
I/O port direction adjusts main circuit SN74LVC8T245 to be used chip, and this chip divides A, B two ends,
A end is connected with master control FPGA's, and B end is connected with measured device, and direction controlling pin determines it is letter
Number from A to B or from B to A, A Yu B end has respective running voltage.Pin is controlled by control direction
The direction of adjustable I/O channel, the level of regulation B end running voltage adjustable I/O channel.If B end works
Voltage IO_VOLT represents, it is achieved the online adjustable concrete schematic diagram of IO_VOLT is as shown in Figure 10.Figure
In 8, TPS76801QD is an adjustable source of stable pressure, its output one non-volatile resistance variable of concatenation
MCP4162, master control FPGA can arrange its resistance value by the SPI interface of this device, thus reach
Line adjusts the purpose of TPS76801QD voltage output.LTC2450CDC in Fig. 8 is a 16bit's
Adc circuit, in order to measure the output voltage values of TPS76801QD, as the foundation of Voltage Cortrol next time.
Power module is formed (see Fig. 6) by master control FPGA, electric current and voltage monitoring and 8 road power supplys.8 tunnels
The each road of power supply is by linear voltage regulator (LDO), digital regulation resistance, current amplifier and on and off switch etc.
Composition.The output of described linear voltage regulator can be by the adjustable realization output of external digital regulation resistance resistance value
The adjustment of voltage；Described current amplifier is to concatenate little resistance on the output lead of LDO, and uses high common mode
The current amplifier of rejection ratio converts electrical current into voltage；Described on and off switch is used for whether controlling power channel
Output.Electric current and electric voltage observation circuit core are analog-digital converter (ADC), for by the electricity of every road power supply
Pressure, electric current are converted to digital quantity；Power supply master control FPGA has following function: (1) is used for regulating numeral
The resistance of potentiometer；(2) the control sequential of ADC device is provided, makes the ADC device can be at DUT irradiation
During circulation the conversion voltage of user's dedicated tunnel, electric current, and read transformation result at any time；(3) by electricity
Stream transformation result compares in real time with the value in current threshold register, when conversion value is more than current threshold,
Output LDO shutdown signal, the power channel corresponding to closedown, and after awaiting a specified time, make LDO
Shutdown signal is invalid, makes power channel output effectively.
Power supply voltage stabilizing chip selects LT1764EQ and digital regulation resistance AD5292BRUZ-50.Current amplifier
Can be chosen with the high-side current amplifying device MAX4372 of high common mode disturbances rejection ability.On and off switch is optional
Use electromagnetic type relay.
The core of electric current and electric voltage observation circuit is D/A converting circuit.16 are had at present on power module upper plate
Road analog voltage signal, the most every road power channel electric current, voltage signal.16 road analog voltage letters
Number collection can employ 2 MAX1168 and realize.
Master control FPGA design it is crucial that ensureing on the basis of electric current, voltage tester accuracy, it is ensured that cross stream
The response time of protection, it is to avoid the device caused due to latch up effect burns.Additionally which user selects lead to
It is random that road uses, and idle channel should not carry out the test of electric current, voltage in this case.Therefore lead
FPGA is relatively complicated to MAX1168 in control.Its control flow (see Figure 11) is as follows:
(1) generating a two-dimentional depositor array in master control FPGA, this array has 8 row, correspondence 8
Power channel, has 9 depositors in every a line, be respectively as follows: status register STT_R (2, read-only,
Be respectively switching-on and switching-off state position PSTS, guard mode position ProtSts), control depositor CTL_R (4,
Read-write, respectively current monitoring enables position CurrEn, voltage monitoring enables position VoltEn, power supply off-position
PSTS, locking monitoring enable position SelEn), channel position depositor POS_R (8, read-only, respectively electricity
Stream, the ADC device simulation channel number that voltage signal corresponding A DC device number, electric current, voltage are corresponding), electricity
Stream threshold register CURRTH_R (16, only write), guard time arrange depositor SETTIME_R
(16, only write), locking number of times depositor SELNUM_R (16, read-only), measured current value are posted
Storage CURR_R (16, read-only), actual measurement voltage value register VOLT_R (16, read-only),
Guard time depositor PROTTIME_R (16, read-only).
(2) reset before radiation SELNUM_R, CURR_R, the VOLT_R in all power channel and
PROTTIME_R, default reset value is 0.CTL_R, CURRTH_R and SETTIME_R are set.
(3), after receiving and starting test instruction, according to channel number from small to large, after first current channel, voltage leads to
The order in road circulates the conversion being simulated digital quantity successively.Only when the electricity checked in CTL_R during conversion
It is effective that stream monitoring or voltage monitoring enable position, and when guard mode position is invalid, just changes, and otherwise enters
The conversion of next passage.After EOC, transformation result is updated CURR_R and VOLT_R.
(4) check that locking monitoring enables position the most effective, if effective ratio is compared with measured current value and current threshold
Size, when measured value > threshold value time, disconnect this channel power source, locking number of times register value adds 1, forwards step to
(3) conversion of next passage is carried out.Start timer simultaneously, and timing result is updated when protecting
Inter-register, when timing time reaches the value that guard time arranges in depositor, recovers power supply output, makes
Guard mode position is invalid.
(5) main control module can read locking number of times in step (3) with step (4) as required at any time
Depositor, measured current value register, actual measurement voltage value register intermediate value.
(6), after receiving end test instruction, SELNUM_R intermediate value is read, it is thus achieved that measured device is at spoke
Locking number of times during according to.Off-test.
The control software of system uses modularized design, comprises main interface, power module arranges interface, IO mould
Block arranges interface, DUT controls, display processes interface etc. with data.Power module can be freely called at main interface
Arrange interface, I/O module arranges interface, measured device controls, display and the interface such as data process.Described electricity
Source module arranges interface, to arrange interface be two basic interfaces to I/O module, can be called by its interface.Power supply mould
Block arrange interface for arrange circuit-under-test test needed for power channel, supply voltage, latching current threshold value,
The latch-up protection time etc.；Open or off power channel.I/O module arranges interface for arranging or display system
The state of existing I/O module in local computer, such as current I/O module quantity, each module is the most measurable
Part category, output and input level value, IO clock frequency, module enabled state etc..DUT controls, display
Processing interface from data and have different interfaces for the digital circuit of different types, it controls, shows and number
The concrete radiation effect method of testing of measurand is depended on according to processing method.The control software of system is in order to drop
The difficulty of low secondary system exploitation, utilizes dynamic link library mode to provide more than 50 basic function, utilizes this
A little functions can quickly develop DUT control for concrete circuit-under-test, display processes interface with data.
It is the flow chart of Modularized digital integrated circuit radiation effect on-line testing method as shown in Figure 7, Figure 8:
Comprise the following steps:
1) carrying out secondary system exploitation, step is:
1.1) according to the testing requirement of DUT, the circuit types in the master control FPGA of I/O module is determined；
1.2) in amendment master control FPGA, DUT controls and test electronic circuit；
1.3) amended circuit is carried out comprehensive and placement-and-routing, and download in master control FPGA；
1.4) write control for circuit-under-test and data process, display software interface；
1.5) debugging verification experimental verification；
2) use system carries out radiation effect test, and step includes:
2.1) according to circuit-under-test classification, the required number of modules of the existing module number of local computer and test is checked
The difference of amount, during number of modules deficiency, inserts new module, updates master control FPGA in I/O module time enough
Interior configuration memory content；
2.2) connection system, and ensure that local computer is not by direct irradiation；
2.3) system of opening controls main interface, arranges the supply voltage of power channel needed for circuit-under-test test
And calibrate；Latching current threshold value and the latch-up protection time etc. of required passage are set；Open test required
Power channel, check irradiation on board supply voltage the most normal；
2.4) check whether the circuit configured in master control FPGA in I/O module is applicable to circuit-under-test, if
Inapplicable, then return step (2.1)；If there being unnecessary I/O module, then close all of unnecessary I/O module
Function；
2.5) corresponding circuit is opened automatically according to I/O module and power module configuring condition in the main interface of system
Radiation effect test interface；
2.6) the required depositor of circuit-under-test effect test and parameter are set；
2.7) while starting irradiation, the radiation effect parameter testing of circuit is started, until off-test.
Claims (8)
1. a Modularized digital integrated circuit radiation effect Online Transaction Processing, including remote computer, basis
Ground computer and irradiation plate, described local computer is not illuminated, it is characterised in that:
Described local computer is a kind of computer running embedded OS, including a master control mould
Block, at least one analog I/O module and at least one power module；
Described remote computer realizes the control to local computer, described master control by Desktop Share and Ethernet
Module is in communication with each other with analog I/O module and power module respectively by bus between plate, described analog I/O module
Being in communication with each other with measured device irradiation plate by signal cable, described power module passes through feed cable and irradiation
Plate connects；
Described main control module undertakes following functions:
A. it is responsible for making the mutually coordinated work of modules in local computer, it is achieved the radiation to measured device is imitated
Should test；
B. it is responsible for the process to radiation effect data, preserves and show；
C. it is responsible for realizing display interface, preserving data and the teleengineering support with host computer；
D. embedded OS is run；
Described analog I/O module is the multi-channel drive signal needed for circuit-under-test offer, and compares circuit-under-test
Output and the difference of expected value, then produce system break when variant or detailed data cached, waiting main
The reading of control module；The online real-time, tunable of the direction of multi-channel drive signal, level, clock and sequential；
Described power module is the voltage needed for circuit-under-test offer, line output voltage of going forward side by side, the prison of static current of lcd
Survey, and possess current protecting function.
Modularized digital integrated circuit radiation effect Online Transaction Processing the most according to claim 1, its
It is characterised by:
Described I/O module includes EBI between plate, clock circuit, test vector memorizer, program and data
Memorizer, I/O port level and direction adjust circuit and master control FPGA；
Described master control FPGA by between plate between EBI and plate bus be in communication with each other, described master control FPGA divides
Not being in communication with each other with test vector memorizer, program and data storage, described master control FPGA passes through IO end
Mouth level and direction adjust circuit and are in communication with each other with measured device irradiation plate；Described master control FPGA and clock electricity
Road connects；
Turning between local bus in EBI mainly realizes intermodule transfer bus and I/O module between described plate
Change, for the data exchange interface of master control FPGA with communication one standard of offer of intermodule bus；
Described clock circuit is mainly by local bus clock, FPGA master clock and I/O signal clock three part group
Become；Described local bus clock is divided into two-way to be respectively supplied to EBI between master control FPGA and plate；FPGA
Master clock is supplied to master control FPGA, master control FPGA and accesses test vector memorizer, data and program storage
Clock all use this clock；The frequency of described I/O signal clock is the most adjustable, adjusts IO letter in real time
Number clock, with the demand of satisfied different circuit-under-tests test frequencies, its control signal is produced by master control FPGA
Raw, produced clock signal is input in master control FPGA；
Described test vector memorizer is mainly used in storing the test vector of I/O channel, is made up of 2 RAM,
The a piece of input vector memorizer as DUT, another sheet is as expected value vector memorizer；
Described program and data storage in master control FPGA during Embeded CPU core as program storage
And data storage；
Described I/O port level and direction adjust circuit and are used for the online level adjusting I/O port in real time and direction,
The output I/O signal level making I/O module is consistent with the incoming level of circuit-under-test, I/O module input signal with
The incoming level of master control FPGA is consistent, thus realizes the compatibility to varying level measured device；
The data exchange that described master control FPGA is responsible between Bus Interface Chip, receives what main control module sent
Order and data, it is achieved the test sequence of measured device, control other circuit in I/O module.
Modularized digital integrated circuit radiation effect Online Transaction Processing the most according to claim 2, its
It is characterised by:
Configurable three kinds of circuit in master control FPGA:
(1) universal circuit: include in FPGA local bus interface, IO clock control, IO Automatic level control,
DUT controls and tests electronic circuit, and described DUT controls mainly to comprise DUT with test and drives generation, DUT
Output monitoring, DUT signal three parts of distribution；In addition to DUT controls with test electronic circuit, other electronic circuit
Designing user inaccessible and change；DUT controls to provide basic template, interface with test electronic circuit
Can not change, and provide standard electronic circuit for SRAM, FLASH, SRAM type FPGA；
Described IO clock control, IO Automatic level control, DUT drive generation and DUT output monitoring to pass through respectively
Between local bus interface with plate, EBI is connected, and the output of described IO clock control is connected with clock circuit,
The input of described IO Automatic level control receives the measured power level signal adjusting circuit from I/O port level and direction,
The output transmission level of described IO Automatic level control adjusts control signal and adjusts circuit to I/O port level and direction；
Described DUT drives the distribution of the output and the DUT signal that produce to be connected, input that described DUT output is monitored and
DUT signal distribution connects；DUT signal distribution adjusts circuit with I/O port level and direction and is connected；
When configuring universal circuit, I/O module EBI between plate receives data or the life that main control module is issued
Order, is converted to local bus in plate, local bus in master control FPGA by the bus interface circuit in I/O module
Interface then receives data or order from local bus, and these data or order is believed according to the address in bus
Write in the trigger specified after breath decoding；The process that data are uploaded to main control module is contrary with this process；
(2) CPU core circuit: this circuit is to be embedded in soft core at FPGA or utilize the stone in FPGA,
Local bus interface, IO clock control, IO Automatic level control, program and data memory interface, DUT control
All it is articulated in the bus of this CPU core with the form of standard IP kernel with electronic circuits such as tests；
Configure this circuit time, local bus interface receive main control module send data or order time, with in
CPU core is informed in disconnected formation, then data are distributed to the circuit specified by CPU core；The passback of its data
Journey is in contrast；
(3) circuit based on test vector: this circuit employs the test vector memorizer in I/O module, this
Time test vector memorizer in two panels RAM, a piece of input vector memorizer as DUT, another sheet
As expected value vector memorizer；The value of output vector memorizer comes from two kinds of situations, and one is by master control
Module is write direct, and one is before radiation effect is tested, the DUT output signal of write actual samples；
Include in master control FPGA that local bus interface, IO clock control, IO Automatic level control, wrong data are delayed
The distribution of storage, output comparator, DUT signal, FIFO1 and FIFO2；Described IO clock control, IO
Automatic level control, wrong data buffer are connected, during described IO by EBI between local bus interface with plate
The outfan of clock is connected with clock circuit, and the input of described IO Automatic level control receives from I/O port electricity
Flat and direction adjusts the measured power level signal of circuit, and the output transmission level of described IO Automatic level control adjusts and controls
Signal adjusts circuit to I/O port level and direction；
Described FIFO1 is connected with expected value vector memorizer, and described FIFO2 is connected with input vector memorizer,
Described FIFO1 and FIFO2 is also connected with local bus interface；Described FIFO1 and FIFO2 also receives
From the IO clock of clock circuit；
The outfan of described FIFO1 is connected with the input of output comparator, the outfan of described FIFO2 and DUT
The input of signal distribution connects, and the output of DUT signal distribution is connected with the input of comparator, and DUT signal divides
Join and be connected with I/O port level and direction adjustment circuit；
During use, user determines the content of test vector memorizer, vector length and defeated before radiation effect is tested
Go out frequency, during test, from test vector memorizer, sequential read out test vector and be stored in FIFO, if defeated
When outgoing vector number reaches vector length, then return first vector and continue to put out vector successively, until receiving
Test END instruction；After FIFO receives data, then it is sequentially output according to set vectorial output frequency；
IO clock control and IO level control circuit in master control FPGA are used for producing the outer IO of master control FPGA
Port level and direction adjust the control sequential needed for circuit；DUT drives generation predominantly DUT to provide institute
The input signal needed；DUT output monitoring be mainly used in comparing DUT output valve and expected value, when both not
Meanwhile, statistics upset number, and by the details press-in fifo buffer of mistake, wait master control mould
The access of block；DUT signal distribution arranges DUT input, output signal and the corresponding relation of concrete I/O channel.
Modularized digital integrated circuit radiation effect Online Transaction Processing the most according to claim 3, its
It is characterised by:
Described I/O port level adjusting circuit includes exporting adjustable linear voltage regulator, digital regulation resistance, ADC
And level translator, digital regulation resistance adjusts resistance, linear voltage regulator as the output voltage of linear voltage regulator
Output voltage be level translator be connected with tested DUT survey supply voltage；
When needing to adjust level, master control FPGA produces the control signal of digital regulation resistance, regulates digital regulation resistance
Resistance, thus the output voltage of linear adjustment manostat, ADC gathers output under master control FPGA controls
Magnitude of voltage, master control FPGA is by constantly adjusting digital regulation resistance resistance, and magnitude of voltage and expectation are surveyed in comparison
Magnitude of voltage, it is achieved the closed loop control to output voltage.
5. according to a kind of Modularized digital integrated circuit radiation effect described in claim 1 or 2 or 3 or 4
Online Transaction Processing, it is characterised in that:
Described power module is made up of power supply master control FPGA, electric current and voltage monitoring and DUT power supply,
Described DUT power supply comprises multiple identical power channel, and each passage all includes linear voltage regulator, number
Word potentiometer, current amplifier and on and off switch；
The output of described linear voltage regulator can be by the adjustable realization output electricity of external digital regulation resistance resistance value
The adjustment of pressure；Described current amplifier is to concatenate little resistance on the output lead of linear voltage regulator, and with high
The current amplifier of common mode rejection ratio converts electrical current into voltage；Described on and off switch is used for controlling power channel
Whether export；
Described electric current and electric voltage observation circuit core are analog-digital converter, for by the voltage of every road power supply, electricity
Circulation is changed to digital quantity；
Described power supply master control FPGA has a following function:
(1) for regulating the resistance of digital regulation resistance；
(2) the control sequential of ADC device is provided, makes ADC device can circulate in DUT irradiation process
The conversion voltage of user's dedicated tunnel, electric current, and read transformation result at any time；
(3) electric current transformation result is compared in real time with the value in current threshold register, when conversion value is big
When current threshold, output linearity manostat shutdown signal, the power channel corresponding to closedown, and wait refer to
After the fixed time, make linear voltage regulator shutdown signal invalid, make power channel output effectively.
A kind of Modularized digital the most according to claim 5 integrated circuit radiation effect on-line testing system
System, it is characterised in that:
The control software of local computer uses modularized design, comprise main interface, power module arranges interface,
I/O module arranges interface, DUT controls interface and display processes interface with data；
Described main interface can freely call that power module arranges interface, I/O module arranges interface, measured device control
System, display process interface with data；
Described power module arranges interface, to arrange interface be two basic interfaces to I/O module, can be by other interface
Call；
Described power module arrange interface for arrange circuit-under-test test needed for power channel, supply voltage,
Latching current threshold value, latch-up protection time；Open or off power channel；
Described I/O module arranges interface for arranging or the shape of existing I/O module in display system local computer
State；
Described DUT controls interface, display has not for the digital circuit of different types from data process interface
Same interface, its control, display and data processing method depend on the concrete radiation effect test of measurand
Method.
A kind of Modularized digital the most according to claim 6 integrated circuit radiation effect on-line testing system
System, it is characterised in that:
The control software of local computer utilizes dynamic link library mode to provide more than 50 basic function, described
Basic function can quickly develop DUT control for concrete circuit-under-test, display processes interface with data.
8. a Modularized digital integrated circuit radiation effect on-line testing method, it is characterised in that: include with
Lower step:
1) carrying out secondary system exploitation, step is:
1.1) according to the testing requirement of DUT, the circuit types in the master control FPGA of I/O module is determined；
1.2) in amendment master control FPGA, DUT controls and test electronic circuit；
1.3) amended circuit is carried out comprehensive and placement-and-routing, and download in master control FPGA；
1.4) write control for circuit-under-test and data process, display software interface；
1.5) debugging verification experimental verification；
2) use system carries out radiation effect test, and step includes:
2.1) according to circuit-under-test classification, the required number of modules of the existing module number of local computer and test is checked
The difference of amount, during number of modules deficiency, inserts new module, time enough, updates master control FPGA in I/O module
Interior configuration memory content；
2.2) connection system, and ensure that local computer is not by direct irradiation；
2.3) system of opening controls main interface, arranges the supply voltage of power channel needed for circuit-under-test test
And calibrate；Latching current threshold value and the latch-up protection time of required passage are set；Needed for opening test
Power channel, checks that irradiation on board supply voltage is the most normal；
2.4) check whether the circuit configured in master control FPGA in I/O module is applicable to circuit-under-test, if
Inapplicable, then return step (2.1)；If there being unnecessary I/O module, then close all of unnecessary I/O module
Function；
2.5) corresponding circuit is opened automatically according to I/O module and power module configuring condition in the main interface of system
Radiation effect test interface；
2.6) the required depositor of circuit-under-test effect test and parameter are set；
2.7) while starting irradiation, the radiation effect parameter testing of circuit is started, until off-test.
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