CN111308328A - Low-frequency digital circuit comprehensive test system and test method thereof - Google Patents
Low-frequency digital circuit comprehensive test system and test method thereof Download PDFInfo
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Abstract
The invention discloses a low-frequency digital circuit comprehensive test system and a test method thereof, and the system comprises a test interaction unit, a data processing system, a tested board test unit and a standard board test unit, wherein the data processing system is respectively in bidirectional electrical connection with the test interaction unit, the tested board test unit and the standard board test unit, and the data processing system is in bidirectional connection with a networking large database through an optical fiber network or a 4G wireless network. The low-frequency digital circuit comprehensive test system and the test method thereof can realize that when a large quantity of circuit boards with large test capacity are tested, data processing can still be carried out rapidly, the test efficiency is greatly improved, the test error is small, the accuracy of the test result is ensured, meanwhile, the data analysis time is greatly shortened, the data processing efficiency is improved, a large amount of time is not required for the test personnel to wait, and therefore, the data processing work of the test personnel is greatly facilitated.
Description
Technical Field
The invention relates to the technical field of circuit test systems, in particular to a low-frequency digital circuit comprehensive test system and a test method thereof.
Background
The digital circuit is a circuit which uses digital signals to complete arithmetic operation and logic operation on digital quantity, and is called as a digital circuit or a digital system, and because the digital circuit has logic operation and logic processing functions, the digital circuit is also called as a digital logic circuit, and according to different requirements of different industries and fields, low-frequency digital circuit test objects are often different, so that the performance requirements of the digital circuit on the test system are different, for example, a small-scale simple digital circuit used in a direct-current variable-frequency air conditioner requires that the test system meets the requirements of channel number and lower test frequency; due to high requirements on data processing speed, the large radar base station has high requirements on the number of channels, the test frequency and the reliability of a test system by related electronic equipment, and the requirements often reach hundreds of channels and tens of megahertz; the onboard equipment of modern warplanes also has the test requirement for different aviation communication buses, so that the design of a digital circuit test system with high performance, high reliability, multiple functions and low cost is necessary.
Referring to a digital array radar DAM receiving digital circuit test system with Chinese patent application No. CN201610082893.8, the test system can test indexes such as signal-to-noise ratio, noise coefficient, channel isolation, inter-channel amplitude consistency and the like of a plurality of channels of a receiving digital circuit in parallel, thereby greatly improving the test efficiency of the receiving digital circuit and realizing rapid and accurate test, however, the reference patent has the following defects:
1) when the circuit board test device is used for testing circuit boards with large batch and large test capacity, the speed is still low, the test efficiency is low, the aim of testing the circuit boards with large batch and large capacity can not be achieved by establishing a targeted fault model according to the test requirement and directly loading the fault model into the circuit board, the purpose of shortening the test time by saving a large amount of test vector generation time can not be achieved, and great inconvenience is brought to the test of the circuit boards.
2) The test error is still large, the test error caused by human factors in the test process cannot be reduced, and the problem of inaccuracy of the test result caused by the human test error cannot be solved by adopting a mode that the standard board and the tested board are simultaneously installed and tested.
3) The data analysis time is long, the efficiency is low, the intelligent degree of data analysis can not be improved, the test data can be analyzed more quickly and accurately, the purpose of carrying out ordered matching processing on various kinds of data can not be achieved by adopting a self-adaptive processing algorithm, and a tester needs to spend a large amount of time to wait, so that great inconvenience is brought to the data processing work of the tester.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects of the prior art, the invention provides a low-frequency digital circuit comprehensive test system and a test method thereof, which solve the problems that the speed is still slower, the test efficiency is lower, the test error is still larger, the test error caused by human factors in the test process cannot be reduced, the data analysis time is long, and the processing efficiency is low when the conventional test system is used for testing circuit boards with large batch and large test capacity.
(II) technical scheme
In order to achieve the purpose, the invention is realized by the following technical scheme: a low-frequency digital circuit comprehensive test system comprises a test interaction unit, a data processing system, a tested board test unit and a standard board test unit, wherein the data processing system is respectively and electrically connected with the test interaction unit, the tested board test unit and the standard board test unit in a bidirectional way, the data processing system is connected with a networking big database in a bidirectional way through an optical fiber network or a 4G wireless network, the data processing system is connected with a remote test monitoring terminal in a wireless bidirectional way through a wireless communication module, the data processing system comprises a central processing module, a test fault modeling unit, a test vector generation module, a test vector loading module and a test data comparison and analysis unit, the central processing module is respectively and electrically connected with the test vector generation module and the test data comparison and analysis unit in a bidirectional way, and the output end of the central processing module is electrically connected with the input end of the test fault modeling unit, the output end of the test vector loading module is electrically connected with the input end of the central processing module.
The test data comparison and analysis unit comprises a micro-processing module, a data transceiving module, a self-adaptive analysis algorithm library module, a self-adaptive algorithm extraction module, a test data self-adaptive analysis unit, a multi-standard data matching analysis module, a standard data optimization module and a data real-time updating module, wherein the micro-processing module is respectively in bidirectional electric connection with the data transceiving module, the self-adaptive analysis algorithm library module, the self-adaptive algorithm extraction module, the test data self-adaptive analysis unit, the multi-standard data matching analysis module, the standard data optimization module and the data real-time updating module.
Preferably, the test data adaptive analysis unit comprises a tested data extraction module, a standard data extraction module, a matching type data comparison module, a difference range analysis module and a fault type judgment module, and the output ends of the tested data extraction module and the standard data extraction module are electrically connected with the input end of the matching type data comparison module.
Preferably, the output end of the matching type data comparison module is electrically connected with the input end of the difference range analysis module, and the output end of the difference range analysis module is electrically connected with the input end of the fault type determination module.
Preferably, the test fault modeling unit includes a fault type induction module, a fault logic diagram drawing module, a fault algorithm editing module, a fault model generation module and a fault model test module, wherein an output end of the fault type induction module is electrically connected with an input end of the fault logic diagram drawing module, and an output end of the fault logic diagram drawing module is electrically connected with an input end of the fault algorithm editing module.
Preferably, the output end of the fault algorithm editing module is electrically connected with the input end of the fault model generating module, and the output end of the fault model generating module is electrically connected with the input end of the fault model testing module.
Preferably, the test interaction unit comprises a user login module, a test data entry module, a data display module, a test model revision module, a test model verification module and a test model sending module.
Preferably, the board test unit under test is composed of n board test modules under test, and the standard board test unit is composed of n standard board test modules.
Preferably, the test fault modeling unit is in bidirectional connection with the networked big database, the output end of the test fault modeling unit is electrically connected with the input end of the test vector generation module, and the output end of the test vector generation module is electrically connected with the input end of the test vector loading module.
The invention also discloses a test method of the low-frequency digital circuit comprehensive test system, which specifically comprises the following steps:
s1, login of the user and installation of the tested board: firstly, login operation is carried out through a user login module in a test interaction unit, after login is successful, a circuit board to be tested and a standard circuit board are respectively installed on a tested board test unit and a standard board test unit, and then a central processing module controls a test fault modeling unit to carry out fault modeling processing through operating the test interaction unit;
s2, test fault modeling: firstly, carrying out information induction and sorting on fault types to be tested of the tested circuit board through a fault type induction module in a test fault modeling unit, drawing a fault modeling logic flow chart through a fault logic diagram drawing module, editing the drawn logic diagram through a fault algorithm editing module or importing a processing algorithm corresponding to the logic diagram from a networking large database, carrying out error checking and generating processing on the edited algorithm through a fault model generating module, and testing and processing the generated fault model through a fault model testing module after the fault model is generated;
s3, fault modeling and loading of test vectors: transmitting the fault model successfully tested in the step S2 to a test vector generation module, and introducing fault data into the fault model to generate a fault index code, which is a test vector, and then transmitting the generated test vector to a test vector loading module, and loading the test vector to the tested circuit board and the standard circuit board installed in the step S1 through a central processing module, respectively, to perform a fault test;
s4, standard test data optimization: the data tested in the step S3 is transmitted to a test data comparison and analysis unit, a micro-processing module in the test data comparison and analysis unit is controlled by a central processing module to control a data transceiver module to receive the test data and transmit the received data of the tested board to a test data adaptive analysis unit, then the test data of the standard board is transmitted to a multi-standard data matching and analysis module to be matched with the fault type of the standard board, standardized processing is performed by a standard board data optimization module, and the optimized test data of the standard fault is transmitted to the test data adaptive analysis unit to be analyzed;
s5, comparative analysis of test data: at the moment, a measured data extraction module and a standard data extraction module in a test data adaptive analysis unit respectively extract measured data and standard test data, the extracted data are transmitted to a matching type data comparison module, the matching type data comparison module extracts a particle swarm analysis algorithm from an adaptive analysis algorithm library module through the adaptive algorithm extraction module to perform data comparison analysis, after comparison, the difference value range analysis module analyzes whether the difference value between a measured value and a standard value exceeds a standard difference value range, if the difference value exceeds the standard difference value range, the tested circuit board is judged to be a fault board, and the fault type judgment module judges the fault type, and the same operation can be performed on a plurality of groups of tested boards simultaneously;
s6, checking the test result and correcting the test model: and sending the test result obtained in the step S5 to a central processing module through a data transceiver module, sending the test result to a test interaction unit through a central processing film or wirelessly sending the test result to a remote test monitoring terminal through a wireless communication module for a tester to check, displaying the test data after receiving the test data by a test data entry module in the test interaction unit through a data display module, revising the test model through a revision algorithm in a test model revision module when the tester needs to modify the test model, testing the test model through a test model verification module, and sending the revised model to a data processing system through a test model sending module after the test is qualified for testing.
Preferably, in step S4, the received board-under-test data and standard board test data are updated in real time by the data real-time updating module.
(III) advantageous effects
The invention provides a low-frequency digital circuit comprehensive test system and a test method thereof. Compared with the prior art, the method has the following beneficial effects:
(1) the data processing system comprises a central processing module, a test fault modeling unit, a test vector generation module, a test vector loading module and a test data comparison and analysis unit, wherein the central processing module is respectively in bidirectional electrical connection with the test vector generation module and the test data comparison and analysis unit, the output end of the central processing module is electrically connected with the input end of the test fault modeling unit, the output end of the test vector loading module is electrically connected with the input end of the central processing module, the test of large-batch and large-capacity circuit boards can be realized by firstly establishing a specific fault model according to test requirements and directly loading the fault model into the circuit board, and the aim of shortening the test time by saving a large amount of test vector generation time is well fulfilled, even when the circuit boards with large batch and large test capacity are tested, the data processing can still be carried out quickly, the test efficiency is greatly improved, and the test of the circuit boards is very beneficial.
(2) The low-frequency digital circuit comprehensive test system and the test method thereof solve the problem of inaccurate test results caused by artificial test errors by adopting a mode that the standard board and the tested board are simultaneously installed and tested by forming the tested board test unit by n tested board test modules and forming the standard board test unit by n standard board test modules, the test errors are reduced, the test errors caused by the artificial factors in the test process are greatly reduced, and the accuracy of the test results is ensured.
(3) The comprehensive test system of the low-frequency digital circuit and the test method thereof realize bidirectional electrical connection with the data transceiver module, the adaptive analysis algorithm library module, the adaptive algorithm extraction module, the test data adaptive analysis unit, the multi-standard data matching analysis module, the standard data optimization module and the data real-time update module respectively by the test data comparison and analysis unit comprising the micro-processing module, the data transceiver module, the adaptive analysis algorithm library module, the test data adaptive analysis unit, the multi-standard data matching analysis module, the standard data optimization module and the data real-time update module, can realize that the test data can be analyzed more quickly and accurately by improving the intelligent degree of data analysis, and well achieves the aim of adopting the adaptive processing algorithm, the purpose of orderly matching and processing various kinds of data is achieved, data analysis time is greatly shortened, data processing efficiency is improved, a large amount of time is not needed for testers to wait, and therefore data processing work of the testers is greatly facilitated.
Drawings
FIG. 1 is a schematic block diagram of the architecture of the system of the present invention;
FIG. 2 is a schematic block diagram of the architecture of a data processing system of the present invention;
FIG. 3 is a schematic block diagram of the structure of the test data comparison and analysis unit according to the present invention;
FIG. 4 is a schematic block diagram of the structure of the adaptive analysis unit for test data according to the present invention;
FIG. 5 is a schematic block diagram of the structure of a test interaction unit according to the present invention;
FIG. 6 is a schematic block diagram of the structure of a test failure modeling unit of the present invention;
FIG. 7 is a logic diagram of the test algorithm of the present invention;
FIG. 8 is a flow chart of a test method of the present invention;
FIG. 9 is a schematic diagram of the particle swarm adaptive algorithm of the present invention;
FIG. 10 is a program code diagram of the particle swarm adaptive algorithm of the present invention.
In the figure, 1 test interaction unit, 11 user login module, 12 test data entry module, 13 data display module, 14 test model revision module, 15 test model verification module, 16 test model transmission module, 2 data processing system, 21 central processing module, 22 test fault modeling unit, 221 fault type induction module, 222 fault logic diagram drawing module, 223 fault algorithm editing module, 224 fault model generation module, 225 fault model test module, 23 test vector generation module, 24 test vector loading module, 25 test data comparison analysis unit, 251 microprocessing module, 252 data transceiver module, 253 adaptive analysis algorithm library module, 254 adaptive algorithm extraction module, 255 test data adaptive analysis unit, 2551 measured data extraction module, 2552 standard data extraction module, 2553 matching type data comparison module, 2554 difference range analysis module, 2555 fault type judgment module, 256 multi-standard data matching analysis module, 257 standard data optimization module, 258 data real-time updating module, 3 tested board test unit, 4 standard board test unit, 5 networking big database, 6 wireless communication module, 7 remote test monitoring terminal.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 10, an embodiment of the present invention provides a technical solution: a low-frequency digital circuit comprehensive test system comprises a test interaction unit 1, a data processing system 2, a tested board test unit 3 and a standard board test unit 4, wherein the tested board test unit 3 and the standard board test unit 4 comprise a jig for mounting a circuit board and a wiring pin on the jig, the data processing system 2 is respectively in bidirectional electric connection with the test interaction unit 1, the tested board test unit 3 and the standard board test unit 4, the data processing system 2 is in bidirectional connection with a networking big database 5 through an optical fiber network or a 4G wireless network, the data processing system 2 is in wireless bidirectional connection with a remote test monitoring terminal 7 through a wireless communication module 6, the wireless communication module 6 is a 4G wireless communication network, the data processing system 2 comprises a central processing module 21, a test fault modeling unit 22, a test vector generating module 23, a test vector generating module 3 and a standard board test unit 4, The test vector loading module 24 and the test data comparison and analysis unit 25, the model of the central processing module 21 is ARM9, the central processing module 21 is respectively and electrically connected with the test vector generation module 23 and the test data comparison and analysis unit 25 in a bidirectional manner, the output end of the central processing module 21 is electrically connected with the input end of the test fault modeling unit 22, the output end of the test vector loading module 24 is electrically connected with the input end of the central processing module 21, the test fault modeling unit 22 comprises a fault type induction module 221, a fault logic diagram drawing module 222, a fault algorithm editing module 223, a fault model generation module 224 and a fault model test module 225, the output end of the fault type induction module 221 is electrically connected with the input end of the fault logic diagram drawing module 222, and the output end of the fault logic diagram drawing module 222 is electrically connected with the input end of the fault algorithm editing module 223, the output end of the fault algorithm editing module 223 is electrically connected to the input end of the fault model generating module 224, the output end of the fault model generating module 224 is electrically connected to the input end of the fault model testing module 225, the fault type induction module 221 in the test fault modeling unit 22 induces and collates the information of the fault type to be tested of the circuit board to be tested, the fault logic diagram drawing module 222 draws the fault modeling logic flow diagram, the fault algorithm editing module 223 edits the drawn logic diagram or imports the corresponding processing algorithm from the networked big database 5, the fault model generating module 224 performs the error-checking generation processing on the edited algorithm, the generated fault model is tested by the fault model testing module 225 after the fault model is generated, the test interaction unit 1 comprises a user login module 11, a user interface module 2, a user interface module 11, a user, A test data entry module 12, a data display module 13, a test model revision module 14, a test model verification module 15, and a test model transmission module 16, when the tester needs to make changes to the test model, the test model is revised by a revision algorithm in the test model revision module 14, then the test model verification module 15 is used for test processing, after the test is qualified, the test model sending module 16 is used for transmitting the corrected model to the data processing system 2 for test use, the tested board test unit 3 is composed of n tested board test modules, the standard board testing unit 4 is composed of n standard board testing modules, the testing fault modeling unit 22 is in bidirectional connection with the networking big database 5, and the output terminal of the test failure modeling unit 22 is electrically connected to the input terminal of the test vector generation module 23, and the output terminal of the test vector generating module 23 is electrically connected to the input terminal of the test vector loading module 24.
The test data contrast analysis unit 25 comprises a micro-processing module 251, a data transceiver module 252, an adaptive analysis algorithm library module 253, an adaptive algorithm extraction module 254, a test data adaptive analysis unit 255, a multi-standard data matching analysis module 256, a standard data optimization module 257 and a data real-time update module 258, wherein the micro-processing module 251 is respectively in bidirectional electrical connection with the data transceiver module 252, the adaptive analysis algorithm library module 253, the adaptive algorithm extraction module 254, the test data adaptive analysis unit 255, the multi-standard data matching analysis module 256, the standard data optimization module 257 and the data real-time update module 258, the micro-processing module 251 in the test data contrast analysis unit 25 controls the data transceiver module 252 to receive test data, transmits the received tested board data to the test data adaptive analysis unit 255, and transmits the standard board test data to an advanced standard board fault test in the multi-standard data matching analysis module 256 The result and fault type matching process, the standard board data optimizing module 257 carries out standardization process, the optimized standard fault test data is transmitted to the test data adaptive analysis unit 255 for analysis process, the real-time data updating module 258 carries out real-time update process on the received tested board test data and the standard board test data, the test data adaptive analysis unit 255 comprises a tested data extracting module 2551, a standard data extracting module 2552, a matching type data comparing module 2553, a difference range analyzing module 2554 and a fault type judging module 2555, the output ends of the tested data extracting module 2551 and the standard data extracting module 2552 are electrically connected with the input end of the matching type data comparing module 2553, the output end of the matching type data comparing module 2553 is electrically connected with the input end of the difference range analyzing module 2554, and the output end of the difference range analyzing module 2554 is electrically connected with the input end of the fault type judging module 2555, the measured data extraction module 2551 and the standard data extraction module 2552 in the test data adaptive analysis unit 255 respectively extract measured data and standard test data, and transmit the extracted data to the matching type data comparison module 2553, at this time, the matching type data comparison module 2553 extracts a particle swarm analysis algorithm from the adaptive analysis algorithm library module 253 through the adaptive algorithm extraction module 254 for data comparison analysis, after comparison, the difference range analysis module 2554 analyzes whether the difference between the measured value and the standard value exceeds the standard difference range, if the difference exceeds the standard difference range, the tested circuit board is determined to be a fault board, and the fault type determination module 2555 determines the fault type, and the same operation can simultaneously perform test analysis on a plurality of groups of tested boards.
The invention also discloses a test method of the low-frequency digital circuit comprehensive test system, which specifically comprises the following steps:
s1, login of the user and installation of the tested board: firstly, login operation is carried out through a user login module 11 in a test interaction unit 1, after login is successful, a circuit board to be tested and a standard circuit board are respectively installed on a tested board test unit 3 and a standard board test unit 4, and then a central processing module 21 controls a test fault modeling unit 22 to carry out fault modeling processing through operating the test interaction unit 1;
s2, test fault modeling: firstly, the fault type to be tested of the circuit board to be tested is induced and collated through a fault type induction module 221 in the test fault modeling unit 22, then a fault logic diagram is drawn through a fault logic diagram drawing module 222, then a corresponding processing algorithm is edited according to the drawn logic diagram through a fault algorithm editing module 223 or is imported from a networking big database 5, then the edited algorithm is subjected to debugging generation processing through a fault model generation module 224, and the generated fault model is tested through a fault model testing module 225 after the fault model is generated;
s3, fault modeling and loading of test vectors: transmitting the fault model successfully tested in the step S2 to the test vector generation module 23, and introducing fault data into the fault model to generate a fault index code, which is a test vector, and then transmitting the generated test vector to the test vector loading module 24, and then loading the test vector to the tested circuit board and the standard circuit board installed in the step S1 through the central processing module 21, respectively, to perform a fault test;
s4, standard test data optimization: the data tested in step S3 is transmitted to the test data contrastive analysis unit 25, the central processing module 21 controls the micro-processing module 251 in the test data contrastive analysis unit 25 to control the data transceiver module 252 to receive the test data, and transmits the received board data to the test data adaptive analysis unit 255, and then transmits the board test data to the multi-standard data matching analysis module 256 to perform matching processing between the board fault test result and the fault type, and performs standardization processing by the board data optimization module 257, and transmits the optimized board test data to the test data adaptive analysis unit 255 to perform analysis processing, and performs real-time update processing on the received board test data and the board test data by the data real-time update module 258;
s5, comparative analysis of test data: at this time, the measured data extraction module 2551 and the standard data extraction module 2552 in the test data adaptive analysis unit 255 respectively extract measured data and standard test data, and transmit the extracted data to the matching type data comparison module 2553, at this time, the matching type data comparison module 2553 extracts a particle swarm analysis algorithm from the adaptive analysis algorithm library module 253 through the adaptive algorithm extraction module 254 for data comparison analysis, and after comparison, the difference between the measured value and the standard value is analyzed through the difference range analysis module 2554 whether to exceed the standard difference range, if the difference exceeds the standard difference range, the tested circuit board is determined to be a fault board, and through the fault type determination module 2555, the same operation can be performed on a plurality of groups of tested boards at the same time;
s6, checking the test result and correcting the test model: the test result obtained in step S5 is sent to the central processing module 251 through the data transceiver module 252, and then sent to the test interaction unit 1 through the central processing film 251 or wirelessly transmitted to the remote test monitoring terminal 7 through the wireless communication module 6 for the tester to check, the test data entry module 12 in the test interaction unit 1 receives the test data and then displays the test data through the data display module 13, when the tester needs to change the test model, the test model is revised through the revision algorithm in the test model revision module 14, then the test model is tested and processed through the test model verification module 15, and after the test is qualified, the revised model is transmitted to the data processing system 2 through the test model sending module 16 for testing and use.
As can be seen from fig. 9-10, the adaptive data processing algorithm uses the particle swarm algorithm for processing, the particle swarm algorithm can creatively select two elements of speed and position as model information, replacing individuals in the set with particles flying at a certain speed without mass and volume in physical space, dynamically adjusting the flying speed v and the current position x of the particles by the flying experience of the individuals and the population, collaborating the population to achieve the aim of searching food, wherein the current position and the current speed of each particle are in each generation of evolution, the optimal solution is gradually approached by continuously being attracted by two position components of local optimal and global optimal, the local optimal is the best position through which the particles individually pass, the global optimal is the best position through which all the particles pass, and the local optimal is to prevent the phenomenon that the algorithm is converged too early to generate precocity due to the fact that the particles are individually attracted by the global optimal.
Particle formula: when these two optimal values are found, the particle updates its velocity and new position according to the following formula:
v [ ] + c1 + rand () (pbest [ ] -present [ ]) + c2 + rand () (gbest [ ] -present [ ]) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
present [ ] = present [ ] + v [ ] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
v [ ] is the velocity of the particle, w is the inertial weight, present [ ] is the position of the current particle, pbest [ ] and gbest [ ], as defined before, rand () is a random number between (0, 1), c1 and c2 are learning factors, typically c1= c2= 2.
Compared with other algorithms, the particle swarm algorithm has the advantages that the speed factor is kept, the particle swarm algorithm has many excellent characteristics, the algorithm design is simple, the solving process is rapid, and the resource cost is low.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. The utility model provides a low frequency digital circuit integrated test system, includes test interactive unit (1), data processing system (2), is surveyed board test unit (3) and standard board test unit (4), data processing system (2) realize two-way electric connection with test interactive unit (1), is surveyed board test unit (3) and standard board test unit (4) respectively, and data processing system (2) realize two-way connection through optical network or 4G wireless network and networking big database (5), data processing system (2) realize wireless two-way connection through wireless communication module (6) and remote test monitor terminal (7), its characterized in that: the data processing system (2) comprises a central processing module (21), a test fault modeling unit (22), a test vector generating module (23), a test vector loading module (24) and a test data comparison and analysis unit (25), wherein the central processing module (21) is respectively in bidirectional electrical connection with the test vector generating module (23) and the test data comparison and analysis unit (25), the output end of the central processing module (21) is electrically connected with the input end of the test fault modeling unit (22), and the output end of the test vector loading module (24) is electrically connected with the input end of the central processing module (21);
the test data comparison and analysis unit (25) comprises a micro-processing module (251), a data transceiver module (252), an adaptive analysis algorithm library module (253), an adaptive algorithm extraction module (254), a test data adaptive analysis unit (255), a multi-standard data matching analysis module (256), a standard data optimization module (257) and a data real-time updating module (258), wherein the micro-processing module (251) is respectively in bidirectional electric connection with the data transceiver module (252), the adaptive analysis algorithm library module (253), the adaptive algorithm extraction module (254), the test data adaptive analysis unit (255), the multi-standard data matching analysis module (256), the standard data optimization module (257) and the data real-time updating module (258).
2. A low frequency digital circuit comprehensive test system according to claim 1, characterized in that: the self-adaptive analysis unit (255) for the test data comprises a tested data extraction module (2551), a standard data extraction module (2552), a matching type data comparison module (2553), a difference range analysis module (2554) and a fault type judgment module (2555), wherein the output ends of the tested data extraction module (2551) and the standard data extraction module (2552) are electrically connected with the input end of the matching type data comparison module (2553).
3. A low frequency digital circuit comprehensive test system according to claim 2, characterized in that: the output end of the matching type data comparison module (2553) is electrically connected with the input end of the difference range analysis module (2554), and the output end of the difference range analysis module (2554) is electrically connected with the input end of the fault type judgment module (2555).
4. A low frequency digital circuit comprehensive test system according to claim 1, characterized in that: the test fault modeling unit (22) comprises a fault type induction module (221), a fault logic diagram drawing module (222), a fault algorithm editing module (223), a fault model generation module (224) and a fault model testing module (225), wherein the output end of the fault type induction module (221) is electrically connected with the input end of the fault logic diagram drawing module (222), and the output end of the fault logic diagram drawing module (222) is electrically connected with the input end of the fault algorithm editing module (223).
5. The system of claim 4, wherein the integrated test system comprises: the output end of the fault algorithm editing module (223) is electrically connected with the input end of the fault model generating module (224), and the output end of the fault model generating module (224) is electrically connected with the input end of the fault model testing module (225).
6. A low frequency digital circuit comprehensive test system according to claim 1, characterized in that: the test interaction unit (1) comprises a user login module (11), a test data entry module (12), a data display module (13), a test model revision module (14), a test model verification module (15) and a test model sending module (16).
7. A low frequency digital circuit comprehensive test system according to claim 1, characterized in that: the tested board testing unit (3) is composed of n tested board testing modules, and the standard board testing unit (4) is composed of n standard board testing modules.
8. A low frequency digital circuit comprehensive test system according to claim 1, characterized in that: the test fault modeling unit (22) is in bidirectional connection with the networking big database (5), the output end of the test fault modeling unit (22) is electrically connected with the input end of the test vector generation module (23), and the output end of the test vector generation module (23) is electrically connected with the input end of the test vector loading module (24).
9. A method for testing a low frequency digital circuit comprehensive test system according to any one of claims 1 to 8, characterized in that: the method specifically comprises the following steps:
s1, login of the user and installation of the tested board: firstly, login operation is carried out through a user login module (11) in a test interaction unit (1), after login is successful, a circuit board to be tested and a standard circuit board are respectively installed on a tested board test unit (3) and a standard board test unit (4), and then a central processing module (21) controls a test fault modeling unit (22) to carry out fault modeling processing through operating the test interaction unit (1);
s2, test fault modeling: firstly, a fault type induction module (221) in a test fault modeling unit (22) induces and collates information of a fault type to be tested of the tested circuit board, then a fault logic diagram drawing module (222) draws a fault modeling logic flow diagram, then a fault algorithm editing module (223) edits according to the drawn logic diagram or imports a processing algorithm corresponding to the logic diagram from a networking big database (5), then a fault model generating module (224) conducts debugging generation processing on the edited algorithm, and a fault model testing module (225) conducts testing processing on the generated fault model after the fault model is generated;
s3, fault modeling and loading of test vectors: transmitting the fault model successfully tested in the step S2 to a test vector generation module (23) and introducing fault data into the fault model to generate a fault index code, which is a test vector, transmitting the generated test vector to a test vector loading module (24), and loading the test vector to the tested circuit board and the standard circuit board installed in the step S1 through a central processing module (21) respectively to perform a fault test;
s4, standard test data optimization: the data tested in the step S3 is transmitted to the test data comparison and analysis unit (25), the central processing module (21) controls the micro-processing module (251) in the test data comparison and analysis unit (25) to control the data transceiver module (252) to receive the test data, transmits the received tested board data to the test data adaptive analysis unit (255), transmits the standard board test data to the multi-standard data matching and analysis module (256) to perform matching processing of the standard board fault test result and the fault type, performs standardization processing through the standard board data optimization module (257), and transmits the optimized standard fault test data to the test data adaptive analysis unit (255) to perform analysis processing;
s5, comparative analysis of test data: at the moment, a measured data extraction module (2551) and a standard data extraction module (2552) in a test data adaptive analysis unit (255) respectively extract measured data and standard test data, the extracted data are transmitted to a matching type data comparison module (2553), the matching type data comparison module (2553) extracts a particle swarm analysis algorithm from an adaptive analysis algorithm library module (253) through an adaptive algorithm extraction module (254) to perform data comparison analysis, after comparison, whether the difference value between the measured value and the standard value exceeds a standard difference value range is analyzed through a difference value range analysis module (2554), if the difference value exceeds the standard difference value range, the measured circuit board is judged to be a fault board, and the fault type is judged through a fault type judgment module (2555), and the same operation can simultaneously perform test analysis on a plurality of groups of measured boards;
s6, checking the test result and correcting the test model: the test result obtained in step S5 is sent to the central processing module (251) through the data transceiver module (252), then the test data is sent to the test interaction unit (1) through the central processing film (251) or is wirelessly transmitted to the remote test monitoring terminal (7) through the wireless communication module (6) for being checked by a tester, the test data is displayed through the data display module (13) after being received by the test data entry module (12) in the test interaction unit (1), when the tester needs to change the test model, the test model is revised through a revision algorithm in the test model revision module (14), and then, the test model is tested by a test model verification module (15), and the corrected model is transmitted to the data processing system (2) for test use by a test model transmitting module (16) after the test is qualified.
10. The method for testing the low-frequency digital circuit comprehensive test system according to claim 9, wherein the method comprises the following steps: and in the step S4, the received board to be tested and standard board test data are updated in real time by the data real-time updating module (258).
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