CN107797816A - FPGA program online updating circuits - Google Patents
FPGA program online updating circuits Download PDFInfo
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- CN107797816A CN107797816A CN201710835513.8A CN201710835513A CN107797816A CN 107797816 A CN107797816 A CN 107797816A CN 201710835513 A CN201710835513 A CN 201710835513A CN 107797816 A CN107797816 A CN 107797816A
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Abstract
A kind of FPGA programs online updating circuit disclosed by the invention, it is desirable to provide one kind can reduce hardware cost, and loading velocity is fast, the online updating circuit of loose coupling.The technical scheme is that：Packets transceiver accesses Integrated system by data/address bus, and bag fever writes connect FLASH by BPI；When data/address bus has FPGA routine datas bag to reach packets transceiver, packet is output to Packet analyzing device and parsed by packets transceiver, and the bag programming result that bag fever writes export is transferred into Integrated system；When the packet of packets transceiver output reaches Packet analyzing device, the completeness and efficiency of Packet analyzing device inspection bag, treating programming address, treat programming length and treating programming data output to bag fever writes for complete effectively bag data will be extracted；Bag fever writes by length be treat programming length treat that programming data write FLASH by BPI and treated in programming address, verify programming result, output programming result to packets transceiver.
Description
Technical field
The present invention relates to Integrated system general signal processing module field, and in particular to one kind is led to based on Integrated system
With the circuit and method of signal processing module FPGA program online updatings.
Background technology
The avionics system of high integrity is on the basis of synthetic aviation electronic system, is by numeral further
The comprehensive thinking of system is applied to aperture and the channel processing section of system, realizes modularization and the synthesization of whole system.It is special
It from the angle of hardware resource is difficult to distinguish the function devices such as radar, communication that point, which is, and most of function is all by leading in system
Fill different software with module to realize, in information processing aspect, realize different sensors are obtained target data,
The fusion of graphic data and threat data, there is provided as automatic target detection, threat level assessment, high confidence level information processing energy
Power, system become more intelligent, significantly reduce the operational load of pilot.Integrated system is extremely complex, because its
Bandwidth of operation will meet big bandwidth and Larger Dynamic area requirement simultaneously, and its function should can support floating-point concurrent operation, prop up again
Fixed point serial arithmetic is held, its transmission network should possess broadband transmission characteristics, possess low transmission time-delay characteristics again.These are complicated
Property to system architecture design, network design, processor design and channel design bring it is many challenge, it is necessary to consider module simultaneously
Generalization, the flexibility of network topology, the concurrency for handling computing etc. realize.With the continuous improvement of system complexity,
It is found that the drawbacks of software and hardware is separated into independent design, exploitation is more and more obvious：Software and hardware, which influences each other, to be assessed,
It is the system integration, difficult in maintenance.In the synthetical electronics information system of Multisensor Measurement data is handled with central fusion, Chang Hui
There is the Non-order matrix phenomenon that each sensor metric data is not reached fusion center by normal sequential.Processor processing is this kind of unordered
Negative time replacement problem can be run into during metric data.Synthesization electronic information signal processing platform mainly includes general at present
Data processing module (DPM), general signal processing module (SPM), network exchange module (RCM), system control module (SCM) and
High speed Mass storage module (MMM).Module is divided with designing in functional unit, it then follows module general utility functions frame requirements are entered
OK.Module general utility functions frame requirements are：Each module is by module supporter (MSU), processing unit (PU), routing unit
(RU), the unit such as NIU (NIU), power supply support part (PSE), module physical interface (MPI) forms, and realizes module
The standardised genericization of hardware circuit designs with synthesization.Each module is divided into different work(according to the difference of processing unit
Can module.General signal processing module forms processing unit by typical signal processor DSP/FPGA, and FPGA utilizes hardware simultaneously
Capable advantage, has broken the pattern that order performs, and more processing tasks are completed within each clock cycle, have surmounted DSP's
Operational capability；And FPGA faster rings in hardware view control input and output (I/O) to meet that application demand provides
With specialized function between seasonable, therefore, the signal processing module that processing unit is made up of FPGA is formed FPGA type signals
Processing module.
In practical engineering application, it can run into often to solve the BUG of some product, it is necessary in engineering site more new equipment
FPGA code, or participate in telecommunications test when need field upgrade equipment FPGA programs in order to debug.FPGA program codes
Typically deposit in the supporting FLASH memory of chip, and it is common in printed board FLASH programming there is several methods that, it is original
Method be to use programmable device, this method needs to remove chip, is inconvenient, or be connected to PC by jtag interface
On machine, but need specific download software (typically being provided by chip production manufacturer).At test site or commissioning computer room scene, to look for
Specific download line to FPGA is relatively difficult.Sometimes research and development or customer service people are just needed only for updating FPGA program
Member goes programming program to scene in person, and this was both inconvenient, also cost of equipment maintenance is greatly increased.In utility system, more
Come more products the online updating of FPGA programs is completed by the intrinsic communication interface of product.
At present, FPGA programs online updating has following two schemes.
The .FPGA function programs of scheme one include FPGA program online updating modules, and FPGA is realized by online updating module
Program is updated into the plug-in memories of FPGA.
The .FPGA program storages of scheme two realize FPGA program online updatings in the plug-in memories of DSP, by DSP.
There is the following shortcoming in some existing schemes：
In one, schemes one, because FPGA program online updating modules are built in FPGA function programs, not only increase application of function
With the coupling of program online updating, valuable FPGA internal resources are also taken up.
In two, schemes two, the program for realizing FPGA by DSP loads, because FPGA program storages are in the plug-in memories of DSP
In, FPGA loading can only just use passive loading mode, i.e., only read FPGA programs by DSP and be output to FPGA programs
Loading interface, realize that FPGA programs load.Although program FPGA programs online updating realizes simple, FPGA programs loading
Realization then becomes complicated, it is often more important that the speed that FPGA is passively loaded is more more slowly than actively loading.
Three, schemes one and scheme two, which are all based on DSP, to be realized, single in no DSP FPGA type signal processing modules
Solely one DSP of increase realizes that FPGA program online updatings not only increase cost, and increases system complexity.
The content of the invention
The purpose of the present invention in view of the shortcomings of the prior art part, there is provided one kind can reduce hardware cost, loading
Speed is fast, loose coupling, FPGA program online updating circuits and its online updating method independent of DSP.
To achieve the above objectives, the present invention provides a kind of FPGA programs online updating circuit, including：It is connected electrically in synthesization
On-site programmable gate array FPGA and module supporter MSU between system and FLASH chip, wherein, MSU includes programmable
PSPLIF buses read write line, FLASH blocks selector and FPGA program Loading Controls built in logic PL and processor system PS, PL
Device, FLASH blocks include FPGA program online updating programs where block, FPGA program online updatings program bag containing packets transceiver,
Packet analyzing device and bag fever writes, it is characterised in that：Packets transceiver accesses Integrated system by data/address bus, and bag fever writes pass through
BPI connections FLASH；When data/address bus has FPGA routine datas bag to reach packets transceiver, packet is output to by packets transceiver
Packet analyzing device is parsed, and the bag that Packet analyzing device is exported transmits result or is transferred to the bag programming result that bag fever writes export
Integrated system；When packets transceiver output packet reach Packet analyzing device when, the integrality of Packet analyzing device inspection bag and effectively
Property, treating programming address, treat programming length and treating programming data output to bag fever writes for complete effectively bag data will be extracted；When
Packet analyzing device is exported when programming address, when programming length and when programming data reach bag fever writes, and length is by bag fever writes
That treats programming length treats that programming data are treated in programming address by BPI write-in FLASH, verifies programming result, exports programming knot
Fruit is to packets transceiver.
A kind of FPGA program online updating methods using foregoing circuit, it is characterised in that comprise the following steps：PS is received
The dynamic load instruction of FPGA program online updating programs is loaded, will be by default tile number (where FPGA program online updatings program
Block) write-in FLASH block selectors, select default tile be the currently active piece；PS is by PSPLIF buses read write line to FPGA journeys
Sequence Loading Control device writes 1, FPGA program Loading Control devices and loads flow by controlling FPGA PROG pins to start FPGA, adds
Carry FPGA programs in FLASH default tiles, the DONE signals by judging FPGA confirm the loading of FPGA program online updatings programs into
Work(；PS reports FPGA program online updating programs to load successfully, and programming FLASH blocks number are treated in reception, are read and write by PSPLIF buses
Device will treat that programming FLASH blocks number write FLASH block selectors, and selection treats programming FLASH blocks as the currently active piece, and reporting module is done
The preparation of FPGA online updatings is got well；FPGA packets transceiver receives online updating packet, and bag is output into Packet analyzing device, Bao Xie
The completeness and efficiency of parser inspection bag determines transmission result and exports transmission result to packets transceiver, if complete effective,
Extract and treat programming address, treat programming length and treat programming data output to bag fever writes；Packets transceiver sends transmission result, bag
Fever writes by length be treat programming length treat that programming data write FLASH by BPI and treated in programming address, verify programming knot
Fruit, output programming result to packets transceiver send programming result.
The present invention has the advantages that compared to prior art：
Reduce hardware cost.The present invention is using the field-programmable gate array being connected electrically between Integrated system and FLASH chip
The FPGA program online updating circuits that FPGA and module supporter MSU is formed are arranged, the MSU that module carries is borrowed, overcomes existing
There is technology individually to increase a DSP and realize FPGA program online updatings, increase cost, the defects of system complexity.
It is decoupling.The present invention accesses Integrated system controlling bus using PS by controlling bus, and packets transceiver passes through number
Integrated system data/address bus is accessed according to bus, FPGA routine datas bag is passed through by data bus transmission, other control instructions
Controlling bus is transmitted, and is realized the separation of data and control instruction, is reduced coupling.
Discord function program seizes internal resource.The present invention is used and is connected electrically between Integrated system and FLASH chip
On-site programmable gate array FPGA and module supporter MSU form FPGA program online updating circuits, pass through pack receiving and transmitting
Device realizes the reception of FPGA routine datas, and Packet analyzing device realizes the parsing of FPGA routine datas, and bag fever writes realize FPGA programs
Data programming, FPGA program online updatings program are simply loaded into FPGA in FPGA online updatings by dynamic load mode,
Exclusive FPGA internal resources, but when FPGA function programs are run, FPGA program online updating programs will be removed from FPGA,
FPGA function programs monopolize whole FPGA internal resources, avoid prior art FPGA program online updating modules and are built in FPGA
Function program, increase application of function and the coupling of program online updating, take the weak point of the FPGA internal resources of preciousness.
The speed of active loaded in parallel is fast.The present invention using FPGA by FPGA loaded in parallel interface BPI connection FLASH,
FLASH blocks selector is led to respectively by the high n bit address pins of the connected FLASH of n roots address, FPGA program Loading Control devices
Cross output discrete lines connection FPGA PROG pins, two output discrete lines connect FPGA INIT pins and DONE is managed
Pin；After choosing the currently active piece by FLASH block selectors, FPGA bootstrap loading streams are started by FPGA program Loading Controls device
Journey, the FPGA programs that FPGA will actively be read in the currently active piece by loaded in parallel interface BPI, complete loading；It is actively parallel
Load relative to passive loading velocity faster.
Brief description of the drawings
Further illustrate technical scheme below in conjunction with the accompanying drawings, but the content protected of the present invention be not limited to
It is lower described.
Fig. 1 is the FPGA program online updating circuit theory schematic diagrams of the present invention.
Fig. 2 is Fig. 1 FPGA program online updating flow chart schematic diagrames.
Embodiment
Refering to Fig. 1.In embodiment described below, a kind of FPGA programs online updating circuit, including：It is connected electrically in comprehensive
On-site programmable gate array FPGA and module supporter MSU between combination system and FLASH chip, wherein, MSU is included can
PSPLIF buses read write line, FLASH blocks selector and the loading control of FPGA programs built in programmed logic PL and processor system PS, PL
Device processed, FLASH blocks include the block where FPGA program online updating programs, and FPGA program online updatings program bag contains pack receiving and transmitting
Device, Packet analyzing device and bag fever writes.Packets transceiver accesses Integrated system by data/address bus, and bag fever writes are connected by BPI
FLASH；When data/address bus has FPGA routine datas bag to reach packets transceiver, packet is output to Packet analyzing device by packets transceiver
Parsed, the bag transmission result that Packet analyzing device exports is transferred to Integrated system, or, the bag that bag fever writes are exported burns
Write result and be transferred to Integrated system；When the packet of packets transceiver output reaches Packet analyzing device, Packet analyzing device inspection bag
Completeness and efficiency determines transmission result and exports transmission result to packets transceiver, if complete effective, the extraction of Packet analyzing device
Go out to treat programming address, treat programming length and treat programming data output to bag fever writes；Programming address is treated when Packet analyzing device exports, is treated
Programming length and when programming data reach bag fever writes, bag fever writes by length be treat programming length treat that programming data pass through
BPI write-in FLASH's treats in programming address, verifies programming result, output programming result to packets transceiver.
Integrated system is accessed in processor system PS one end by controlling bus, and the other end connects PSPLIF by PSPLIF
Bus read write line；FPGA passes through FPGA loaded in parallel interface BPI connections FLASH.PSPLIF buses read write line passes through processor system
System PS PSPLIF bus connected processor systems PS；FLASH blocks selector is by the high n positions of n address connection FLASH
Location pin；FPGA program Loading Control devices are connected by the PROG pins of an output discrete lines and FPGA；FPGA programs load
Controller is connected by INIT the and DONE pins of two input discrete lines and FPGA.
After PSPLIF bus read write lines receive PS calling-on signal, the FLASH blocks number of FLASH block selectors, FLASH are set
The low and high level that the high n bit address lines of FLASH are contoured to correspond to by block selector by n roots address, to choose corresponding blocks
Number FLASH blocks be the currently active piece, or after receiving PS calling-on signal, the value of FPGA program Loading Control devices is set to
1；PROG pins by exporting discrete line traffic control FPGA are started FPGA bootstrap loading flows by FPGA program Loading Control devices；
After FLASH block selectors receive the block number of PSPLIF bus control units setting, by n roots address by the high n positions of FLASH
The low and high level that address wire is contoured to correspond to, to choose the FLASH blocks of corresponding blocks number as the currently active piece.PSPLIF buses are read and write
The PSPLIF bus connected processor systems PS that device passes through processor system PS；FLASH blocks selector is connected by n address
Connect the high n bit address pins of FLASH；FPGA program Loading Controls device passes through an output discrete lines and two input discrete lines respectively
Connect FPGA PROG pins, INIT pins and DONE pins.
Refering to Fig. 2.FPGA program online updating circuits receive the dynamic of loading FPGA program online updating programs by PS
Loading instruction, PS control PL selection acquiescence FLASH, selecting acquiescence FLASH blocks by PSPLIF buses read write line, (FPGA programs exist
Block where line more new procedures) it is the currently active piece, by acquiescence FLASH blocks number write-in FLASH block selectors；PS passes through PSPLIF
The PROG pins that bus read write line writes 1, FPGA program Loading Controls device control FPGA to FPGA program Loading Controls device start
FPGA loads flow, loads FPGA programs in FLASH default tiles；It is height that PS, which waits FPGA DONE signals, to confirm FPGA journeys
Sequence online updating program loads successfully.PS judges whether the DONE signals of FPGA before time-out uprise, and is not that PS reports FPGA programs
The loading failure of online updating program, is that PS reports FPGA program online updating programs to load successfully；PS is received and is treated programming FLASH
Block number, it will treat that programming FLASH blocks number write FLASH block selectors by PSPLIF buses read write line, programming FLASH blocks are treated in selection
For the currently active piece；PS reporting modules have carried out the preparation of FPGA online updatings.In FPGA program online updating programs, FPGA's
Packets transceiver receives online updating packet and is output to Packet analyzing device, and the completeness and efficiency of Packet analyzing device inspection bag determines
Transmission result simultaneously exports transmission result to packets transceiver, and packets transceiver, which is sent, transmits result, and Packet analyzing device judges whether bag is complete
Effectively, no, it is bust this to report transmission result, returns to packets transceiver and receives online updating packet and be output to Packet analyzing
Device, be report transmission result be transmission success；Then extracted by Packet analyzing device and treat programming address, treated programming length and treat
Programming data output to bag fever writes, bag fever writes by length be treat programming length treat that programming data write FLASH by BPI
Treat in programming address, verify programming result, output programming result is to packets transceiver.
Circuit provided by the invention and method are described in detail below by 2 embodiments.
Embodiment 1：FLASH blocks include the block where FPGA program online updating programs；FLASH program online updating programs
Place block is divided into 16 pieces that block number is 0~15, and FPGA program online updating programs are placed in the FLASH blocks that block number is 15.MSU can
To use TI companies C2000 Series MCUs as PS, from CPLD as PL.
PS is connected by external interface XINTF connections PL, FPGA by BPI with FLASH, and PL passes through an output discrete lines
It is connected with FPGA PROG pins, PL is connected by INIT the and DONE pins of two input discrete lines and FPGA, and PL passes through 4
Address connects the high 4 bit address pins of FLASH, and PS accesses Integrated system controlling bus by CAN, and FPGA passes through
RapidIO buses access Integrated system data/address bus.
After PS receives the dynamic load instruction of loading FPGA program online updating programs by CAN, pass through PSPLIF
Block number 15 is write FLASH block selectors by bus read write line, and the FLASH blocks of selection block number 15 are the currently active piece.PS passes through
PSPLIF buses read write line writes 1, FPGA program Loading Control devices by controlling FPGA's to FPGA program Loading Controls device
PROG pins export high level after exporting 1 millisecond of low level and kept, and start FPGA loading flows, and loading blocks number are 15
FPGA programs in FLASH blocks, the DONE signals by judging FPGA confirm the loading of FPGA program online updatings program for high level
Success.If loading failure, PS reports the loading failure of FPGA program online updatings program by CAN, is transferred to and waits into one
Walk instruction state.If loaded successfully, PS reports FPGA program online updating programs to load successfully and after continuing by CAN
Afterflow journey.PS is received by CAN and is treated programming FLASH blocks number, it is assumed that the block number is that 0, PS passes through PSPLIF bus read write lines
FLASH block selectors are write by 0, the FLASH blocks for selecting block number to be 0 are the currently active piece.PS is carried out by CAN reporting module
FPGA online updatings prepare.Packets transceiver receives online updating packet by RapidIO buses and is output to Packet analyzing device.
The completeness and efficiency of Packet analyzing device inspection bag determines transmission result and exports transmission result to packets transceiver.Packets transceiver is led to
Cross RapidIO buses and send transmission result.If it is complete effectively, Packet analyzing device extracts and treats programming address, treat programming length and
Treat that programming data output to bag fever writes, otherwise continues waiting for RapidIO bus datas.Length is to treat that programming is grown by bag fever writes
Degree treats that programming data are treated in programming address by BPI write-in FLASH.Bag fever writes verify programming result, export programming knot
Fruit is to packets transceiver.Packets transceiver sends programming result by RapidIO buses, and continues waiting for RapidIO bus datas.On
It is all that MSU is controlled to state block selection and the loading of FPGA program online updating programs, and FPGA routine datas receive, parsing and burning
Write all is that FPGA program online updating programs are completed.
Embodiment 2：ASH blocks include the block where FPGA program online updating programs；FLASH program online updating programs institute
It is divided into 32 pieces that block number is 0~31 in block, FPGA program online updating programs are placed in the FLASH blocks that block number is 31.MSU is selected
XILINX companies ZYNQ family chips.PS of the PS parts of ZYNQ chips as MSU, the PL parts of ZYNQ chips are as MSU's
PL。
PS is connected with PL by the AXI buses of ZYNQ chip internals, and FPGA is connected by BPI with FLASH, and PL passes through one
The PROG pins for exporting discrete lines and FPGA are connected, and PL is connected by INIT the and DONE pins of two input discrete lines and FPGA
Connect, PL connects the high 5 bit address pins of FLASH by 5 address, and PS accesses Integrated system by TTP buses and controlled
Bus, FPGA access Integrated system data/address bus by PCIE buses.
After PS receives the dynamic load instruction of loading FPGA program online updating programs by TTP buses, pass through PSPLIF
Block number 31 is write FLASH block selectors by bus read write line, and the FLASH blocks of selection block number 31 are the currently active piece.PS passes through
PSPLIF buses read write line writes 1, FPGA program Loading Control devices by controlling FPGA's to FPGA program Loading Controls device
PROG pins export high level after exporting 1 millisecond of low level and kept, and start FPGA loading flows, and loading blocks number are 15
FPGA programs in FLASH blocks, the DONE signals by judging FPGA confirm the loading of FPGA program online updatings program for high level
Success.If loading failure, PS reports the loading failure of FPGA program online updatings program by TTP buses, is transferred to and waits into one
Walk instruction state.If loaded successfully, PS reports FPGA program online updating programs to load successfully and after continuing by TTP buses
Afterflow journey.PS is received by TTP buses and is treated programming FLASH blocks number, it is assumed that the block number is that 0, PS passes through PSPLIF bus read write lines
FLASH block selectors are write by 0, the FLASH blocks for selecting block number to be 0 are the currently active piece.PS is carried out by TTP bus reporting modules
FPGA online updatings prepare.Packets transceiver receives online updating packet by PCIE buses and is output to Packet analyzing device.Bag
The completeness and efficiency of resolver inspection bag determines transmission result and exports transmission result to packets transceiver.Packets transceiver passes through
PCIE buses send transmission result.If complete effective, Packet analyzing device, which extracts, to be treated programming address, treat programming length and treats programming
Otherwise data output continues waiting for PCIE bus datas to bag fever writes.Length is to treat that programming length is waited to burn by bag fever writes
Data are write to treat in programming address by BPI write-in FLASH.Bag fever writes verify programming result, and output programming result is received to bag
Send out device.Packets transceiver sends programming result by PCIE buses, and continues waiting for PCIE bus datas.Above-mentioned piece of selection and FPGA
The loading of program online updating program is all that MSU is controlled, and FPGA routine datas receive, and parsing and programming are all FPGA programs
What online updating program was completed.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (9)
1. a kind of FPGA programs online updating circuit, including：The scene being connected electrically between Integrated system and FLASH chip can
Gate array FPGA and module supporter MSU are programmed, wherein, MSU is included built in FPGA PL and processor system PS, PL
PSPLIF buses read write line, FLASH blocks selector and FPGA program Loading Control devices, it is online more that FLASH blocks include FPGA programs
Block where new procedures, FPGA program online updatings program bag contain packets transceiver, Packet analyzing device and bag fever writes, and its feature exists
In：Packets transceiver accesses Integrated system by data/address bus, and bag fever writes connect FLASH by BPI；When data/address bus has
When FPGA routine datas bag reaches packets transceiver, packet is output to Packet analyzing device and parsed by packets transceiver, by Packet analyzing
The bag programming result that bag fever writes export is transferred to Integrated system by the bag transmission result of device output；When packets transceiver exports
Packet when reaching Packet analyzing device, the completeness and efficiency of Packet analyzing device inspection bag, complete effective bag data will be extracted
Treat programming address, treat programming length and treat programming data output to bag fever writes；Programming address is treated when Packet analyzing device exports, is treated
Programming length and when programming data reach bag fever writes, bag fever writes by length be treat programming length treat that programming data pass through
BPI write-in FLASH's treats in programming address, verifies programming result, output programming result to packets transceiver.
2. FPGA programs online updating circuit as claimed in claim 1, it is characterised in that：Processor system PS one end passes through control
Bus processed accesses Integrated system, and the other end passes through PSPLIF connection PSPLIF bus read write lines；FPGA one end is total by data
Line accesses Integrated system, and the other end passes through FPGA loaded in parallel interface BPI connections FLASH.
3. FPGA programs online updating circuit as claimed in claim 1, it is characterised in that：PSPLIF bus read write lines pass through place
Manage device system PS PSPLIF bus connected processor systems PS；FLASH blocks selector connects FLASH by n address
High n bit address pin；FPGA program Loading Controls device is connected by an output discrete lines with two input discrete lines respectively
FPGA PROG pins, INIT pins and DONE pins.
4. FPGA programs online updating circuit as claimed in claim 1, it is characterised in that：PSPLIF bus read write lines receive PS
Calling-on signal after, set FLASH block selectors FLASH blocks number, FLASH blocks selector pass through n roots address will
The low and high level that the high n bit address lines of FLASH are contoured to correspond to, to choose the FLASH blocks of corresponding blocks number as the currently active piece, or
After the calling-on signal for receiving PS, the value of FPGA program Loading Control devices is set to 1；FPGA program Loading Control devices will be by defeated
Go out discrete line traffic control FPGA PROG pins, start FPGA bootstrap loading flows.
5. FPGA programs online updating circuit as claimed in claim 1, it is characterised in that：FLASH block selectors receive
After the block number that PSPLIF bus control units are set, the high n bit address lines of FLASH are contoured to correspond to by n roots address
Low and high level, to choose the FLASH blocks of corresponding blocks number as the currently active piece.
A kind of 6. FPGA program online updating methods using online updating circuit described in claim 1, it is characterised in that including
Following steps：PS receives the dynamic load instruction of loading FPGA program online updating programs, by FPGA program online updating programs
The default tile number write-in FLASH block selectors of place block, it is the currently active piece to select default tile；PS is read and write by PSPLIF buses
Device writes 1, FPGA program Loading Control devices by controlling FPGA PROG pins to start FPGA to FPGA program Loading Controls device
Flow is loaded, loads FPGA programs in FLASH default tiles, by judging that FPGA DONE signals confirm FPGA program online updatings
Program loads successfully；PS reports FPGA program online updating programs to load successfully, and programming FLASH blocks number are treated in reception, are passed through
PSPLIF buses read write line will treat that programming FLASH blocks number write FLASH block selectors, and selection treats programming FLASH blocks currently to have
Block is imitated, reporting module has carried out the preparation of FPGA online updatings；FPGA packets transceiver receives online updating packet, and bag is exported
To Packet analyzing device, the completeness and efficiency of Packet analyzing device inspection bag determines transmission result and exports transmission result to pack receiving and transmitting
Device, if complete effective, extract and treat programming address, treat programming length and treat programming data output to bag fever writes；Pack receiving and transmitting
Device sends transmission result, bag fever writes by length be treat programming length treat that programming data write FLASH by BPI and treat programming
In address, programming result is verified, output programming result to packets transceiver sends programming result.
7. FPGA programs online updating method as claimed in claim 6, it is characterised in that：Resolver is according to the knot for checking bag
Fruit, judge whether bag is complete effectively, it is no, the loading failure of FPGA program online updatings program is reported, packets transceiver is returned and receives
Line updated data package is simultaneously output to Packet analyzing device, is to report FPGA program online updating programs to load successfully, programming is treated in reception
FLASH blocks number, it will treat that programming FLASH blocks number write FLASH block selectors by PSPLIF buses read write line, programming is treated in selection
FLASH blocks are the currently active piece.
8. FPGA programs online updating method as claimed in claim 6, it is characterised in that：PS is received by controlling bus and loaded
After the dynamic load instruction of FPGA program online updating programs, by PSPLIF buses read write line by FPGA program online updating journeys
The block number write-in FLASH block selectors of block where sequence, the FLASH blocks where selecting FPGA program online updating programs are current
Active block；PS writes 1, FPGA program Loading Control devices to FPGA program Loading Controls device by PSPLIF buses read write line and passed through
Control FPGA PROG pins export high level after exporting 1 millisecond of low level and kept, and start FPGA loading flows, load FPGA
Program online updating program, the DONE signals by judging FPGA confirm the loading of FPGA program online updatings program for high level
Success；If loading failure, PS reports the loading failure of FPGA program online updatings program by controlling bus, is transferred to and waits into one
Walk instruction state；If loaded successfully, PS reports FPGA program online updating programs to load successfully and continued by controlling bus
Follow-up process；PS is received by controlling bus and is treated programming FLASH blocks number, and PS will treat programming by PSPLIF buses read write line
FLASH blocks number write FLASH block selectors, select block number to treat that the FLASH blocks of programming FLASH blocks number are the currently active piece.PS leads to
Cross controlling bus reporting module and carry out the preparation of FPGA online updatings.Above-mentioned piece of selection adds with FPGA program online updating programs
Load is all that MSU is controlled.
9. FPGA programs online updating method as claimed in claim 6, packets transceiver receive online updating by data/address bus
Packet is simultaneously output to Packet analyzing device.The completeness and efficiency of Packet analyzing device inspection bag determines transmission result and exports transmission knot
Fruit is to packets transceiver.Packets transceiver sends transmission result by data/address bus.If complete effective, Packet analyzing device, which extracts, to be waited to burn
Write address, treat programming length and treat that programming data output to bag fever writes, otherwise continues waiting for data/address bus data.Bag fever writes
By length be treat programming length treat that programming data write FLASH by BPI and treated in programming address.Bag fever writes verify programming
As a result, programming result is exported to packets transceiver.Packets transceiver sends programming result by data/address bus, and it is total to continue waiting for data
Line number evidence.Above-mentioned piece of FPGA routine data receives, and parsing and programming are all that FPGA program online updating programs are completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710835513.8A CN107797816A (en) | 2017-09-15 | 2017-09-15 | FPGA program online updating circuits |
Applications Claiming Priority (1)
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| CN110069030A (en) * | 2019-04-16 | 2019-07-30 | 湖南必然网络科技有限公司 | A kind of unmanned aerial vehicle (UAV) control core buckle |
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| CN112269585A (en) * | 2020-11-04 | 2021-01-26 | 配天机器人技术有限公司 | Joint driver firmware online updating method and device and joint driver |
| CN113312098A (en) * | 2020-04-01 | 2021-08-27 | 阿里巴巴集团控股有限公司 | Program loading method, device, system and storage medium |
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| CN112199315A (en) * | 2020-09-28 | 2021-01-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | RapidIO network management device and network management method of integrated electronic information system |
| CN112199315B (en) * | 2020-09-28 | 2023-10-20 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Comprehensive electronic information system rapidIO network management device and network management method |
| CN112269585A (en) * | 2020-11-04 | 2021-01-26 | 配天机器人技术有限公司 | Joint driver firmware online updating method and device and joint driver |
| CN112269585B (en) * | 2020-11-04 | 2022-11-25 | 配天机器人技术有限公司 | Joint driver firmware online updating method and device and joint driver |
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