CN107301256B - Verification method and device of integrated circuit - Google Patents
Verification method and device of integrated circuit Download PDFInfo
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- CN107301256B CN107301256B CN201610239448.8A CN201610239448A CN107301256B CN 107301256 B CN107301256 B CN 107301256B CN 201610239448 A CN201610239448 A CN 201610239448A CN 107301256 B CN107301256 B CN 107301256B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Abstract
The embodiment of the invention discloses a verification method and a device of an integrated circuit, wherein the method comprises the following steps: acquiring a port to be checked in each file to be checked of the integrated circuit; determining a port path of the integrated circuit according to all the ports to be checked; and when a preset matched starting point and end point are found in the port path of the integrated circuit, judging that the integrated circuit is connected and passed.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a verification method and apparatus for an integrated circuit.
Background
The integrated circuit verification is an indispensable important component in integrated circuit design and is used for judging whether the design specification is consistent with the implementation, ensuring the functions described in the specification document of actual design and implementation, finding out the logic defects in the functional modules and ensuring the correctness of the design logic. With the rapid development of the integrated circuit industry, the diversity and complexity of the integrated circuit design are higher and higher, and the design scale and efficiency of the traditional engineering verification method is behind the development scale, so that the difficulty of the integrated circuit verification is higher and higher.
At present, the verification method for the integrated circuit mainly includes two means, namely, dynamic simulation and formal verification, wherein the verification method based on the dynamic simulation is as follows: inputting various test signals at one end of the integrated circuit, and detecting at the other end of the connection; the correctness of the connection is proved by comparing whether the two are consistent; the verification method based on formal verification comprises the following steps: the constraint conditions are written in advance, the algorithm traverses various conditions of the integrated circuit through the constraint conditions, and the integrated connection can be always met under the constraint conditions, so that the accuracy of integration is proved.
In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art:
because the dependency of the verification method of dynamic simulation on the input test signal is strong, and the type of the test signal may not be comprehensive enough, the verification method of dynamic simulation may have a case that the verification result is not reliable, that is: although the verification result passes, an error exists in the actual connection, so that the confidence degree of the verification result cannot reach 100% by adopting a dynamic simulation verification method; for the formal verification method, if the design scale of the integrated circuit is too large, the situations that the time consumption is too long or the algorithm cannot be converged occur.
Disclosure of Invention
In order to solve the existing technical problems, embodiments of the present invention provide a method and an apparatus for verifying an integrated circuit, which can not only improve the confidence of the verification result of the integrated circuit, but also improve the verification efficiency of the integrated circuit.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:
the embodiment of the invention provides a verification method of an integrated circuit, which comprises the following steps:
acquiring a port to be checked in each file to be checked of the integrated circuit;
determining a port path of the integrated circuit according to the ports to be verified of all the files to be verified;
and when a preset matched starting point and end point are found in the port path of the integrated circuit, judging that the integrated circuit is connected and passed.
In the above embodiment, the acquiring the to-be-verified ports in each to-be-verified file of the integrated circuit includes:
selecting an unverified file from a preset file list as a current file to be verified;
and acquiring all ports to be checked of the current file to be checked.
In the above embodiment, the determining the port path of the integrated circuit according to the ports to be verified of all the files to be verified includes:
selecting an unverified port from all the ports to be verified as a current port to be verified;
determining a port path of the current port to be checked;
and determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
In the above embodiment, the determining the port path of the current port to be verified includes:
searching the current port to be checked in the current file to be checked as a keyword, and determining the current instance of the current port to be checked;
determining an instance and a port for instance calling through the current port to be checked and the current instance;
and determining the port path of the current port to be checked according to the instance and the port which are called by the instance and the current instance.
In the above embodiment, before the determining the port path of the port to be checked currently, the method further includes:
judging whether the depth of the current instance where the current port to be checked is called by a preset top-layer instance is greater than a preset depth threshold value or not;
if yes, ending the determination of the port path of the current port to be checked.
An embodiment of the present invention provides a verification apparatus for an integrated circuit, including:
the device comprises an acquisition unit, a determination unit and a processing unit, wherein the acquisition unit is used for acquiring a port to be checked in each file to be checked of the integrated circuit and sending the port to be checked to the determination unit;
the determining unit is used for determining the port path of the integrated circuit according to all the ports to be checked and sending the port path of the integrated circuit to the judging unit;
and the judging unit is used for judging that the integrated circuit is connected and passed when a preset matched starting point and an end point are found in the port path of the integrated circuit.
In the above embodiment, the obtaining unit includes:
the first selection subunit is used for selecting an unverified file from a preset file list as a current file to be checked and sending the current file to be checked to the acquisition subunit;
and the obtaining subunit is configured to obtain all ports to be verified of the current file to be verified.
In the above embodiment, the determining unit includes:
the second selection subunit is used for selecting one unverified port from all the ports to be verified as a current port to be verified and sending the current port to be verified to the determination subunit;
the determining subunit is configured to determine a port path of the current port to be verified; and determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
In the above embodiment, the determining unit is further configured to search the current port to be checked in the current file to be checked as a keyword, and determine a current instance where the current port to be checked is located; determining an instance and a port for instance calling through the current port to be checked and the current instance; and determining the port path of the current port to be checked according to the instance and the port which are called by the instance and the current instance.
In the above embodiment, the determining unit is further configured to determine whether a depth, called by a preset top-level instance, of a current instance where the current port to be checked is located is greater than a preset depth threshold; if yes, ending the determination of the port path of the current port to be checked.
Therefore, in the technical scheme of the embodiment of the invention, all the ports to be checked in each file to be checked of the integrated circuit are firstly obtained, then the port paths of the integrated circuit are determined according to all the ports to be checked, and when the preset matched starting point and end point are found in the port paths of the integrated circuit, the connection of the integrated circuit is judged to be passed. In the technical scheme of the embodiment of the invention, various test signals do not need to be input at the end connected with the integrated circuit, and the constraint condition does not need to be programmed in advance; in contrast, in the prior art, the verification method of dynamic simulation has strong dependence on the input test signal, the confidence of the verification result cannot reach 100%, and the formal verification method cannot be applied to large-scale design of circuits. Therefore, compared with the prior art, the verification method and the verification device for the integrated circuit, which are provided by the embodiment of the invention, not only can improve the confidence of the verification result of the integrated circuit, but also can improve the verification efficiency of the integrated circuit; moreover, the method is simple and convenient to realize, convenient to popularize and wide in application range.
Drawings
FIG. 1 is a schematic diagram illustrating an implementation flow of a verification method for an integrated circuit according to an embodiment of the invention;
fig. 2 is a schematic flow chart of an implementation method for obtaining the to-be-verified port of each to-be-verified file in the embodiment of the present invention;
FIG. 3 is a flow chart illustrating an implementation method for determining a port path of an integrated circuit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a first connection relationship of a current port to be verified in the embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating a second connection relationship of a current port to be verified according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a third connection relationship of a current port to be verified in the embodiment of the present invention;
fig. 7 is a schematic flowchart of an implementation method for determining a port path of a current port to be verified in the embodiment of the present invention;
FIG. 8 is a diagram illustrating a first scenario of ending determining a port path according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a second scenario for ending determining a port path according to an embodiment of the present invention;
FIG. 10 is a block diagram illustrating an exemplary configuration for determining a port path of an integrated circuit according to an embodiment of the present invention;
FIG. 11 is a block diagram of an apparatus for verifying an integrated circuit according to an embodiment of the present invention.
Detailed Description
In various embodiments of the present invention, fig. 1 is a schematic flow chart illustrating an implementation of a verification method for an integrated circuit according to an embodiment of the present invention, as shown in fig. 1, the verification method includes the following steps:
In an embodiment of the present invention, the check port includes: input port, output port and input-output port.
Verilog HDL (Hardware Description Language) is a Hardware Description Language for describing the structure and behavior of digital system Hardware in text form, and can be used to represent logic circuit diagrams and logic expressions including combinational logic devices and sequential logic devices, and also can represent the logic functions performed by the digital logic system.
The basic design unit for describing a hardware circuit by using Verilog HDL is a Module (Module), and a complex electronic circuit is constructed mainly by connecting and calling modules. Modules in the Verilog HDL can provide input ports, output ports, and input/output ports, and the Verilog HDL can call other modules by instantiating one module or by instantiating other modules. Thus, embodiments of the present invention utilize modules in Verilog HDL to provide input ports, output ports, and input-output ports.
Fig. 2 is a schematic flow chart of an implementation method for obtaining the to-be-verified port of each to-be-verified file in the embodiment of the present invention, and as shown in fig. 2, the implementation method for obtaining the to-be-verified port includes the following steps:
Typically, the design files for an integrated circuit include: a top level code file, a pin control code file, a core entity code file, etc. In the embodiment of the invention, a current file to be checked can be selected from a preset file list through the script, and because the design of the current integrated circuit generally adopts a Top-down (Top-down) design method, in the step, the script can firstly select a TOP file in the file list as the current file to be checked.
And step 101b, acquiring all ports to be checked of the current files to be checked.
In this step, the regular expression in the IEEE standard is used to match the current document to be checked, and all ports to be checked of the current document to be checked can be obtained, where the ports to be checked include an input port, an output port, and an input/output port.
And 102, determining a port path of the integrated circuit according to the to-be-verified ports of all to-be-verified files.
Fig. 3 is a schematic flowchart of an implementation method for determining a port path of an integrated circuit according to an embodiment of the present invention, and as shown in fig. 3, the method for determining a port path of an integrated circuit includes the following steps:
102a, selecting an unverified port from all ports to be verified of the current file to be verified as the current port to be verified.
In this step, an unverified port can be selected from all the ports to be verified of the current file to be verified through the script as the current port to be verified. For example, input port a in the current to-be-verified file may be selected as the current to-be-verified port.
And 102b, determining the port path of the current port to be verified.
In the specific embodiment of the present invention, the current port to be checked may have three connection relationships in the current file to be checked.
Fig. 4 is a schematic structural diagram of a first connection relationship of a current port to be verified in the embodiment of the present invention, as shown in fig. 4, a current port a to be verified is an input port of an example a, and a current port B is an output port of an example B; the calling relationship between the example A and the example B is as follows: instance A calls instance B; the connection relation of the current port A to be verified in the current file to be verified is as follows: the input port a of instance a is connected to the output port B of instance B and can be represented as: instance a, instance B. output port B → instance a. input port a.
Fig. 5 is a schematic structural diagram of a second connection relationship of a current port to be verified in the embodiment of the present invention, and as shown in fig. 5, a current port a to be verified is an input port of an example a, and a current port B is an output port of an example B; the calling relationship between the example A and the example B is as follows: instance A calls instance B; the connection relation of the current port A to be verified in the current file to be verified is as follows: the input port a of the instance a is connected with the output port B of the instance B through an inverter and a buffer, and can be represented as follows: example a, example B. output port B → inverter → buffer → example a. input port a.
Fig. 6 is a schematic structural diagram of a third connection relationship of a current port to be checked in the embodiment of the present invention, as shown in fig. 6, where the current port to be checked a is an input port of an instance a, the instance a includes combinational logic or sequential logic, and a connection relationship of the current port to be checked a in a current file to be checked is: input port a of instance a is connected to the combinational or sequential logic in instance a.
Fig. 7 is a flowchart illustrating an implementation method for determining a port path of a current port to be verified according to an embodiment of the present invention, where as shown in fig. 7, the method for determining a port path includes the following steps:
and 102b _1, searching the current port to be checked in the current file to be checked as a keyword, and determining the current instance of the current port to be checked.
In the specific embodiment of the present invention, the regular expression in the IEEE standard may also be adopted to match the current file to be checked, and all instances in the current file to be checked and the port list corresponding to each instance are obtained. Therefore, in this step, the current port to be checked is used as a keyword to search in the current file to be checked, so that the current instance where the current port to be checked is located can be determined. For example, assuming that the current port to be checked is the input port a, in a specific embodiment of the present invention, the input port a may be used as a keyword to search in the current file to be checked, and it may be determined that the current instance where the input port a is located is the instance a.
And 102b _2, determining the instance and the port for instance calling through the current to-be-checked port and the current instance.
In this step, the instance and the port for instance calling through the current to-be-verified port and the current instance may be determined by using an analysis method for instance calling in the prior art. For example, the instance and the port for instance calling through the current port to be checked a and the current instance a are instance B and output port B, and in this step, the instance and the port for instance calling through the current port to be checked and the current instance are determined to be instance B and output port B, respectively.
And 102b _3, determining the port path of the current port to be checked according to the instance and the port which are called by the current instance.
In this step, after the instance and the port for instance calling with the current instance are determined, the port path of the current port to be checked can be determined according to the instance and the port. For example, the instance B performs instance calling with the current instance a through the output port B and the input port a of the current instance a, and in this step, it may be determined that the port path of the current port a to be checked is: instance B, output port B → instance a, input port a.
Further, in the embodiment of the present invention, the buffer and the input port a, or the inverter and the input port a may be used as a key to search in the current file to be checked, so that it may be determined whether the input port a of the instance a is connected to another instance through the buffer or the inverter. For example, assuming that the input port a of the current instance a is connected to the output port B of the instance B through the output port C and the input port C1 of the buffer, therefore, the buffer buf and the input port a can be used as a key to search in the current file to be checked, when buf (C, a) is found, it may be determined that the input port a of the current instance a is connected to the output port C of the buffer, then the input port C1 of the buffer is used as a key to search in the current file to be checked, and it may be further determined that the buffer is connected to the output port B of the instance B through the input port C1, therefore, it may be determined that the path of the current port to be checked is: example B, output port B → buffer, input port C1 → buffer, output port C → example a.
Fig. 8 is a schematic structural diagram of a first case of ending determining a port path in the embodiment of the present invention, as shown in fig. 8, a current port a to be verified is an input port of an instance a, and a call relationship between the instance a, the instance C, and combinational logic or sequential logic is as follows: instance C invokes instance C and combinational or sequential logic. In the specific embodiment of the present invention, when the current port a to be checked is used as a keyword to search in the current file to be checked, if the current port a to be checked is connected to the combinational logic or the sequential logic in the instance a, the process of determining the port path of the current port a to be checked is ended. That is, if the port a to be checked is connected to the combinational logic or sequential logic in instance a, the combinational logic or sequential logic may be used as an end point of the port path of the port a to be checked.
FIG. 9 is a structural diagram illustrating a second case of ending determining a port path according to the embodiment of the present invention, as shown in FIG. 9, a current inspection port A1 is an output port of instance A, and a port T1 is an input port of a TOP instance (i.e., instance TOP) in a current inspection file; the call relationship of example a to example TOP is: example TOP calls example A; the connection relation of the current port A to be verified in the current file to be verified is as follows: output port a1 of instance a is connected to input port T1 of instance TOP. In the embodiment of the present invention, if the current instance is called by the instance TOP, after the port path of the current port to be checked is acquired, the input port T1 of the instance TOP may be used as one terminal of the port path of the current port to be checked.
And 102c, determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
In this step, after determining the port paths of all the ports to be verified, the port paths of the integrated circuit may be determined according to the port paths of all the ports to be verified.
FIG. 10 is a block diagram illustrating an embodiment of determining a port path of an integrated circuit, where, as shown in FIG. 10, port A is an input port of example A and port A1 is an output port of example A; port B is the output port of instance B; port D is the input port of instance D; the calling relationship of instance A, instance B and instance D is: instance D calls instance A and instance B; the port path for input port a of example a is: the input port a of the example a is connected with the output port B of the example B, that is: instance d, instance B, output port B → instance d, instance a, input port a; the port path of output port a1 of example a is: the output port a1 of instance a is connected to the input port D of instance D, i.e.: instance D, instance a, output port a1 → instance D, input port D, in this step, the two port paths of input port a and output port a1 of instance a may be merged into one port path, namely: instance D, instance B, output port B → instance D, instance a, input port a → instance D, instance a, output port a1 → instance D.
As can be seen from the above description, the port paths of the integrated circuit can be determined according to all the ports to be verified through the steps 102a to 102c, and thus, in the embodiment of the present invention, various test signals need to be input at one end of the integrated circuit connection, and the constraint condition does not need to be programmed in advance, so that compared with the prior art, the verification method of the integrated circuit provided in the embodiment of the present invention can not only improve the confidence of the verification result of the integrated circuit, but also improve the verification efficiency of the integrated circuit.
Preferably, in the embodiment of the present invention, a depth threshold of the instance analysis may also be preset. For example, if only three layers of instances down from the top level instance in an integrated circuit design are associated with pins, the depth threshold may be set to 3 in particular embodiments of the present invention, and if four layers of instances down from the top level instance in an integrated circuit design are associated with pins, the depth threshold may be set to 4 in particular embodiments of the present invention.
Therefore, before determining the port path of the current port to be checked, it may be first determined whether the depth, called by the preset top-level instance, of the current instance where the current port to be checked is located is greater than the depth threshold, and if so, the process of determining the port path of the current port to be checked is ended; otherwise, determining the port path of the current port to be checked.
And 103, when the preset matched starting point and end point are found in the port path of the integrated circuit, determining that the integrated circuit is connected and passed.
In the specific embodiment of the present invention, after determining the port path of the integrated circuit, the starting point and the terminal of the preset match may be searched in the port path of the integrated circuit, and when the search is successful, it is determined that the integrated circuit passes the connection; otherwise, the integrated circuit connection is determined not to pass.
Specifically, a preset matching starting point may be input at an input end of the integrated circuit, and then the integrated circuit is searched in a port path of the integrated circuit, and when a preset matching end point is found, it is determined that the integrated circuit passes through connection; and when the preset matched terminal point is not found, determining that the integrated circuit connection does not pass.
The verification method of the integrated circuit provided by the embodiment of the invention does not need to input various test signals at one end connected with the integrated circuit and also does not need to write constraint conditions in advance, so that compared with the prior art, the verification method of the integrated circuit provided by the embodiment of the invention can not only improve the confidence coefficient of the verification result of the integrated circuit, but also improve the verification efficiency of the integrated circuit; moreover, the method is simple and convenient to realize, convenient to popularize and wide in application range.
Fig. 11 is a schematic diagram of a structure of an ic verification apparatus according to an embodiment of the present invention, as shown in fig. 11, the ic verification apparatus includes: an acquisition unit 1101, a determination unit 1102, and a determination unit 1103; wherein the content of the first and second substances,
the acquiring unit 1101 is configured to acquire a port to be checked in each file to be checked of the integrated circuit, and send the port to be checked to the determining unit 1102;
the determining unit 1102 is configured to determine a port path of the integrated circuit according to all the ports to be verified, and send the port path of the integrated circuit to the determining unit 1103;
the determining unit 1103 is configured to determine that the integrated circuit is connected when a preset matched start point and end point are found in a port path of the integrated circuit.
Further, the obtaining unit 1101 includes:
a first selecting subunit 11011, configured to select an unverified file from a preset file list as a current file to be checked, and send the current file to be checked to the obtaining subunit 11012;
the obtaining subunit 11012 is configured to obtain all ports to be verified of the current file to be verified.
Further, the determining unit 1102 includes:
a second selecting subunit 11021, configured to select an unverified port from all the ports to be verified as a current port to be verified, and send the current port to be verified to a determining subunit 11022;
the determining subunit 11022 is configured to determine a port path of the current port to be verified; and determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
Further, the determining unit 1102 is further configured to search the current port to be checked in the current file to be checked as a keyword, and determine a current instance where the current port to be checked is located; determining an instance and a port for instance calling through the current port to be checked and the current instance; and determining the port path of the current port to be checked according to the instance and the port which are called by the instance and the current instance.
Further, the determining unit 1103 is further configured to determine whether a depth, called by a preset top-level instance, of a current instance where the current port to be checked is located is greater than a preset depth threshold; if yes, ending the determination of the port path of the current port to be checked.
In practical applications, the obtaining unit 1101, the determining unit 1102 and the determining unit 1103 can be implemented by a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like located in an integrated circuit designer.
The verification device of the integrated circuit provided by the embodiment of the invention does not need to input various test signals at one end connected with the integrated circuit and also does not need to write constraint conditions in advance, so that compared with the prior art, the verification device of the integrated circuit provided by the embodiment of the invention can not only improve the confidence coefficient of the verification result of the integrated circuit, but also improve the verification efficiency of the integrated circuit; moreover, the method is simple and convenient to realize, convenient to popularize and wide in application range.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. A method of verifying an integrated circuit, comprising:
acquiring a port to be checked in each file to be checked of the integrated circuit;
determining a port path of the integrated circuit according to the ports to be verified of all the files to be verified;
when a preset matched starting point and end point are found in a port path of the integrated circuit, judging that the integrated circuit is connected and passed;
the determining the port path of the integrated circuit according to the ports to be verified of all the files to be verified comprises the following steps:
selecting an unverified port from all the ports to be verified as a current port to be verified;
determining a port path of the current port to be checked;
and determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
2. The method of claim 1, wherein the obtaining the ports to be checked in each file to be checked of the integrated circuit comprises:
selecting an unverified file from a preset file list as a current file to be verified;
and acquiring all ports to be checked of the current file to be checked.
3. The method of claim 2, wherein the determining the port path of the current candidate port comprises:
searching the current port to be checked in the current file to be checked as a keyword, and determining the current instance of the current port to be checked;
determining an instance and a port for instance calling through the current port to be checked and the current instance;
and determining the port path of the current port to be checked according to the instance and the port which are called by the instance and the current instance.
4. The method of claim 2, wherein prior to said determining the port path of the current candidate port, the method further comprises:
judging whether the depth of the current instance where the current port to be checked is called by a preset top-layer instance is greater than a preset depth threshold value or not;
if yes, ending the determination of the port path of the current port to be checked.
5. An apparatus for verifying an integrated circuit, comprising:
the device comprises an acquisition unit, a determination unit and a processing unit, wherein the acquisition unit is used for acquiring a port to be checked in each file to be checked of the integrated circuit and sending the port to be checked to the determination unit;
the determining unit is used for determining the port path of the integrated circuit according to all the ports to be checked and sending the port path of the integrated circuit to the judging unit;
the judging unit is used for judging that the integrated circuit is connected and passed when a preset matched starting point and an end point are found in a port path of the integrated circuit;
wherein the determination unit includes:
the second selection subunit is used for selecting one unverified port from all the ports to be verified as a current port to be verified and sending the current port to be verified to the determination subunit;
the determining subunit is configured to determine a port path of the current port to be verified; and determining the port paths of the integrated circuit according to the port paths of all the current ports to be checked.
6. The apparatus of claim 5, wherein the obtaining unit comprises:
the first selection subunit is used for selecting an unverified file from a preset file list as a current file to be checked and sending the current file to be checked to the acquisition subunit;
and the obtaining subunit is configured to obtain all ports to be verified of the current file to be verified.
7. The apparatus of claim 6,
the determining unit is further configured to search the current port to be checked in the current file to be checked as a keyword, and determine a current instance where the current port to be checked is located; determining an instance and a port for instance calling through the current port to be checked and the current instance; and determining the port path of the current port to be checked according to the instance and the port which are called by the instance and the current instance.
8. The apparatus of claim 6,
the judging unit is further configured to judge whether a depth called by a preset top-level instance of the current instance where the current port to be checked is located is greater than a preset depth threshold; if yes, ending the determination of the port path of the current port to be checked.
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