CN111651946A - Method for hierarchically identifying circuit gate based on workload - Google Patents
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Abstract
The invention discloses a method for hierarchically identifying a circuit gate based on a working load, and belongs to the field of high reliability of a high-performance processor. The method comprises the following steps: acquiring a working load signal, extracting a signal probability, reading a circuit netlist, a design constraint and obtaining a path delay of a circuit to obtain a potential critical path; a parameter analysis and calculation stage, which is used for calculating the maximum critical path delay which can be borne by the circuit path and is obtained by aging delay degradation under the NBTI effect; and a step of determining hierarchical identification gates, which is used for determining gates with higher aging sensitivity in the critical path, and providing a new method for calculating weights. The method can be integrated in the design flow of the ASIC, can effectively identify the aging critical path and the aging critical gate, reduces the complexity of replacing the gate in the critical path by the traditional method, and improves the working efficiency.
Description
Technical Field
The invention relates to a method for hierarchically identifying a circuit gate based on a working load, and belongs to the field of high reliability of a high-performance processor.
Background
With the development of very large scale integrated circuits, the level of manufacturing processes has been continuously improved, and the integrated circuits have entered the nanometer era. Reliability issues have become a major consideration in ultra-deep CMOS manufacturability. Designing reliable circuits that can operate for long periods of time, especially circuits that can guarantee correct functionality in different operating environments, has been a difficult challenge.
For reliability, Negative Bias Temperature Instability (NBTI) refers to the degradation of a series of electrical parameters caused by applying a Negative gate voltage to a PMOSFET at high temperature, and in ultra-deep CMOS manufacturability, reliability issues have become a major factor to be considered. Designing highly reliable circuits that can operate for long periods of time, especially circuits that can guarantee correct functioning in different operating environments, has been a difficult challenge. The NBTI effect has a large impact on digital circuit reliability. This phenomenon is further aggravated in severe environments such as high temperature and high pressure. The NBTI effect affects the threshold voltage of the pass transistor, and as the operating time of the circuit increases, the threshold voltage of the gate increases continuously, which results in longer gate delay and increased path delay of the gate. For digital circuits, when the path delay is increased, once the time margin reserved in the design stage is exceeded, the signal sent by the previous register cannot be correctly captured by the next register in one cycle, resulting in incorrect or invalid circuit functions. If the delay increase is significant, the logic function of the circuit is likely to be incorrect. Even if the bandwidth comparison is added to tolerate the increase in circuit path delay due to aging, the circuit may fail, and the increased redundant timing may affect the circuit performance and reduce the operating frequency of the circuit. While frequency is also an important factor in evaluating performance of a processor in the present day of microprocessor development, if too large a guard band is used, too much timing in the path for redundancy protection will have a significant impact on performance due to aging delay. Therefore, other strategies must be taken to increase the reliability of the circuit.
Currently, researchers have explored a variety of approaches for mitigating the effects of NBTI on circuits, mainly classified as optimization at the circuit level or optimization at the architecture level. The method comprises the steps of adjusting the threshold voltage of a transistor, enabling the threshold voltage of the transistor to be increased when a circuit is aged, and responding to the time delay influence of the circuit aging by dynamically adjusting the threshold voltage of the transistor. And secondly, adjusting the size of the logic gate, wherein the intrinsic delay of the logic gate is adjusted by mainly changing the width-to-length ratio of the logic gate so as to obtain more time sequence margins and delay caused by tolerance aging. Finally, the self-adaptive power supply voltage is used, and the principle is that when the circuit is aged, the driving voltage is increased to reduce the circuit path delay. The above method has a certain influence on the performance of the circuit as described above, and is therefore not suitable for a high-performance circuit. Therefore, some researchers have utilized the self-recovery principle of NBTI effect to the method for controlling the nodes of the gate circuit, and by controlling the input nodes, the gates in the path are in a positive bias state as much as possible, so as to alleviate the influence of NBTI effect, which mainly includes an input vector control technique, an internal node control technique, and the like.
For these techniques, identification of critical paths and critical gates is not left. Aiming at the problems, the invention provides an effective method for selecting the NBTI key path, and the most favorable key gate can be found to improve the reliability of the circuit. By considering the delay sensitivity of the gate and comprehensively considering the critical condition of the gate, the work load and the relaxation time factor of the aging path, the accuracy of the method is improved. The gate delay here takes into account the contents of the two parts, the intrinsic delay of the gate and the increment of the delay of the gate that has already undergone aging effects, which make up the sensitivity of the aging delay gate.
Based on the worst case aging prediction, a static aging algorithm model is usually adopted, that is, all logic gates are in the worst case, the input vector of the logic gate is always 0 at the input end of the logic gate, and then the logic gates in the whole path are summed after aging for a certain time. However, the method is to simulate the logic gate, establish aging delay degradation characteristics, and then analyze the aging characteristics with the target netlist, which is relatively simple and fast, but does not consider the aging state of the circuit under the actual operation state, and is not suitable for complex circuits. Therefore, by introducing a working load and proposing a Transistor Stress Probability (TSP) concept, the aging condition of the circuit in the operating state can be simulated more accurately. The method has the advantages that the critical path of the circuit in the actual working state is accurately simulated and extracted, and the method has better guiding significance for aging protection of the circuit.
Disclosure of Invention
Aiming at the problems, the invention provides a method for hierarchically identifying circuit gates based on a working load, which can effectively select a key path of NBTI and search the most favorable gate to improve the reliability of a circuit.
In the process of identifying the circuit gate, the method provided by the application considers the delay sensitivity of the gate, comprehensively considers the critical condition of the gate, the working load and the relaxation time factor of an aging path, and provides a concept of transistor stress probability TSP, so that the accuracy of aging prediction of the circuit in the actual operation period is improved.
The invention provides a method for hierarchically identifying a circuit gate based on a workload, which comprises the following steps:
s1, according to the circuit net list and the constraint file, static time sequence analysis is carried out to obtain the set of original time delay values of all time sequence paths in the circuit, which is defined as an original time delay set Dp＝{dp1,dp2,…,dpj,…,dpnN represents the number of original paths; and sequencing the original time delay time sequence of the circuit to find out the maximum time delay T of the circuit without considering the aging time delaymax(ii) a What is needed isThe original delay value is the sum of the delay of each gate circuit which is not aged;
s2 traversing original delay set DpIf d ispj×(1+R％)>TmaxThen define dpjThe corresponding paths are potential paths considering aging conditions and are written into a potential critical path set RCP until an original delay set DpEnding traversal when the time is empty; wherein, R% is the delay increment percentage after path aging;
s3 according to door delay increment dpj× (1+ R%) calculate the delay values D (G) of all gatesk)，D(Gk)＝max{D(Gi)+t(Gk,i) K refers to different paths, i refers to different nodes in the paths; d (G)i) Is the original delay value of the ith gate, t (G)k,i) Is the aging delay increment of the ith gate circuit in the k path under the action of NBTI;
s4 is based on delay values D (G) of all gatesk) All the critical gates are traversed until the largest critical gate D (G) is traversedk) Stopping, and calculating to obtain a critical condition theta of the aging gate;
s5 determines all potential sets of aging critical gates according to the critical condition theta of the aging gates, and the determination condition is D (G)i)≥θ；
S6, calculating the number of the critical paths where all the aging potential critical gates in the aging potential critical gate set are located;
s7 calculates the weight of all aging potential critical gates according to their weight W (G)k) Size, reordering aging potential critical gates;
and S8, updating the time sequence again, repeatedly executing S7 until the aging potential key gate set is empty, outputting a hierarchical key gate set, and finishing the identification of hierarchical circuit gates based on the workload.
Optionally, the weights W (G) of the aging potential critical gates in S7k) The calculation method comprises the following steps:
wherein the content of the first and second substances,Nin(Gk) Number of fan-in paths aggregated for aging potentially critical doors, Nout(Gk) Number of fanout path sets, m, to age potentially critical gateskRepresenting different timing paths. Optionally, the method further comprises extracting information about the operational load of each individual gate and transistor within the circuit.
Optionally, the value of R% in S2 is 20%.
Optionally, the method further includes extracting information about the operation load of each individual gate and transistor inside the circuit, including:
for the design of a microprocessor, extracting a workload by using a performance simulator;
for other designs, system level simulation vectors are used for performance analysis to derive their workload.
Optionally, the extracting information about the working load of each individual gate and transistor in the circuit includes:
mapping the circuit to a technology library through a synthesis tool and generating a gate-level netlist;
providing the generated gate-level netlist and the workload analysis to a logic simulator so as to obtain the signal probability and the switching activity of each transistor in the gate-level netlist;
by considering V induced for accurate NBTIthStack effects of offset and delay variation analysis, the output of the logic simulator is further processed to obtain the effective duty cycle of each transistor in each gate.
Optionally, the method is implemented by using a Tcl language in the implementation process.
Optionally, the method takes into account the two-part contents of the gate delay, i.e. the inherent delay of the gate and the increment of the delay of the gate that has undergone the aging effect.
Optionally, in the circuit gate identification process, the delay sensitivity of the gate is considered, the critical conditions of the gate, the workload and the relaxation time factor of the aging path are considered comprehensively, and finally a hierarchical key gate set is output.
The application also provides a method for optimizing the circuit gate based on the working load, the method adopts the method to obtain a hierarchical key gate set, and when the key gate is optimized, the priority for optimization is determined according to the corresponding hierarchy of the key gate.
The application also provides a design method of the integrated circuit in the processor, and the method adopts the method for identifying the aging critical path and the aging critical gate based on the hierarchical circuit gate under the working load, and/or adopts the method for optimizing the aging critical path and the aging critical gate based on the circuit gate under the working load to optimize the aging critical path and the aging critical gate.
The invention has the beneficial effects that:
compared with the traditional method for determining the key gate, the method can accurately and effectively extract the key path of the circuit and the key gate thereof, and is embodied as follows:
(1) the present invention introduces a workload and proposes a TSP concept. The aging condition of the circuit under the running state can be accurately simulated. Because the traditional aging prediction method is to simulate a logic gate, establish aging delay degradation characteristics, and then compare and analyze the aging characteristics with a target netlist, although the aging characteristics are simple and fast, the aging state of a circuit in an actual operation state is not considered, and the aging prediction method is not suitable for complex circuits. Therefore, the method accurately simulates and extracts the critical path of the circuit in the actual working state, and has better guiding significance for aging protection of the circuit.
(2) The invention provides a new weight calculation method, which can effectively perform hierarchical processing on the extracted key gates, avoid repeated processing in the processing process of the key gates, and effectively prevent excessive extraction (namely, a non-key gate is mistaken as a key gate) or omission (namely, the key gate is not identified) of the key gates. Since if the critical gates are over fetched, unnecessary overhead is incurred in guarding the critical gates. And if a key door is omitted, incomplete protection can be caused. According to the invention, the key gates are divided into different levels by hierarchical processing, and the gates with higher priority levels are firstly output to the key gate set to be optimized, so that the gates with high priority levels can be prevented from being repeatedly optimized when the gates with the second priority levels are optimized, and the working efficiency is improved.
(3) The invention is completed by adopting a Tcl language, can be well embedded into the flow of circuit design by adopting a mode of combining Tcl voice and an EDA tool, maps the circuit into a basic process library (such as an SMIC 65nm process library), does not need additional software, and improves the universality and the easy portability of the invention.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of identifying circuit gates based on hierarchy under a workload in one embodiment of the invention.
FIG. 2 is a framework diagram of a workload critical path based extraction flow in one embodiment of the invention.
FIG. 3 is a graph of critical path and critical gate count versus area overhead for one embodiment of the present invention.
FIG. 4 is a conceptual diagram of stress probability calculations for different gates in one embodiment of the invention.
FIG. 5 is a critical path diagram in one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
the embodiment provides a method for hierarchically identifying circuit gates based on workload, which comprises the following steps:
s1, according to the circuit netlist and the constraint file, static time sequence analysis is carried out to obtain an original time delay value set of the time sequence path in the circuit, and the original time delay value set is defined as an original time delay set Dp＝{dp1,dp2,…,dpj,…,dpnWhere n represents the original path number. And sequencing the original time delay time sequence of the circuit to find out the maximum time delay T of the circuit without considering the aging time delaymax(ii) a The original delay value is the sum of the delay of each gate circuit which is not aged;
s2 traversing original delay set DpIf d ispj×(1+R％)>TmaxThen define dpjThe corresponding paths are potential paths considering aging conditions and are written into a potential critical path set RCP until an original delay set DpEnding traversal when the time is empty; wherein, the R% takes 20% which represents that the increment percentage of the time delay can rise by 20% after the route is aged for about ten years;
s3 according to door delay increment dpj× (1+ R%) calculate the delay values D (G) of all gatesk)，D(Gk)＝max{D(Gi)+t(Gk,i) K refers to different paths, i refers to different nodes in the paths; d (G)i) Is the original delay value of the ith gate, t (G)k,i) Is the aging delay increment of the ith gate circuit in the k path under the action of NBTI;
s4 is based on delay values D (G) of all gatesk) All the critical gates are traversed until the largest critical gate D (G) is traversedk) Stopping, calculating to obtain a critical condition theta of the aging gate, namely a gate circuit in a path to be violated in a path time sequence after aging delay;
s5 determines all potential sets of aging critical gates according to the critical condition theta of the aging gates, and the determination condition is D (G)i)≥θ；
S6, calculating the number of the critical paths where all the aging potential critical gates in the aging potential critical gate set are located;
s7 calculates the weight of all aging potential critical gates according to their weight W (G)k) Size, reordering aging potential critical gates;
and S8, updating the time sequence again, repeatedly executing S7 until the aging potential key gate set is empty, outputting a hierarchical key gate set, and finishing the identification of hierarchical circuit gates based on the workload.
Optionally, the weights W (G) of the aging potential critical gates in S7k) The calculation method comprises the following steps:
wherein N isin(Gk) Number of fan-in paths aggregated for aging potentially critical doors, Nout(Gk) Number of fanout path sets, m, to age potentially critical gateskRepresenting different timing paths. Specifically, as shown in fig. 1, the determination of the critical path of the circuit netlist is completed based on the overall thought of the hierarchical recognition circuit gate under the workload, and the circuit netlist and the workload thereof are used as the input files of the static timing analysis.
Further, all the gate circuits in the critical path are extracted according to the selected circuit critical path, the transmission delay of all the gate circuits is calculated according to the delay increment of the gate circuits under the NBTI effect, the maximum delay gate is found out to be used as a reference, and all the gate circuits are sequenced. All gate circuits are traversed, the threshold condition of the key gate is found, and a potential key gate set is determined. And determining the weight of the key gate by calculating the number of the fan-in and fan-out key paths of the key gate in the potential key gate set, and performing hierarchical processing on the determined potential key gate.
Example two:
the embodiment provides an application of a method for hierarchically identifying circuit gates based on workload in practice, wherein the method comprises the following steps:
step 1: acquiring a working load signal and extracting the probability of the working load signal;
for the design of a microprocessor, extracting a workload by using a performance simulator; for example, a performance simulator is utilized to extract input patterns for different functional blocks of the processor of the target application.
For other designs (e.g., ASICs), high-level (system-level) simulation vectors may be used for performance analysis. I.e. the performance analysis data comprising system level workload correlations is provided to step 2 for further processing for timing analysis.
In this way, a link is established between system level workload dependencies (i.e., occurring at runtime) and timing analysis at design time.
Step 2: the information obtained from the system level workload analysis step is processed at the circuit level to extract workload related detailed information for each individual gate (and transistor) within the circuit.
Under the SMIC 65nm process, the circuit is mapped to the technology library by a synthesis tool (such as Design compiler, DC) and a gate-level netlist is generated. The generated gate-level netlist and workload analysis are then provided to a logic simulator (e.g., a VCS) to obtain the signal probability and switching activity for each transistor within the gate-level netlist. By considering V induced for accurate NBTIthStack effects of offset and delay variation analysis, the output of the logic simulator is further processed to obtain the effective duty cycle of each transistor in each gate.
And step 3: reading the circuit netlist and the constraint file generated in the step 2, performing static time sequence analysis, circularly traversing the set of the original delay values, and defining the set as an original delay set DpThen, the circuit delay sequences are sequenced, the maximum delay of the circuit without considering the aging delay is found out and is set as Tmax. The original delay value is the sum of the delay of each gate circuit which is not aged;
and 4, step 4: traverse the original delay set DpIf D isp×(1+R％)>TmaxThen define the delay DpAnd writing the paths into a potential critical path set RCP (path graph) by taking aging into consideration, and ending traversal until an original delay set is empty, wherein R% is increment percentage of the delay rising after the paths are aged for a period of time.
And 5: calculating delay values D (G) of all gate circuits based on the gate delay increments estimated due to NBTI aging effectsk)；
Under this step, the inputs are all gates in the critical path, the gates in the critical path are traversed, and the time under the NBTI effect is foundThe largest key gate, using the key gate with the largest delay as the reference for the key gate traversal, according to the transmission delay D (G)k) Sorting all gates in the critical path, D (G)k)＝max{D(Gi)+t(Gk,i) In which D (G)i) Is the original delay value of the ith gate, t (G)k,i) For aging delay increment of ith gate circuit in k path under the action of NBTI, k refers to different paths, and i is different node in the path.
Step 6: according to the step 5, the transmission delay of all gates under the NBTI effect is calculated, and all key gates are traversed until the maximum key gate D (G) is traversedk) Stopping, calculating to obtain a critical condition theta of the aging gate, namely a gate circuit in a path to be violated in a path time sequence after aging delay;
and 7: determining all potential sets of aging key gates according to the critical condition theta of the aging gates obtained in the step 6, wherein the determination condition is D (G)i)≥θ。
And 8: calculating the number of the located critical paths of the potential critical gate set; wherein, the number of fan-in paths for defining potential key door is Nin(Gk) The fan-out path set number of the key gate is Nout(Gk)。
And step 9: weights are calculated for all potential critical gates, according to which weight W (G)k) The size, the key gate is reordered, the key gate with the highest weight has the highest priority, and the weight calculation method is that
Step 10: and (4) processing the key gate with the highest priority, updating the time sequence again, repeatedly executing the step (9) until the potential key gate set is empty, outputting the hierarchical key gate set for subsequent key gate replacement size adjustment and the like, and completing identification of the hierarchical circuit gate based on the workload.
In order to verify that the method provided by the application can accurately and effectively extract the critical path and the critical gate of the circuit, the experiment is carried out on an ISCS standard circuit, and the experiment is as follows:
as shown in FIG. 5, the critical path diagram, in practical applications, using the Tcl language embedded in the EDA tool, has the advantages of making the code have better portability, facilitating debugging, reducing the complexity of operation, and not requiring to resynthesize the netlist. Wherein the embedded Tcl command in the PT, hierarchical-of _ object-filter, etc., may filter the circuit netlist using multiple attributes to obtain the desired object to return. The experimental procedure using the Tcl language for the main steps is as follows:
1) extracting a circuit path
set original_paths[list]
set original_all_paths[get_timing_paths–slack_lesser_than$number]
lappend orginal_paths$original_all_paths
2) All paths required can be extracted using the PT self-contained get _ timing _ pages command, written into the set using the lappend.
3) Path set ordering
set original_paths_sorts[list]
set original_paths_sorts_get[lsort–decreasing$original_paths]
lappend original_paths_sorts$original_paths_sorts_get
The lsort command may sort all timing paths in descending order according to the size of the timing path and according to a-dividing function.
4) Setting threshold and extracting key path
set slack_threshold$margin
set critical_paths[get_timing_paths–slack_lesser_than$slack_threshold–max_path$max_path–nworst$nworst]
Setting the size of an aging margin, and extracting a key path set for sensing aging from the path set.
5) Obtaining logic gates in a critical path
foreach_in_collection cell$critical_paths[get_cells–hierarchical–filter“is_combinational＝＝true”]{
lappend com_cell[get_attribute$cell full_name]
}
The forward _ in _ collection will traverse all paths to find the eligible logic gates.
6) And extracting the fan-in and fan-out conditions of each key door to judge the weight of the key door.
set through_pins[get_pins–of_object[get_cells$com_cell]–filter“@direction＝＝in”]
foreach_in_collection through_pin$through_pins{
incr path_count[sizeof_cellection[get_timing_paths–through$through_pin]]
}
7) The optimized replacement of the key door can directly use the process library unit without the need of comprehensive treatment again.
foreach_in_collection swap$swap_cells{
set swap_base_name[get_attribute$swap base_name]
set swap_ref_name[get_attribute$swap ref_name]
if{[string match“swap_cell”]string range$swap_ref_name$range}{
set new_cell[string replace$swap_ref_name$new_cell]
}
Values in the byte range can be matched by srting, if there is a full match, then return and replace with repalce command.
To verify the effectiveness of the proposed method, the present application performs experiments on the ISCAS reference circuit and the microprocessor core as follows:
under the SMIC 65nm process, the RTL code is converted into a gate-level netlist using DC (design compiler). In the DC synthesis process, the clock cycles are constrained, and the timing constraints of the circuit are set to 5% and 10%, respectively, and the experimental results are shown in tables 1 and 2.
Table 1: experimental results with timing margin of 5%
| Circuit arrangement | Number of paths | Door number | Critical path | Potential key door | Key door | Ratio of occupation of |
| S298 | 231 | 166 | 63 | 35 | 27 | 16.7 |
| S838 | 1714 | 279 | 246 | 95 | 64 | 23.1 |
| C880 | 4935 | 254 | 219 | 63 | 39 | 15.3 |
| C1908 | 15769 | 296 | 2176 | 148 | 47 | 15.9 |
| C2670 | 3379 | 420 | 187 | 79 | 49 | 11.6 |
| C5315 | 24668 | 1224 | 594 | 298 | 67 | 5.4 |
| C7552 | 43174 | 1450 | 579 | 267 | 71 | 4.8 |
| ROCKET | 925468 | 91588 | 177910 | 27476 | 1658 | 1.8 |
| Mean value of | - | - | - | - | - | 11.8 |
Table 2: experimental results with timing margin of 10%
| Circuit arrangement | Number of paths | Door number | Critical path | Potential key door | Key door | Ratio of occupation of |
| S298 | 231 | 166 | 52 | 28 | 21 | 13.8 |
| S838 | 1714 | 279 | 192 | 73 | 58 | 21.3 |
| C880 | 4935 | 254 | 174 | 32 | 28 | 11.0 |
| C1908 | 15769 | 296 | 1747 | 144 | 34 | 11.4 |
| C2670 | 3379 | 420 | 138 | 78 | 36 | 8.5 |
| C5315 | 24668 | 1224 | 432 | 253 | 42 | 3.4 |
| C7552 | 43174 | 1450 | 418 | 252 | 46 | 3.1 |
| ROCKET | 925468 | 91588 | 125686 | 16864 | 963 | 1.1 |
| Mean value of | - | - | - | - | - | 9.2 |
As shown in Table 1, the gate count of a standard circuit is not proportional to the path length, which may be a long path with more gates in a single path. Conversely, fewer gates may form more timing paths, since the same gate may appear in different timing paths, which is also a basis for determining the weight. But the basic trend is that the number of paths is increasing as the number of gates increases.
As can be seen from table 1, for the protection against aging, all paths do not need to be processed, and only the critical gates of the critical paths need to be replaced, so that the critical gates are in a positive bias state as much as possible on the premise of affecting the logic of the circuit, thereby reducing the influence of the NBTI effect and prolonging the service life of the circuit.
As shown in Table 2, the critical path and the critical gates are gradually decreased by relaxing the timing margin. This is because by relaxing the timing, the circuit can be made more redundant to guard against timing increases due to the NBTI effect. Thus, the critical path with a timing margin of 5% will not violate the constraint with a timing margin of 10%, and thus will become a non-critical path, and correspondingly, the number of critical gates will be small. This is also the simplest way that the circuit can work properly if aging errors occur in the circuit, but the performance of the circuit will be degraded.
As can be seen from fig. 3, as the number of gates increases, although the number of the critical paths and the number of the critical gates increase, after the critical gates are optimized, the area overhead thereof is in a downward trend, where the left side is labeled as the number of the critical paths, the right side is labeled as the number of the critical gates, and the broken line is the area overhead caused by optimizing the critical gates. The reason for this is shown in tables 1 and 2, that is, although the number of circuit gates and the number of key gates are increased, the ratio of the key gates tends to decrease, and thus the area overhead is also decreased when optimizing. It can be concluded that the method proposed in the present application can alleviate the aging effect with a small area overhead when processing large-scale digital circuits and microprocessor cores.
As the timing margin relaxes, the ratio of the number of critical gates decreases. This is because when the timing margin is increased, the potential path, which was originally in the case where the timing margin was small, may have its timing still satisfied after the NBTI effect of ten years. Thus, the number of sets of potential critical paths is reduced, and correspondingly, the number of critical gates that make up the potential critical paths is also reduced.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A method for identifying circuit gates based on hierarchy under a workload, the method comprising:
s1, according to the circuit net list and the constraint file, static time sequence analysis is carried out to obtain the collection of the original delay values of the time sequence paths in the circuit, which is defined as the collection D of the original delay values of the pathsp＝{dp1,dp2,…,dpj,…,dpnN represents the number of original paths; and sequencing the original time delay time sequence of the circuit to find out the maximum time delay T of the circuit without considering the aging time delaymax(ii) a The original delay value is the sum of the delay of each gate circuit which is not aged;
s2 traversing original delay set DpIf d ispj×(1+R％)>TmaxThen define dpjThe corresponding paths are potential paths considering aging conditions and are written into a potential critical path set RCP until an original delay set DpEnding traversal when the time is empty; wherein, R% is the delay increment percentage after path aging;
s3 according to door delay increment dpj× (1+ R%) calculate the delay values D (G) of all gatesk)，D(Gk)＝max{D(Gi)+t(Gk,i) K refers to different paths, i refers to different nodes in the paths; d (G)i) Is the original delay value of the ith gate, t (G)k,i) Is the aging delay increment of the ith gate circuit in the k path under the action of NBTI;
s4 is based on delay values D (G) of all gatesk) Go through allUntil the largest critical gate D (G) is traversedk) Stopping, and calculating to obtain a critical condition theta of the aging gate;
s5 determines all potential sets of aging critical gates according to the critical condition theta of the aging gates, and the determination condition is D (G)i)≥θ；
S6, calculating the number of the critical paths where all the aging potential critical gates in the aging potential critical gate set are located;
s7 calculates the weight of all aging potential critical gates according to their weight W (G)k) Size, reordering aging potential critical gates;
and S8, updating the time sequence again, repeatedly executing S7 until the aging potential key gate set is empty, outputting a hierarchical key gate set, and finishing the identification of hierarchical circuit gates based on the workload.
2. The method of claim 1, wherein the weight W (G) of the aging potential critical gate in S7k) The calculation method comprises the following steps:
wherein N isin(Gk) Number of fan-in paths aggregated for aging potentially critical doors, Nout(Gk) Number of fanout path sets, m, to age potentially critical gateskRepresenting different timing paths.
3. The method of claim 2, wherein the value of R% in S2 is 20%.
4. The method of claim 3, further comprising extracting information about the operational load of each individual gate and transistor within the circuit, including:
for the design of a microprocessor, extracting a workload by using a performance simulator;
for other designs, system level simulation vectors are used for performance analysis to derive their workload.
5. The method of claim 4, wherein extracting information about the operational load of each individual gate and transistor within the circuit comprises:
mapping the circuit to a technology library through a synthesis tool and generating a gate-level netlist;
providing the generated gate-level netlist and the workload analysis to a logic simulator so as to obtain the signal probability and the switching activity of each transistor in the gate-level netlist;
by considering V induced for accurate NBTIthStack effects of offset and delay variation analysis, the output of the logic simulator is further processed to obtain the effective duty cycle of each transistor in each gate.
6. The method of claim 5, wherein the method is implemented in a Tcl language.
7. The method of claim 6, wherein the method takes into account the gate delay in terms of two components, namely the inherent delay of the gate and the incremental delay of the gate that has been caused by aging effects.
8. The method of claim 7, wherein the method considers the delay sensitivity of the gates in identifying the circuit gates, and comprehensively considers the critical conditions of the gates, the workload and the slack time of the aging path, and finally outputs a hierarchical set of key gates.
9. A method for optimizing circuit gates based on workload, the method comprising using the method of any one of claims 1-8 to obtain a hierarchical set of key gates, and determining the priority for optimization according to the hierarchy corresponding to the key gates when optimizing the key gates.
10. A method for designing an integrated circuit in a processor, the method comprising identifying optimized aging critical paths and aging critical gates using the method for identifying circuit gates based on workload down hierarchies of any one of claims 1-8 and/or the method for optimizing circuit gates based on workload of claim 9.
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