CN109766233A - A kind of detection circuit and its method of the delay of aware processor NBTI effect - Google Patents
A kind of detection circuit and its method of the delay of aware processor NBTI effect Download PDFInfo
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Abstract
The invention belongs to high-performance processor reliability fields, it is related to a kind of detection circuit of aware processor NBTI effect delay, including aging detection module and aging measurement module, it is characterized in that, the input terminal of the aging detection module is connect with the output end of processor critical path, the output end of the aging detection module is connect by multiplexer with the input terminal of aging measurement module, the amount of delay of the output end output processor critical path of the aging measurement module；The signal upset information that processor critical path exports is converted to pulse signal by aging detection module by the present invention, processing calculating is carried out to the pulse signal by aging measurement module, measure the amount of delay of critical path, it can accurately reflect the specific ageing state of processor, provide fine-grained information for protection.
Description
Technical field
The present invention relates to a kind of processor detection circuit and its method, specially a kind of aware processor NBTI effect delay
Detection circuit and its method, belong to high-performance processor reliability field.
Background technique
It is predicted according to International Semiconductor Technology Blueprint, with the continuous diminution of process, negative bias thermal instability
(NBTI) circuit aging caused by, the key factor for influencing chip reliability and reducing chip service life will be increasingly becoming.By
In NBTI effect, the threshold voltage Δ V of PMOSTHReachable+100 mV, so as to cause data path entirety time delay increase, cause
The generation of mistake.For micro process in the systems such as aerospace, automotive electronics, life cycle it is extremely very long (mostly 10 years with
On), working environment it is more severe, prolonged high temperature, high pressure, the work of high load capacity, can OverDrive Processor ODP aging, also to place
The life cycle of reason device brings stern challenge.
In microprocessor circuit design work, under given environmental condition and operating mode, how to make in circuit every
The NBTI degeneration amount in path accurately and can be calculated quickly, be a very crucial problem.So accurate pre-
The processor combinational logic delay under NBTI effects is surveyed, is anticipated to reliability circuitry design and circuit critical path selection analysis
Justice is great.
2007, Sensor circuit was embedded in a standard flip-flop by the S.Mitra group of Stanford University, the biography
Sensor circuit postpones clock signal using delay cell, forms detection window, defeated in upper level combinational logic to monitor
Time delay out, innovation is the ageing resistance of Sensor circuit itself, but complexity is too high, and monitors the big of window
It is small not easy to control.Thereafter, part work improves it, for example, 2011, J.Semio is a kind of online in proposing
Adaptive aging sensor prediction circuit, and monitoring function is integrated using feed circuit, significantly improve its performance.
The major defect of such method is: aging Sensor can only decision circuitry aging whether already lead to the generation of failure, cannot
The practical degree of aging of metric circuit can not submit necessary information for the anti-aging maintenance of circuit；It can not specifically detect critical path
The surplus of timing in diameter, it is difficult to fine-grained guidance is provided to the reliability design of processor, in addition, aging Sensor's is big
Amount uses, and will increase circuit load, and increasing circuit power consumption reduces circuit performance.
Summary of the invention
The purpose of the present invention is being directed to processor circuit ageing failure caused by existing NBTI effect, and then circuit is caused to prolong
When the problem of, the detection circuit and its method of a kind of delay of aware processor NBTI effect are provided, by aging detection module, with
The signal upset information that processor critical path exports is converted to pulse signal by NOT gate NAND3, passes through aging measurement module pair
The pulse signal carries out processing calculating, measures the amount of delay of critical path, can accurately reflect that processor is specifically old
Change state provides fine-grained information for protection.
To realize the above technical purpose, the technical scheme is that a kind of inspection of aware processor NBTI effect delay
Slowdown monitoring circuit, including aging detection module and aging measurement module, which is characterized in that the input terminal of the aging detection module and place
The output end connection of device critical path is managed, the output end of the aging detection module passes through multiplexer and aging measurement module
Input terminal connection, the amount of delay of the output end output processor critical path of the aging measurement module.
Further, the aging detection module include main latch D1, from latch D2, from latch D3, phase inverter
NOT1, phase inverter NOT2, NAND gate NAND1, NAND gate NAND2 and NOT gate NAND3, the signal upset information of critical path output
It is input to the end input D of main latch D1, the output end QM of main latch D1 is respectively and from the end input D of latch D2, reverse phase
The input terminal of device NOT1 connects, and the output end QMN of main latch D1 is connect with the input terminal of phase inverter NOT2, from latch D2's
The output end Q is connect with the end input D from latch D3, and the output end at the output end QS and phase inverter NOT1 from latch D3 is distinguished
Access NAND gate NAND1 input terminal, the output end at the output end QSN and phase inverter NOT2 from latch D3 be respectively connected to it is non-
The input terminal of door NAND2, the output end PR of the output end PF and NAND gate NAND2 of NAND gate NAND1 are respectively connected to a multichannel
The input terminal of multiplexer；The input terminal of the output end access NAND gate NAND3 of the multiplexer, the NOT gate NAND3's
Output end exports critical path pulse signal.
Further, the aging measurement module includes ring oscillator module, delay wire module and N-bit counter mould
Block, it is described delay wire module input terminal NAND gate NAND3 output end connection, the input terminal of the ring oscillator module with
Be delayed wire module output end connection, the ring oscillator module and delay wire module output end with N-bit counter mould
The input terminal of block connects, the amount of delay of the output end output processor critical path of the N-bit counter module.
Further, the ring oscillator module is composed in series ring oscillation circuit by a NAND gate and N number of and door,
Wherein, NAND gate generates positive feedback.
Further, the cycle of oscillation of the ring oscillator module is TRO=Ntdelay, wherein N is the number with door,
tdelayFor the propagation delay time of door, the cycle of oscillation of circuit can change in circuit with the number of door by changing.
Further, the delay wire module is composed in series by multiple NOT gates, and the frequency for the wire module that is delayed is greater than annular
The frequency of oscillation of oscillator module.
Further, the N-bit counter module calculates the retardation of pulse signal, calculation formula are as follows: and Pulsewidth=
k*TRO+ (N1-N2) * Tdelay, wherein TROFor the period of ring oscillator module, TdelayFor the period for the wire module that is delayed, k is N
Counter module counts to the number of porch.
Further, processor includes a plurality of critical path, is all connected with an aging detection module in every critical path,
Each aging detection module passes through two multiplexers and connect with aging measurement module.
Further, further include control module, the control module respectively with aging detection module, aging measurement module,
Multiplexer connection.
In order to further realize the above technical purpose, the present invention also proposes a kind of processing for detecting NBTI effect circuit delay
Device detection method, characterized in that include the following steps:
Step 1: the trigger of every critical path end of processor is connect with an aging detection module, obtains the key
The signal upset information in path；
Step 2: each aging detection module is connect with two multiplexers, and multiplexer receives aging detection mould
The information of block output, and control enable signal is exported according to control module, judge the information inputted in which paths, while simultaneously
Export the routing information；
Step 3: inputting NOT gate NAND3 for the routing information, the routing information be converted to pulse signal by NOT gate NAND3,
And give the output of pulse signal to aging measurement module；
Step 4: by pulse signal input time delay wire module, by being delayed, pulse information is completely transmitted to N meters by wire module
Number device module, while the delay time for quantifying path is calculated by ring oscillator module and N-bit counter module.
Compared with the processing circuit of tradition perception NBTI effect circuit delay, the invention has the following advantages that
(1) present invention opening or closing using enable signal control aging detection module makes module when not working in pass
Closed state can preferably reduce the dynamic power consumption of entire circuit, while the structure of aging detection module is simple, have lower face
The long-pending expense with power consumption, is embedded into processor in which can be convenient；
(2) present invention fine-grained can measure the delayed data of critical path, can accurately reflect processing implement body
Ageing state, for protection fine-grained information is provided；
(3) ring oscillator module of the invention has more flexible structure and frequency compared with traditional ring oscillator
Adjustment, and corresponding circuit structure can be obtained after electric design automation (EDA) software synthesis；
(4) all structures of the invention and all RTL level of module are realized, can preferably be integrated together with the IP kernel of processor.
Detailed description of the invention
Fig. 1 is overall structure block diagram of the present invention.
Fig. 2 is the circuit diagram of aging detection module in the present invention.
Fig. 3 is the architecture diagram of multiplexer and aging measurement module in the present invention.
Fig. 4 is the circuit diagram of ring oscillator module of the present invention.
Fig. 5 is the structural schematic diagram of aging detection module embedded position in the processor in the present invention.
Fig. 6 is the timing diagram of aging detection module of the present invention.
Fig. 7 is the timing diagram of aging measurement module of the present invention.
Description of symbols: 1- aging detection module, 2- aging measurement module, 21- ring oscillator module, 22- delay
Wire module, 23-N digit counter module, 3- multiplexer, 4- control module.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
Embodiment 1: as shown in Fig. 1, a kind of detection circuit of aware processor NBTI effect delay in the present embodiment 1,
Including aging detection module 1 and aging measurement module 2, input terminal and the processor critical path of the aging detection module 1
Output end connection, the output end of the aging detection module 1 pass through the input of two multiplexers 3 and aging measurement module 2
End connection, the amount of delay of the output end output processor critical path of the aging measurement module 2；
Further include control module 4, the control module 4 respectively with aging detection module 1, aging measurement module 2, multiplexer
3 connections.
As shown in attached drawing 2 and Fig. 3, the aging detection module 1 include main latch D1, from latch D2, from latch
D3, phase inverter NOT1, phase inverter NOT2, NAND gate NAND1, NAND gate NAND2 and NOT gate NAND3, the letter of critical path output
Number upset information is input to the end input D of main latch D1, and the output end QM of main latch D1 is respectively and from the defeated of latch D2
Entering the input terminal connection at the end D, phase inverter NOT1, the output end QMN of main latch D1 is connect with the input terminal of phase inverter NOT2, from
The output end Q of latch D2 is connect with the end input D from latch D3, from the output end QS of latch D3 with phase inverter NOT1's
Output end is respectively connected to the input terminal of NAND gate NAND1, from the output end QSN of latch D3 and the output end point of phase inverter NOT2
Not Jie Ru NAND gate NAND2 input terminal, the output end PR of the output end PF and NAND gate NAND2 of NAND gate NAND1 connects respectively
Enter the input terminal of a multiplexer 3, while the control enable signal Control vector input that control module 4 exports is more
The end EN of path multiplexer 3, the input terminal of the output end access NAND gate NAND3 of the multiplexer 3, the NOT gate NAND3
Output end export critical path pulse signal；Opening for aging detection module 1 is controlled by the enable signal of control module 3 simultaneously
It opens or closes；
The aging detection module 1 captures the signal upset information of critical path trigger by the input end D of main latch D1,
NAND gate NAND1, NAND gate NAND2 and NOT gate NAND3 handle the information, and signal upset information is converted and generates pulse
Signal, the time sequence allowance of pulsewidths representative circuit.
The aging measurement module 2 includes ring oscillator module 21, be delayed wire module 22 and N-bit counter module 23,
The output end connection of the input terminal NAND gate NAND3 of the delay wire module 22, the input terminal of the ring oscillator module 21
With delay wire module 22 output end connect, the ring oscillator module 21 and delay wire module 22 output end with N
The input terminal of counter module 23 connects, the delay of the output end output processor critical path of the N-bit counter module 23
Amount.
It is returned as shown in figure 4, the ring oscillator module 21 is composed in series ring oscillation by a NAND gate and N number of and door
Road；The cycle of oscillation of the ring oscillator module 21 is TRO=2Ntdelay, wherein N is the number with door, tdelayFor the biography of door
Defeated delay time can change the cycle of oscillation of circuit by changing with the number of door in circuit；
Wherein, NAND gate generates positive feedback, it is N number of it is concatenated play the role of delay buffering with door, by change the quantity of door with
And the type of door changes the frequency of oscillation of output end, while ring oscillator module 21 is not limited by " odd number " a, as long as
Ensure that first door obtains positive feedback and can form oscillation；
The delay wire module 22 is composed in series by multiple NOT gates, and the frequency for the wire module 22 that is delayed is greater than ring oscillator module
21 frequency of oscillation.
The N-bit counter module 23 calculates the retardation of pulse signal, calculation formula are as follows: Pulsewidth=k*TRO+
(N1-N2) * Tdelay, wherein TROFor the period of ring oscillator module 21, TdelayFor the period for the wire module 22 that is delayed, k is N meters
Number device module 23 counts to the number of porch.
As shown in figure 5, processor includes a plurality of critical path Path1, Path2 ... Path N, in every critical path
It is all connected with an aging detection module 1, each aging detection module 1 passes through two multiplexers 3 and aging measurement module 2
Connection；Embedded position connects the aging detection module 1 in the end of the trigger of each critical path in the processor
By the signal message of critical path trigger, a trigger can be the end point of a plurality of critical path, i.e. trigger may
In a plurality of critical path, they can share the same aging detection device module 1 in this way, can reduce the aging of insertion in this way
The quantity of detecting module 1 reduces circuit area and power consumption；While in order to reduce the expense of power consumption and area, all agings
Detecting module 1 shares an aging measurement module 2, and multiplexer 3 can recognize and separate the letter of each aging measurement module 2
Breath reaches the independent delay for measuring each paths.
Control module 4 in the present embodiment 1 includes single-chip microcontroller.
The processor detection method of a kind of detection NBTI effect circuit delay of embodiment 1 as above, characterized in that including such as
Lower step:
Step 1: the trigger of every critical path end of processor is connect with an aging detection module 1, obtains the pass
The signal upset information in key path；
Step 2: each aging detection module 1 is connect with two multiplexers 3, and multiplexer 3 receives aging detection
The information that module 1 exports, and control enable signal is exported according to control module 4, judge the information inputted in which paths, together
When and export the routing information；
As shown in fig. 6, being the timing diagram of aging detection module 1, CLK is clock signal waveform, and EN is enable signal waveform, and D is
The input D end signal waveform of main latch D1, QM are the output end signal waveform of main latch D1, and Q is from the defeated of latch D2
Q end signal waveform out, QS are the output QS end signal waveform from latch D3, and PF is the signal wave of NAND gate NAND1 output end
Shape, PR are the signal waveform of NAND gate NAND2 output end；Aging detection module 1 carries out the signal upset information of critical path
Processing, signal output waveform PR, PF；
Step 3: inputting NOT gate NAND3 for PR, PF signal waveform, will by the processing of aging detection module 1 and NOT gate NAND3
The routing information is converted to pulse signal, and by the output of pulse signal to aging measurement module 2；
Step 4: by pulse signal input time delay wire module 22, by being delayed, pulse information is completely transmitted to N by wire module 22
Digit counter module 4, while when calculating the delay in quantization path by ring oscillator module 21 and N-bit counter module 23
Between；
As shown in fig. 7, being the timing diagram of aging measurement module 2, EN is enable signal waveform, and RO_CLK is ring oscillator module
21 waveform diagram, TdelayFor the waveform diagram for the wire module 3 that is delayed, Pulse is the retardation of pulse signal；Loop oscillator module 21
Loop checking installation is formed by NAND gate and with door, generates the oscillator signal of 0-1 circulation.
The present invention and its embodiments have been described above, description is not limiting, it is shown in the drawings also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those skilled in the art
It is enlightened by it, without departing from the spirit of the invention, is not inventively designed similar with the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (10)
1. a kind of detection circuit of aware processor NBTI effect delay, including aging detection module (1) and aging measurement module
(2), which is characterized in that the input terminal of the aging detection module (1) is connect with the output end of processor critical path, described old
The output end for changing detecting module (1) is connect by two multiplexers (3) with the input terminal of aging measurement module (2), described
The amount of delay of the output end output processor critical path of aging measurement module (2).
2. a kind of detection circuit of aware processor NBTI effect delay according to claim 1, it is characterised in that: described
Aging detection module (1) include main latch D1, from latch D2, from latch D3, phase inverter NOT1, phase inverter NOT2, with
The signal upset information of NOT gate NAND1, NAND gate NAND2 and NAND gate NAND3, critical path output are input to main latch D1
The end input D, the output end QM of main latch D1 respectively with from latch D2 input the end D, phase inverter NOT1 input terminal connect
Connect, the output end QMN of main latch D1 is connect with the input terminal of phase inverter NOT2, from the end output Q of latch D2 with from latch
The end input D of device D3 connects, and the output end at the output end QS and phase inverter NOT1 from latch D3 is respectively connected to NAND gate NAND1
Input terminal, the output end at the output end QSN and phase inverter NOT2 from latch D3 is respectively connected to the input of NAND gate NAND2
End, the output end PR of the output end PF and NAND gate NAND2 of NAND gate NAND1 are respectively connected to the defeated of a multiplexer (3)
Enter end；The input terminal of the output end access NAND gate NAND3 of the multiplexer (3), the output end of the NOT gate NAND3 are defeated
Critical path pulse signal out.
3. a kind of detection circuit of aware processor NBTI effect delay according to claim 1, it is characterised in that: described
Aging measurement module (2) includes ring oscillator module (21), be delayed wire module (22) and N-bit counter module (23), described
The output end connection of the input terminal NAND gate NAND3 of delay wire module (22), the input terminal of the ring oscillator module (21)
It is connect with the output end of delay wire module (22), the output end of the ring oscillator module (21) and delay wire module (22) is equal
It is connect with the input terminal of N-bit counter module (23), the output end output processor critical path of the N-bit counter module (23)
The amount of delay of diameter.
4. a kind of detection circuit of aware processor NBTI effect delay according to claim 3, it is characterised in that: described
Ring oscillator module (21) is composed in series ring oscillation circuit by a NAND gate and N number of and door, wherein NAND gate generates just
Feedback.
5. a kind of detection circuit of aware processor NBTI effect delay according to claim 4, it is characterised in that: described
The cycle of oscillation of ring oscillator module (21) is TRO=2Ntdelay, wherein N is the number with door, tdelayFor the transmission delay of door
Time can change the cycle of oscillation of circuit by changing with the number of door in circuit.
6. a kind of detection circuit of aware processor NBTI effect delay according to claim 3, it is characterised in that: described
Delay wire module (22) is composed in series by multiple NOT gates, and the frequency of delay wire module (22) is greater than ring oscillator module (21)
Frequency of oscillation.
7. a kind of detection circuit of aware processor NBTI effect delay according to claim 3, it is characterised in that: described
N-bit counter module (23) calculates the retardation of pulse signal, calculation formula are as follows: Pulsewidth=k*TRO+ (N1-N2) *
Tdelay, wherein TROFor the period of ring oscillator module (21), TdelayFor the period of delay wire module (22), k is N countings
Device module (23) counts to the number of porch.
8. a kind of detection circuit of aware processor NBTI effect delay according to claim 1, it is characterised in that: processing
Device includes a plurality of critical path, is all connected with an aging detection module (1), each aging detection module in every critical path
(1) it is connect by two multiplexers (3) with aging measurement module (2).
9. a kind of detection circuit of aware processor NBTI effect delay according to claim 1, it is characterised in that: also wrap
Include control module (4), the control module (4) respectively with aging detection module (1), aging measurement module (2), multiplexer
(3) it connects.
10. a kind of detection method of aware processor NBTI effect delay as described in claim 1, characterized in that including such as
Lower step:
Step 1: the trigger of every critical path end of processor is connect with an aging detection module (1), is somebody's turn to do
The signal upset information of critical path；
Step 2: each aging detection module (1) is connect with two multiplexers (3), and multiplexer (3) receives old
Change the information of detecting module (1) output, and export control enable signal according to control module (4), judges which paths inputted
In information, while and exporting the routing information；
Step 3: inputting NOT gate NAND3 for the routing information, the routing information be converted to pulse signal by NOT gate NAND3,
And give the output of pulse signal to aging measurement module (2)；
Step 4: pulse signal input time delay wire module (3) is completely transmitted pulse information by delay wire module (3)
Quantization path is calculated to N-bit counter module (4), while by ring oscillator module (21) and N-bit counter module (23)
Delay time.
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| CN113391193A (en) * | 2021-06-25 | 2021-09-14 | 合肥工业大学 | Circuit aging test method based on BIST structure and self-oscillation ring |
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| CN113552190A (en) * | 2021-07-26 | 2021-10-26 | 电子科技大学长三角研究院(湖州) | Sensor assembly integral screening system and method for aging monitoring |
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| CN109766233B (en) | 2023-04-07 |
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