CN106970317A - A kind of degradation failure detection sensor based on protection band - Google Patents
A kind of degradation failure detection sensor based on protection band Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a kind of degradation failure detection sensor based on protection band; including delay unit, stable detection device, output latch and the first phase inverter; delay unit is used for the switch for controlling degradation failure detection sensor; the clock signal GB of delay is produced when delay unit is opened, degradation failure detection sensor is in anti-aging state when delay unit is closed；Stable detection device receives clock signal GB, the reverse signal nclk of original clock signal of delay and the CL signals of combinational logic circuit; the clock signal GB of delay and the reverse signal nclk formation protection band times of original clock signal; and detect whether combinational logic circuit signal CL saltus step occurs in the protection band time, export skip signal to output latch；Output latch is used to latch the skip signal received and sends alarm signal.The present invention is simple in construction, low in energy consumption, itself is anti-aging, reliability is high can be predicted circuit natural aging failure, can meet the requirement of chip low-power consumption.
Description
Technical field
The invention belongs to Fault of Integrated Circuits detection field, and in particular to a kind of degradation failure detection based on protection band is passed
Sensor.
Background technology
With the high speed development of semiconductor technology, the characteristic size of circuit is less and less, integrated level more and more higher, chip face
Product is less and less, and this is an inevitable direction of integrated circuit development, i.e., develop towards high integration, it can make the performance of circuit
It is improved, production cost can also be reduced.Another direction of integrated circuit development is i.e. towards high reliability development, semiconductor skill
The development of art make it that gate medium is thinning, channel shortening, and these changes bring the integrity problem of circuit simultaneously.Some reliable
Property require higher field, such as Aero-Space, reliability is even important as technical performance, even leading factor.
Aging is the natural phenomena of all things, and integrated circuit is no exception, the characteristic size drastically reduced cause one be
The negative mechanism of row accelerating circuit aging.According to the difference of the physical mechanism of its generation, they are divided into：Negative bias temperature is unstable
It is fixed, hot carrier in jection, through when dielectric breakdown, and electromigration etc..These aging effects negatively affect the time delay of circuit, make
Be continuously increased with the passage of use time, cause circuit paths sequential occur in violation of rules and regulations, mistake occurs in circuit function, finally
The life-span of circuit is influenceed, causing the performance and working frequency of chip constantly reduces, and disabler occurs in chip.How to design anti-ageing
Change circuit, extend the service life of chip, it has also become a hot issue in IC design.How monitor is old
Change situation, obtains aging data to weigh the precondition that degree of aging is anti-aging circuit design.
Chinese patent application CN102435931A, the online circuit ageing predetermination method based on measurement electric leakage change is by surveying
Amount electric leakage change carrys out prediction circuit due to aging caused by Negative Bias Temperature Instability NBTI effects, circuit can be avoided to perform
Influence of the real-time noise produced during feature operation to measurement accuracy.But it is small using scope, and detects that circuit has been at
Working condition, can increase the power consumption of circuit, while itself does not possess ageing resistance.
A kind of cmos circuit aging sensors using delay structure for amplifying of Chinese patent application CN106291322A, bag
Include with reference to delay circuit, delay detection circuit, delay amplifier, digital quantization circuit, S/R latch, the one or two input with door and
First phase inverter, with reference to delay circuit and delay detection circuit connection, is detected with reference to the output terminal of clock of delay circuit and delay
The 3rd input connection of circuit, with reference to delay circuit the second output end respectively with the one or two input and the first input end of door
With the first input end connection of delay amplifier, the output end of delay detection circuit and the first input end connection of S/R latch,
The output end of S/R latch and the second input connection of delay amplifier, delay amplifier and the connection of the first phase inverter, first
The output end of phase inverter and the one or two input are connected with the second input of door, the one or two input and the output end and digital quantity of door
Change the input connection of circuit.The sensor construction is complicated so that introduce larger power consumption when actual use to primary circuit, it is impossible to
Meet requirement nowadays to chip low-power consumption.
The content of the invention
The purpose of the present invention is to overcome the shortcoming that available circuit aging sensor is complicated, power consumption is high, can not be anti-aging,
A kind of degradation failure detection sensor based on protection band is provided, the sensor construction is simple, low in energy consumption, itself is anti-aging, can
By the predictable natural aging failure of property height.
The implementation of the present invention is as follows：A kind of degradation failure detection sensor based on protection band, including delay unit,
Stable detection device, output latch and the first phase inverter, delay unit are used for the switch for controlling degradation failure detection sensor, prolong
The clock signal GB of delay is produced when Shi Danyuan is opened, degradation failure detection sensor is in anti-aging shape when delay unit is closed
State；Stable detection device receives clock signal GB, the reverse signal nclk of original clock signal and combinational logic circuit of delay
CL signals, the clock signal GB of delay and the reverse signal nclk formation protection band times of original clock signal（That is time window
Tg）, and detect whether combinational logic circuit signal CL saltus step occurs in the protection band time, to output latch output saltus step letter
Number；Output latch is used to latch the skip signal received and sends alarm signal.
The delay unit has input end of clock, monitoring signal input（Monitor）And output end, stable detection device
With first input end, the second input, the 3rd input and output end, output latch has first input end, second defeated
Enter end and output end, the output end of delay unit is connected with the first input end of stable detection device, and the second of stable detection device is defeated
Enter end connection combinational logic circuit, the input connection clock of the first phase inverter, output end and the 3rd input of stable detection device
End connection, the output end of stable detection device connects the first input end of output latch, and the second input of output latch connects
Meet reset signal reset.
The delay unit includes two inputs and door T1, two inputs and door T2, phase inverter S1, phase inverter S2, phase inverter
S3... phase inverter Sn, two input nor gate D1, phase inverter S1 input connection monitoring signal Monitor, phase inverter S1 are defeated
Go out the first input end that end is connected to two input nor gate D1, and clk clock signals are connected to the second of two input nor gate D1
Input, two input nor gate D1 output end is connected to phase inverter S2 input, and it is defeated that phase inverter S2 output ends are connected to two
Enter the first input end with door T1, monitoring signal Monitor is connected to the second input of two inputs and door T1, two inputs and door
T1 output end is connected to phase inverter S3 input, and phase inverter S3 outputs are connected to the input of next series connection phase inverter,
Connect phase inverter number according to being adjusted the need for delay, afterbody phase inverter Sn output end be connected to two inputs with
Door T2 first input end, monitoring signal Monitor is connected to the second input of two inputs and door T2, and two inputs are with door T2's
Output is the output GB of delay unit.
The stable detection device includes basic RS filpflop H1, basic RS filpflop H2, with door T3 and door T4, phase inverter
S4, phase inverter S5, phase inverter S6, phase inverter S7, nor gate D2.Signal CL from combinational logic is connected after passing through NOT gate S9
To the first input end with door T3, the GB from delay unit is signally attached to the second input with door T3, defeated with door T3
Go out the first input end that end is connected to basic RS filpflop H1, nclk signals are connected to the second of rest-set flip-flop H1 by NOT gate S7
Input, CL signals are connected to the first input end with door T4 simultaneously, and GB is signally attached to the second input with door T4, with door
T4 output end is connected to basic RS filpflop H2 first input end, and nclk signals are connected to basic RS by phase inverter S4 and touched
Device H2 the second input is sent out, basic RS filpflop H1 output end is output to nor gate D2 the first input by phase inverter S5
End, basic RS filpflop H2 output end is output to nor gate D2 the second input by phase inverter S6, and nor gate D2's is defeated
Go out the output as Detection of Stability unit.
The output latch includes phase inverter S8, and the basic RS filpflop being made up of nor gate T5, nor gate T6
H3.Signal OUT_SC from Detection of Stability unit is connected to basic RS filpflop H3 first input end, reset signal
Reset is output to basic RS filpflop H3 the second input after passing through phase inverter S8, and basic RS filpflop H3 output is
For the output of ageing predetermination sensor.
Degradation failure detection sensor of the invention based on protection band can be plugged into circuit in several critical timing paths
Monitor the aging that their Delay Variation carrys out prediction circuit on-line.Sensor circuit is embedded in trigger and can be with tactile
Hair device equally receives the output signal from combinational logic.By delay cell to the clock signal delay regular hour, then
Detection of Stability device is sent to together with the reverse signal of original clock signal, a desired guard interval is formed（Guardband
Interval）, i.e. time window Tg, the signal saltus step of combinational logic end in time window Tg monitoring system critical paths
（Tg size is sufficiently close to a delay fault）, so as to know circuit aging situation, realize the prediction of aging.If circuit
Aging is not above defined threshold value, then in guard interval Tg saltus step does not occur for the signal of combinational logic end output.And
If to the signal that combinational logic end is exported saltus step occurs for Sensor monitoring in the range of Tg, show the aging of combinational logic
Defined threshold value is exceeded.Sensor can export a skip signal and be latched to output latch, so as to issue the user with
Alarm signal.The present invention have it is simple in construction, reasonable in design, compared to existing ageing management sensor, present invention employs
Itself anti-aging design, and early warning can be sent before delay causes fault, the power consumption of sensor is relatively low.
Brief description of the drawings
Fig. 1 is the connection figure of the degradation failure detection sensor of the invention based on protection band.
Fig. 2 is the structure chart of delay unit of the present invention.
Fig. 3 is the structure chart of Detection of Stability device in the present invention.
Fig. 4 is the structure chart of output latch in the present invention.
Fig. 5 is the structure chart of the degradation failure detection sensor of the invention based on protection band.
Fig. 6 is the degradation failure detection sensor operation principle schematic diagram of the invention based on protection band.
Embodiment
Below in conjunction with accompanying drawing, by embodiment, the invention will be further described.
Design natural aging sensor circuit can be inserted into actual use in circuit in several critical timing paths
Monitor the aging that their Delay Variation carrys out prediction circuit on-line.Aging sensor circuit is embedded in trigger and can be with
The output signal from combinational logic is equally received with trigger.
Aging sensor mainly includes delay unit 1, the stable detection device 2 for detecting aging and the part of output latch 3 three,
The data path figure of each part is as shown in Figure 1.Delay unit 1 has input end of clock, monitoring signal input
（Monitor）And output end, stable detection device 2 has first input end, the second input, the 3rd input and output end, defeated
Go out latch 3 with first input end, the second input and output end, the of the output end of delay unit 1 and stable detection device 2
One input is connected, the second input connection combinational logic circuit of stable detection device 2, the input connection of the first phase inverter 4
Clock, the output end of the first phase inverter 4 is connected with the 3rd input of stable detection device 2, the output end connection of stable detection device 2
The first input end of output latch 3, the second input connection reset signal reset of output latch 3.
As shown in Fig. 2 the delay unit 1 of the degradation failure detection sensor based on protection band of the invention include two inputs with
Door T1, two inputs and door T2, phase inverter S1, phase inverter S2, phase inverter S3...Sn, two input nor gate D1, phase inverter S1's is defeated
Enter end connection monitoring signal Monitor, phase inverter S1 output ends are connected to two input nor gate D1 first input end, and clock
Signal clk is connected to two input nor gate D1 the second input, and two input nor gate D1 output is connected to phase inverter S2's
Input, phase inverter S2 output ends are connected to the inputs of E bis- and door T1 first input end, and monitoring signal Monitor is connected to two
Input and door T1 the second input, two inputs and door T1 output end are connected to phase inverter S3 input, and phase inverter S3 is defeated
Go out end and be connected to the input of next phase inverter, the number of phase inverter is according to being adjusted the need for delay, and afterbody is anti-
Phase device Sn output end is connected to the first input end of two inputs and door T2, and monitoring signal Monitor is connected to two inputs and door
T2 the second input, two inputs and door T2 output are the output GB of delay unit 1.MONITOR is degradation failure detection
The global control signal of sensor, it is a slow clock signal, controls the switch of whole degradation failure detection sensor.When
When starting ageing management, MONITOR signals are switched on, it is not necessary to can just be closed when detecting.Monitor=1, delay unit
Open, now nor gate D1 is equivalent to a phase inverter, and clock CLK obtains CLK inversion signal after nor gate D1, then
What phase inverter can realize the time-lag action of signal, and delay unit afterbody realizes Monitor to prolonging by one with door T2
When unit switch control, output signal be delay after GB signals.Similarly, as Monitor=0, delay unit is closed,
Now this unit is in anti-aging state.Because the aging of functional circuit is a progressive process, it therefore, there is no need to aging
Predicting unit keeps work forever, so running time is considerably less, delay unit may be considered non-ageing.
As shown in figure 3, the Detection of Stability device 2 of the degradation failure detection sensor of the invention based on protection band mainly includes
Basic RS filpflop H1, basic RS filpflop H2, with door T3 and door T4, phase inverter S4, phase inverter S5, phase inverter S6, phase inverter
S7, nor gate D2.Signal CL from combinational logic is connected to first input end with door T3 after passing through NOT gate S9, from prolonging
Shi Danyuan GB is signally attached to the second input with door T3, and the of basic RS filpflop H1 is connected to door T3 output end
One input, nclk signals are connected to basic RS filpflop H1 the second input by NOT gate S7, and CL signals are connected to simultaneously
With door T4 first input end, GB is signally attached to the second input with door T4, basic RS is connected to door T4 output end
Trigger H2 first input end, nclk signals are connected to basic RS filpflop H2 the second input, base by phase inverter S4
This rest-set flip-flop H1 output end is output to nor gate D2 first input end by phase inverter S5, and basic RS filpflop H2's is defeated
Go out the second input that end is output to nor gate D2 by phase inverter S6, nor gate D2 output is Detection of Stability unit
Output.Detection of Stability device 2 is also the core cell of the design, and delay unit 1 is delayed for clock signal, the clock letter of delay
The reverse signal nclk of number GB and original clock signal is sent to the signal of Detection of Stability device 2 and is changed into 1, is then touched again by basic RS
A device H1 and NOT gate S5 is sent out, signal is maintained at 1 so that final flag signals are 0；And when nclk and GB is simultaneously 1, this two
Individual signal will construct the protection band time together, and the CL signals for being simultaneously from combinational logic circuit are also sent to Detection of Stability
Device 2, if saltus step occurs in combinational logic circuit signal CL in the time range, no matter from 0-1 or 1-0, by two nor gate groups
Into basic RS filpflop H1, H2 output be always 1, after nor gate D2 so that final flag signals are set to 1, then
Illustrate circuit aging to certain threshold value, that is, will appear from mistake.
As shown in figure 4, the output latch 3 of the degradation failure detection sensor of the invention based on protection band is mainly included instead
Phase device S8, and the basic RS filpflop H3 being made up of nor gate T5, nor gate T6.Signal from Detection of Stability unit
OUT_SC is connected to basic RS filpflop H3 first input end, and reset signal reset is output to base after passing through phase inverter S8
This rest-set flip-flop H3 the second input, basic RS filpflop H3 output is the output of ageing predetermination sensor.In Fig. 4
Reset is reset signal, when reset is 0, is 1 after phase inverter S8, knot can be made after basic RS filpflop H3
Fruit is 0, and now circuit is non-detection status；It is 0 by NOT gate S8 when reset is 1, when OUT_SC is 0, can latches
As a result, when it is 1 that OUT_SC, which is jumped, output can be put 1, sends alarm signal, so as to notify that peripheral circuit or user are timely
Circuit is adjusted, reset can be set to 0, it is necessary to reset puts 1 when detecting when detecting that circuit does not work, can so be subtracted
The working time of few latch, latch units may be considered non-ageing.
Fig. 5 is the structure chart of the degradation failure detection sensor of the invention based on protection band, degradation failure detection sensor
Delay cell receives clock signal, the reverse letter of clock signal GB, then GB signals and original clock signal for producing delay
The CL signals of number nclk and combinational logic circuit are sent to Detection of Stability unit together, the clock signal GB of delay and it is former when
The reverse signal nclk formation protection band times of clock signal（That is time window Tg）, and detect combinational logic electricity in the protection band time
Whether road signal CL there is saltus step, and testing result is output into output latch, and output latch is used to latch what is received
Skip signal simultaneously sends alarm signal.The saltus step in protection zone for CL signals marked in Fig. 6, illustrates circuit aging arrived necessarily
Threshold value.
The present invention is simple in construction, and reasonable in design, real work power consumption is relatively low, employs itself anti-aging design, and
Realize aging on-line prediction, can success prediction go out the generation of degradation failure.
Claims (4)
1. a kind of degradation failure detection sensor based on protection band, it is characterised in that the sensor includes delay unit, steady
Determine detector, output latch and the first phase inverter, delay unit is used for the switch for controlling degradation failure detection sensor, delay
The clock signal GB of delay is produced when unit is opened, degradation failure detection sensor is in anti-aging shape when delay unit is closed
State；Stable detection device receives clock signal GB, the reverse signal nclk of original clock signal and combinational logic circuit of delay
CL signals, the clock signal GB of delay and the reverse signal nclk formation protection band times of original clock signal, and detect protection band
Whether combinational logic circuit signal CL there is saltus step in time, and skip signal is exported to output latch；Output latch is used for
Latch the skip signal received and send alarm signal；The delay unit has input end of clock, monitoring signal input
And output end, stable detection utensil has first input end, the second input, the 3rd input and output end, output latch utensil
There are first input end, the second input and output end, the output end of delay unit is connected with the first input end of stable detection device,
The second input connection combinational logic circuit of stable detection device, the input connection clock of the first phase inverter, output end with it is steady
Determine the 3rd input connection of detector, the output end of stable detection device connects the first input end of output latch, output lock
The second input connection reset signal reset of storage.
2. the degradation failure detection sensor according to claim 1 based on protection band, it is characterised in that the delay list
Member includes two inputs and door T1, two inputs and door T2, phase inverter S1, phase inverter S2, phase inverter S3... phase inverters Sn, two inputs
Nor gate D1, phase inverter S1 input connection monitoring signal Monitor, phase inverter S1 output ends are connected to two input nor gates
D1 first input end, and clk clock signals are connected to two input nor gate D1 the second input, two input nor gate D1's
Output end is connected to phase inverter S2 input, and phase inverter S2 output ends are connected to the first input end of two inputs and door T1, prison
Control signal Monitor is connected to the second input of two inputs and door T1, and two inputs and door T1 output end are connected to phase inverter
S3 input, phase inverter S3 outputs are connected to the input of next series connection phase inverter, and the number for phase inverter of connecting is according to prolonging
When the need for be adjusted, afterbody phase inverter Sn output end is connected to the first input end of two inputs and door T2, monitoring
Signal Monitor is connected to the second input of two inputs and door T2, and two inputs and door T2 output are the defeated of delay unit
Go out GB.
3. the degradation failure detection sensor according to claim 1 based on protection band, it is characterised in that the stable inspection
Surveying device includes basic RS filpflop H1, basic RS filpflop H2, with door T3 and door T4, phase inverter S4, phase inverter S5, phase inverter
S6, phase inverter S7, nor gate D2；Signal CL from combinational logic is by being connected to the first input with door T3 after NOT gate S9
End, the GB from delay unit is signally attached to the second input with door T3, and being connected to basic RS with door T3 output end touches
Device H1 first input end is sent out, nclk signals are connected to rest-set flip-flop H1 the second input by NOT gate S7, and CL signals are simultaneously
The first input end with door T4 is connected to, GB is signally attached to the second input with door T4, is connected to door T4 output end
Basic RS filpflop H2 first input end, nclk signals are connected to basic RS filpflop H2 the second input by phase inverter S4
End, basic RS filpflop H1 output end is output to nor gate D2 first input end, basic RS filpflop by phase inverter S5
H2 output end is output to nor gate D2 the second input by phase inverter S6, and nor gate D2 output is Detection of Stability
The output of unit.
4. the degradation failure detection sensor according to claim 1 based on protection band, it is characterised in that the output lock
Storage includes phase inverter S8, and the basic RS filpflop H3 being made up of nor gate T5, nor gate T6；From Detection of Stability list
The signal OUT_SC of member is connected to basic RS filpflop H3 first input end, and reset signal reset passes through after phase inverter S8
Basic RS filpflop H3 the second input is output to, basic RS filpflop H3 output is the defeated of ageing predetermination sensor
Go out.
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| CN201710183825.5A CN106970317A (en) | 2017-03-24 | 2017-03-24 | A kind of degradation failure detection sensor based on protection band |
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| CN201710183825.5A CN106970317A (en) | 2017-03-24 | 2017-03-24 | A kind of degradation failure detection sensor based on protection band |
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| CN108646170A (en) * | 2018-05-15 | 2018-10-12 | 安徽理工大学 | A kind of soft fault preventing ageing predetermination sensor based on duplication redundancy |
| CN109766233A (en) * | 2019-03-08 | 2019-05-17 | 江南大学 | A kind of detection circuit and its method of the delay of aware processor NBTI effect |
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| WO2022082919A1 (en) * | 2020-10-19 | 2022-04-28 | 温州大学 | Adaptive anti-aging sensor based on cuckoo search algorithm |
| CN115856590A (en) * | 2023-03-01 | 2023-03-28 | 上海励驰半导体有限公司 | Test circuit, zero period same edge sampling circuit, test method and electronic equipment |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108107343A (en) * | 2017-11-22 | 2018-06-01 | 宁波大学 | A kind of aging sensor based on the true SH times |
| CN108646170A (en) * | 2018-05-15 | 2018-10-12 | 安徽理工大学 | A kind of soft fault preventing ageing predetermination sensor based on duplication redundancy |
| CN108646170B (en) * | 2018-05-15 | 2020-10-30 | 安徽理工大学 | Soft error aging resistant prediction sensor based on dual-mode redundancy |
| CN109766233A (en) * | 2019-03-08 | 2019-05-17 | 江南大学 | A kind of detection circuit and its method of the delay of aware processor NBTI effect |
| CN109766233B (en) * | 2019-03-08 | 2023-04-07 | 江南大学 | Detection circuit and method for sensing NBTI effect delay of processor |
| WO2022082919A1 (en) * | 2020-10-19 | 2022-04-28 | 温州大学 | Adaptive anti-aging sensor based on cuckoo search algorithm |
| US11722131B2 (en) | 2020-10-19 | 2023-08-08 | Wenzhou University | Adaptive anti-aging sensor based on cuckoo algorithm |
| CN112698181A (en) * | 2020-12-07 | 2021-04-23 | 电子科技大学 | State-configurable in-situ aging sensor system |
| CN115856590A (en) * | 2023-03-01 | 2023-03-28 | 上海励驰半导体有限公司 | Test circuit, zero period same edge sampling circuit, test method and electronic equipment |
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Application publication date: 20170721 |