CN105044623B - A kind of on-chip power supply noise peak measuring system and its measuring method suitable for IC chip - Google Patents
A kind of on-chip power supply noise peak measuring system and its measuring method suitable for IC chip Download PDFInfo
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Abstract
The invention discloses a kind of on-chip power supply noise peak measuring system and measuring method suitable for IC chip, the power supply noise peak value measurement system is amplified by electric resistance partial pressure, phase inverter, the process of trigger sampling generation digital signature, to measure the power supply noise peak value of the regional in the electric power network on IC chip in real time, and coordinate self-adaptive control module that processing is adjusted to measurement peak value, so as to reduce influence of the power supply noise to ic core piece performance.The power supply noise peak value measurement the measuring precision that the present invention is designed is higher, smaller on chip influence, thus can be used alone as chip monitoring or test to use, interference of the reduction power supply noise to chip.
Description
Technical field
It is that one kind is applied to IC chip more precisely the present invention relates to a kind of system for measuring power supply noise
Piece in real time detection power supply noise peak value measuring system.
Background technology
Integrated circuit (integrated circuit) is a kind of microelectronic device or part.Using certain technique,
Members such as transistor (transistor is the main devices in gate circuit), resistance, electric capacity and the inductance needed for a circuit
Part and wiring interconnection together, are produced on a fritter or a few fritter semiconductor wafers or dielectric substrate, are then encapsulated in a pipe
In shell, as the microstructure with required circuit function；Wherein all elements have formed a whole in structure, make electronics
Element has strided forward major step in terms of microminaturization, low-power consumption, intellectuality and high reliability.Integrated circuit is by its function, knot
The difference of structure, can be divided into Analogous Integrated Electronic Circuits, digital integrated electronic circuit and D/A hydrid integrated circuit three major types.
For 55nm and the IC chip of following technique, often integrated hundreds of millions of gate circuit, this is allowed for
In chip operation, substantial amounts of gate circuit can simultaneously be overturn in the rising edge or trailing edge of clock signal of system, in power supply
On network under the influence of dead resistance and inductance, current/resistance pressure drop (i.e. IR-Drop) can be produced and simultaneous switching noise is (i.e.) two kinds of more serious power supply noises.
" designing power supply network quickly is disclosed in application number 200910052451.9, the applying date 2009 year 06 month 03
Method ".The schematic diagram of electric power network is disclosed in Fig. 1 of this document.
The voltage peak of power supply noise in usual electric power network can reach the 20%~30% of reference voltage, can cause door
Circuit unit operating rate is reduced, and some delay path sequential may be triggered disorderly, and function breaks down.It is especially integrated at some
In circuit chip, in order to reach the metal oxidation in faster operating rate, chip using the relatively low P-channel of threshold value and N-channel
Thing semiconductor field effect transistor (PMOS/NMOS), the low-threshold circuitry unit for example used in some chips, its threshold value electricity
Pressure can as little as reference voltage 10%~15%, if power supply noise occur among these units, will greatly increase electricity
The probability of road error.
The factors such as the manufacturing process error due to IC chip, it is difficult to which simple use wiring simulation software comes
The size for the power supply noise that each part may occur in prediction chip, this is accomplished by carrying out chip actual measurement.Generally
The method used, which can be divided on piece external pelivimetry and piece, measures two kinds.Piece external pelivimetry need not modify to the layout of chip,
But its limitation is mainly reflected in also than larger：
(a) it is difficult to be measured in real time in chip real work；
(b) it is difficult to measure the power supply noise at some positions of chip internal；
(c) it is difficult to other systems in chip real work and on piece to coordinate to prevent chip function caused by power supply noise
It is not normal.
For these reasons, if necessary to monitor the power supply noise of chip in real time and make corresponding processing, one preferably
Scheme be using measuring system on piece.The advantage of measuring system is that on piece:Can be real-time in chip real work
The power supply noise of regional in the electric power network of chip is monitored, and can be adjusted with other systems cooperation.
By carrying out retrieval discovery to existing technical literature, Z.Abuhamdeh is equal to 2007 in IEEE
International Test Conference (international testing meeting) have delivered " Separating temperature
Effects from ring-oscillator rdadings to measure true ir-drop on a chip (are removed
Influence of the temperature to ring oscillator carrys out IR-Drop noises on detection lug) " propose to pass through the change for the frequency for detecting ring oscillator
The method for changing to detect power supply noise, but this method can only provide the average power supply noise in a period of time, be not directed to
The peak value of power supply noise.T.Okumoto in 2005 et al. is in IEEE Journal of Solid-State Circuits (solid-states
Circuit journal) on delivered " A built-in technique for probing power-supply noise
(one kind is built in large-scale collection to distribution within large-scale digital integrated circuits
It is used for detecting the technology of power supply noise distribution into circuit) ", it is proposed that obtain power supply wink in a kind of method of use AD samplings
When noise method, its usual sample frequency should be the several times of system clock frequency, and this will result in larger power consumption, together
When be difficult to produce so high frequency on chip.Chen-Hsiang Hsu are equal to 2013 in International
Symposium on VLSI Design, Automation and Test (international VLSI designs, automation
And test annual meeting) on delivered " Worst-case IR-drop monitoring with 1GHz sampling rate
(monitoring IR-Drop under the conditions of 1GHz sampling rates) ", the peak value of power supply noise is converted into the width of impulse wave, reduced
The loss of requirement and power to sampling rate.
Although above-mentioned document employs measuring system on piece, the measurement accuracy to power supply noise peak value is relatively low, during operation
Power consumption is larger, and measurement speed is slow.
The content of the invention
The present invention devises a kind of system for being used to measure the on-chip power supply noise peak of IC chip, and the power supply is made an uproar
Sound peak value measurement system can monitor the intensity for the power supply noise peak value being subject to during IC chip work in real time, and by certainly
The list easily influenceed on the cooperation of suitable solution module and power supply noise peak value adjustment module, real-time adjustment sheet by power supply noise
Member.Can avoid IC chip because by power consumption in larger power supply noise lead sheet it is abnormal, cause some units on piece
Disabler makes a mistake.
A kind of on-chip power supply noise peak measuring system suitable for IC chip of the present invention, the integrated circuit
Chip has N number of region according to the different demarcation of function；
Electric power network on the IC chip is described N number of block supply；
It is characterized in that：
Power supply noise peak value measurement system by self-adaptive control module (3) and with the IC chip ShangNGe areas
N number of power supply noise peak value measurement module composition of domain matching；
The power supply noise peak value measurement module set for a-quadrant is designated as first power supply noise peak value measurement module
(2A)；
The power supply noise peak value measurement module set for B regions is designated as second power supply noise peak measurement module
(2B)；
The power supply noise peak value measurement module set for n-quadrant is designated as n-th power supply noise peak value measurement module (2N)；
Described power supply noise peak value measurement module (2A, 2B ... and 2N) structure be identical；I.e.：
Power supply noise peak value measurement module is by resistance adjustment module (20D), permanent resistance module (20E), divider resistance
Array (20A), phase inverter array (20B) and flip-flop array (20C) are constituted；
Self-adaptive control module (3) first aspect receives the real-time digital signature of power supply noise peak value measurement module output
NameIn real time；Second aspect to each power supply noise peak value measurement module (2A, 2B ..., 2N) send measuring control signal WN, institute
The measuring control signal W statedNIn include work enabling signal ENWork, partial pressure control signal FV3With inverter controlling signal NV3,
That is WN={ ENWork,FV3,NV3}；The ENWorkTo set the working time node under collection several sampling periods；
Resistance adjustment module (20D), on the one hand for containing noisy power supply signal by what is receivedCarry out partial pressure；
On the other hand environment temperature T is offset by adjusting the resistance of each resistance in resistance adjustment module (20D)EnvironmentTo power supply noise
Peak value measurement module (2A, 2B ..., 2N) influence；
Permanent resistance module (20E) cooperates with resistance adjustment module (20D), realizes in divider resistance array (20A)
Voltage between adjacent resistor is in the threshold voltage V of connected phase inverter in phase inverter array (20B)Threshold valueNear；
Divider resistance array (20A) is made up of multiple series resistances；
Phase inverter array (20B) is connected between the adjacent resistor in divider resistance array (20A)；
Flip-flop array (20C) is connected in the output end of phase inverter.
The advantage for the power supply noise peak value system that the present invention is designed is：
1. the power supply noise on IC chip is detected in real time using power supply noise peak value system, it measures essence
Degree is high, and minimum measurement interval is 10mV.
2. by adjusting the resistance of resistance adjustment module, to control whether power supply noise peak value measurement module enters work
Make state；When that need not work, the resistance of resistance adjustment module is adjusted to maximum；So that power supply noise peak value measurement mould
Block is stopped, so that system power dissipation is extremely low.
3. power supply noise peak value measurement module uses resistance, phase inverter, the design of trigger, takes ic core unilateral
Product very little.
4. the regulation to the threshold voltage of phase inverter is used, is compensated come the environment temperature to system, environment temperature is offset
Spend the influence to measurement accuracy.
5. using digital signature and the fit system of supply voltage, surveyed with the power supply noise peak value measurement module of the present invention
Accuracy of measurement is influenceed minimum by IC chip manufacture craft difference.
Brief description of the drawings
Fig. 1 is the schematic diagram of electric power network and regional in traditional integrated circuit chip.
Figure 1A is the clock signal of system square wave schematic diagram of IC chip.
Figure 1B is mains voltage waveform schematic diagram when electric power network has a noise on IC chip.
Fig. 1 C are the structural representations of delay path on IC chip.
Fig. 2 is the structured flowchart that the present invention is monitored and adjusted for power supply noise peak value on IC chip.
Fig. 3 is the connection diagram of power supply noise peak value measurement module multilink of the present invention.
Fig. 3 A are the structure charts of resistance adjustment module in power supply noise peak value measurement module of the present invention.
Fig. 3 B are the structural representations of the first bit digital signature generation in power supply noise peak value measurement module of the present invention.
Fig. 3 C are the structural representations of the 30th binary digit signature generation in power supply noise peak value measurement module of the present invention.
Fig. 3 D are that the waveform for the different nodes that power supply noise peak value measurement module of the present invention is measured to power supply noise is black
Bai Tu.
Fig. 3 E are that the waveform for the different nodes that power supply noise peak value measurement module of the present invention is measured to power supply noise is color
Chromatic graph.
Fig. 4 is the structure chart of power supply noise peak value adjustment module of the present invention.
Fig. 4 A are the latency sensitives when not containing noise in power supply and power supply noise peak value adjustment module does not make regulation
The output waveform figure in path.
Fig. 4 B are when the noise contained in power supply exceedes threshold value and power supply noise peak value adjustment module does not make regulation
The output waveform figure in latency sensitive path.
Fig. 4 C are that the noise contained in power supply exceedes threshold value and power supply noise peak value adjustment module makes corresponding regulation
The output waveform figure in certain latency sensitive path afterwards.
Embodiment
Below in conjunction with drawings and examples, the present invention is described in further detail.
Power supply noise peak value measurement module that the present invention is designed (2A, 2B ... and 2N), power supply noise peak value adjustment module
(4A~4X and 5A~5Y and 6A~6Z) is embedded on existing IC chip with self-adaptive control module 3.Referring to Fig. 2 institutes
Show, power supply noise peak value measurement module (2A, 2B ... and 2N) with self-adaptive control module 3 constitute power supply noise peak value measurement
System.Power supply noise peak value adjustment module (4A~4X and 5A~5Y and 6A~6Z) constitutes power supply with self-adaptive control module 3 and made an uproar
Sound peak value regulating system.
Programming Control for IC chip employs the softwares of HSPICE 2009.HSPICE is Synopsys companies
For the steady-state analysis in IC design, the sunykatuib analysis of the circuit performance such as transient analysis and frequency-domain analysis and develop one
It is commercialized universal circuit simulation program.Its SPICE (Simulation Program with IC compared to Berkeley
Emphasis) software, the PSPICE of MicroSim companies and other circuit analysis softwares, add some new functions again,
By constantly improvement, at present by many companies, university and research and development organization's extensive use.
It is shown in Figure 3, wherein, power supply noise peak value measurement module (2A, 2B ... and 2N) pass through electric resistance partial pressure, anti-
The amplification of phase device, the detection process of trigger sampling, to measure the regional in the electric power network on IC chip in real time
Power supply noise peak value, and coordinate self-adaptive control module to measurement peak value processing is adjusted, so as to reduce power supply noise pair
The influence of ic core piece performance.Power supply noise peak value measurement the measuring precision that the present invention is designed is higher, to chip shadow
Sound is smaller, thus can be used alone as chip monitoring or test to use, interference of the reduction power supply noise to chip.
It is shown in Figure 4, wherein, power supply noise peak value adjustment module (4A~4X and 5A~5Y and 6A~6Z) is by prolonging
When Path-sensitive on increase trigger and data selector constitute Delay reconstruction path, so as to solve caused by power supply noise
The gate circuit time delay increase being attached thereto so that cause wrong output because delay is long in some latency sensitive paths；Coordinating
Under self-adaptive control module, region is adjusted in real time according to the size of the power supply noise of regional, prevented because power supply is made an uproar
Sound causes regional function to fail or generation mistake output.
(1) noise waveform in the electric power network of IC chip：
The IC chip reference voltage tested is 1.2V, and voltage digitally is 0V, when having substantial amounts of in circuit
Gate circuit unit is overturn simultaneously, or during by outside electromagnetic interference, its electric power network can produce noise, the power supply noise
So that supply voltage is fluctuated, its waveform is as shown in Figure 1B.
(2) region division in IC chip：
Shown in Figure 1, IC chip is N number of region (region) according to the different demarcation of function, such as a-quadrant, B
Region, C regions ..., n-quadrant.In Fig. 1 then by a-quadrant be designated as 1A, B region be designated as 1B ... n-quadrant is designated as 1N.
In the present invention, it is shown in Figure 2, it is due to there are N number of region on an IC chip, then matching
Power supply noise peak value measurement module be also equipped with it is N number of.The power supply noise peak value measurement module set for a-quadrant is designated as the
One power supply noise peak value measurement module 2A；The power supply noise peak value measurement module set for B regions is designated as second power supply
Noise peak measurement module 2B；The power supply noise peak value measurement module set for n-quadrant is designated as n-th power supply noise peak value and surveyed
Measure module 2N.The structure of each power supply noise peak value measurement module is identical.
Electric power network (power supply network) on IC chip is each block supply.The present invention is set
Meter power supply noise peak value measurement module (2A, 2B ... and 2N) be connected on the electric power network for each block supply.Pass through
The power supply noise (power supply noise) in each region is measured in real time to judge the power supply noise whether to the region
Impact.The voltage signal of the power supply noise of a-quadrant is designated asThe voltage signal of the power supply noise in B regions is designated asThe voltage signal of the power supply noise of n-quadrant is designated asFor convenience of explanation, it is describedAlso referred to as any one electricity
The voltage signal of source noise.
Each region (region) on IC chip there are mulitpath (paths), as shown in Figure 1 C arbitrarily
One paths (path) are made up of the gate circuit unit of preceding trigger 10A, rear trigger 10D and 2 or multiple series connection, door electricity
Road unit is located between preceding trigger 10A and rear trigger 10D.Electric signal sequentially premenstrual trigger 10A, first gate circuit unit
10B ... export electric signal after tail-gate circuit unit 10C and rear trigger 10D.
Time needed for starting point arrival terminating point of the voltage signal from path is designated as path delay.In no power supply noise
Under conditions of, reach sampling period T for the path delay of any one paths (path)Cycle95%~100%, be referred to as
Latency sensitive path (delay-sensitive path).
It is shown in Figure 2, due to there are N number of region on an IC chip, if there are P bars road in a-quadrant
Footpath, wherein have X paths for latency sensitive path, and X ∈ P.First latency sensitive path in a-quadrant is designated as 4A, most
Latter bar latency sensitive path is designated as 4X.It is quick that the power supply noise peak value adjustment module (4A~4X) that the present invention is designed is connected to delay
Feel on path (delay-sensitive path).
It is shown in Figure 2, due to there are N number of region on an IC chip, if there are Q bars road in B regions
Footpath, wherein have Y paths for latency sensitive path, and Y ∈ Q.First latency sensitive path in B regions is designated as 5A, most
Latter bar latency sensitive path is designated as 5Y.It is quick that the power supply noise peak value adjustment module (5A~5Y) that the present invention is designed is connected to delay
Feel on path (delay-sensitive path).
It is shown in Figure 2, due to there are N number of region on an IC chip, if there are R bars road in n-quadrant
Footpath, wherein have Z paths for latency sensitive path, and Z ∈ R.First latency sensitive path in n-quadrant is designated as 6A, most
Latter bar latency sensitive path is designated as 6Z.It is quick that the power supply noise peak value adjustment module (6A~6Z) that the present invention is designed is connected to delay
Feel on path (delay-sensitive path).
The power supply noise peak value adjustment module that the present invention is designed be by regulation trigger 40E, the first data selector 40F and
Second data selector 40D is constituted, as shown in Figure 4.Provided with described power supply noise peak value regulation mould in described N number of region
Block.
(3) system clock in IC chip：
Referring to shown in Figure 1A, the peak value of the clock signal of system of IC chip is 1.2V square-wave signal.In system
Clock TSystemUnder, a sampling period T is constituted between two rising edges of clock signal of systemCycle, therefore there will be has M sampling all
Phase TCycle.If by the sampling period TCycleBeginning sampling time point be designated as t1(also referred to as first sampling time point), sequentially
Respectively t2、、、、tM-1、tM、tM+1,, then t2It is both the end time in first sampling period, is second sampling time again
Point t2At the beginning of between.t2Represent second beginning sampling time point；tMRepresent that m-th starts sampling time point, when being also system
Clock TSystemUnder last start sampling time point.In the present invention, for convenience of explanation, by tMReferred to as any one starts
Sampling time point；tM-1Represent the tMPrevious beginning sampling time point；tM+1Represent the tMIt is latter when starting sampling
Between point.
(4) digital signature inquiry table：
In the electric power network (power supply network) of integrated design circuit chip, reference temperature is designated as TWith reference to,
Reference voltage in electric power network during power supply noiseless is designated as VVDD.One is often reduced for power supply noise in electric power network
Measurement interval VIntervalA supply voltage arranges value will be produced, the supply voltage arranges value is designated as MVSet, the MVSetIt is corresponding
Digital signature identification number is designated as NameSet；The MVSetWith the NameSetConstitute the digital signature inquiry table of a two row multirows
DST(digital signature table).When running IC chip, signed identification number by real-time digital
NameIn real time=[b] searches NameSetCorresponding MVSet, so as to monitor the power supply noise peak being subject to during IC chip operation
The influence of value.In the present invention, the VIntervalCan be 10mV or for 5mV.It is in the data operation digit of IC chip
At 32, from VInterval=10mV.When the data operation digit of IC chip is 64, from VInterval=5mV.
Digital signature inquiry table DST (digital signature table)：
S represents power supply noise from reference voltage VVDDReduce how many measurement interval VIntervalMultiple.
(A) if the data operation digit of monitored IC chip is 32, from power supply noiseless when reference it is electric
Source voltage VVDD9mV is have dropped, then supply voltage arranges value is designated asDigital signature identification number is designated asAnd
(B) if the data operation digit of monitored IC chip is 32, from power supply noiseless when reference it is electric
Source voltage VVDD50mV is have dropped, then supply voltage arranges value is designated asDigital signature identification number is designated as, and
(5) self-adaptive control module 3
It is shown in Figure 2, the first aspect of self-adaptive control module 3 reception power supply noise peak value measurement module (2A,
2B ... and 2N) output real-time digital signature NameIn real time。
In the present invention, self-adaptive control module 3 is recorded power supply noise peak value measurement module (2A, 2B ... and
2N) the binary system assignment matched with the data operation digit of IC chip digital [01] of output is (if operational bits are
32, then by 32 " 0 and/or 1 " to constitute the binary system assignment digital [01]), and binary system assignment digital [01] constitutes numeral
Signing messages [b], [b] is characterized with real-time digital signature, i.e. NameIn real time=[b].Real-time digital signature NameIn real time=[b]
In b for IC chip data operation digit 0 and/or 1.
In the present invention, the digital signature inquiry table DST of a two row multirows is prestored in self-adaptive control module 3
(digital signature table).When running IC chip, signed Name by real-time digitalIn real time=[b] comes
Search NameSetCorresponding MVSet, so as to monitor influenceing for the power supply noise peak value being subject to during IC chip operation.
In the present invention, by realizing real-time digital signing messages NameIn real timeIn=[b] and digital signature inquiry table DST
Digital signature information in digital signature row is compared, and is obtained and digital signature information identical digital signature identification number；So
The corresponding supply voltage of signature identification number is inquired by the digital signature identification number afterwards.Made according to the value of supply voltage
Judge, decide whether to send signal be adjusted or alarm to power supply noise peak value adjustment module.
The second aspect of self-adaptive control module 3 to each power supply noise peak value measurement module (2A, 2B ..., 2N) send
Measuring control signal WN, described measuring control signal WAIn include work enabling signal ENWork, partial pressure control signal FV3With
Inverter controlling signal NV3, i.e. WN={ ENWork,FV3,NV3}.The ENWorkTo set the work under collection several sampling periods
Timing node.
It is shown in Figure 2, power supply noise peak value adjustment module of the third aspect of self-adaptive control module 3 into each region
Data selector 40D, 40F in (4A~4X and 5A~5Y and 6A~6Z) send regulation control signal MN, described regulation control
Signal M processedNFor carrying out data flow control to data selector 40D, 40F.
(6) any one power supply noise peak value measurement module 2N
Referring to shown in Fig. 2, Fig. 3, any one power supply noise peak value measurement module 2N is by resistance adjustment module 20D, permanent electricity
Resistance module 20E, divider resistance array 20A, phase inverter array 20B and flip-flop array 20C is hindered to constitute.
Wherein, divider resistance array 20A, phase inverter array 20B and flip-flop array 20C setting number and integrated circuit
The data operation digit of chip is related.If the data operation digit of IC chip is 32, divider resistance array 20A is set
32 divider resistances are put, it is matching also to have 32 phase inverters and trigger.If the data operation digit of IC chip is
64, then 64 divider resistances of divider resistance array 20A settings, matching also to have 64 phase inverters and trigger.
Resistance adjustment module 20D
Resistance adjustment module 20D, on the one hand for containing noisy power supply signal by what is receivedCarry out partial pressure,
The voltage that partial pressure is obtained is designated as(it is referred to as branch pressure voltage), the branch pressure voltageAct on divider resistance array 20A
On；
In the present invention, resistance adjustment module 20D uses the structure that NMOS tube is combined with resistance, as shown in Figure 3A.
Partial pressure control signal FV3G ends respectively with first NMOS1 pipe, the G ends of second NMOS2 pipe and z-th
The G ends connection of NMOSz pipes；The S ends connection at the S ends of first NMOS1 pipe, the S ends of second NMOS2 pipe and z-th of NMOSz pipe
On divider resistance array 20A；The D ends of first NMOS1 pipe and resistance1 end connection；The D ends of second NMOS2 pipe
With resistance1 end connection；The D ends of z-th NMOSz pipe and resistance1 end connection；ResistanceResistance
And resistanceIt is connected to after series connection on divider resistance array 20A.Power supply UNoiseD ends input through first NMOS1 pipe.
In the present invention, when certain partial pressure control signal all the wayDuring for high level, the G ends of NMOS tube carry disconnection contact it
Series resistance afterwards so that resistance total resistance adjustment module 20D carries the series connection before disconnection contact for the G ends of NMOS tube
The resistance sum of resistance, so as to play a part of resistance regulation.When the power supply noise peak that of the invention need not be designed
When being worth measurement module work, by adjusting resistance adjustment module 20D resistance its resistance can be made maximum.So as to
Reduction uses the power consumption of power supply noise peak value measurement module.
Permanent resistance module 20E
In the present invention, permanent resistance module 20E cooperates with resistance adjustment module 20D and realizes divider resistance array 20A
In adjacent resistor between voltageThe threshold voltage of phase inverter in phase inverter array 20BNear,
I.e.Q represents the voltage difference between adjacent resistor, and value can be q=
50mV。
Divider resistance array 20A
In the present invention, for the requirement of the data operation digit that meets IC chip, then divider resistance array 20A
It is made up of, or is made up of 64 resistance of series connection (resistance is 25 Ω) 32 resistance of series connection (resistance is 50 Ω).
In divider resistance array 20A, according to branch pressure voltageSo that adjacent resistor in divider resistance array 20A it
Between output voltageThe threshold voltage value of connected phase inverter in phase inverter array 20BIt is attached
Closely.
Between adjacent first resistor 20A1 and second resistance 20A2 in expression divider resistance array 20A
Output voltage；It can similarly obtain, the output voltage between any two resistance is designated asA represents divider resistance array
Previous resistance identification number in 20A, b represents the latter resistance identification number in divider resistance array 20A.
As shown in Figure 3 B, it is connected with the first phase inverter 20B1's between the first resistor 20A1 and second resistance 20A2 of series connection
Input, the first phase inverter 20B1 output end is connected with the first trigger 20C1 prime clock signal input terminal.Then first
Output voltage adjacent with second resistance 20A2 resistance 20A1 is designated as
It can similarly obtain, the 1 of the second phase inverter 20B2 is connected between the second resistance 20A2 and 3rd resistor 20A3 of series connection
End, the second phase inverter 2,0B2 2 ends are connected with the second trigger 20C2 prime input end of clock.Then second resistance 20A2 and
Output voltage adjacent three resistance 20A3 is designated as
It can similarly obtain, as shown in Figure 3 C, connect between the 32nd resistance 20A32 of series connection and permanent resistance module 20E
The 32nd phase inverter 20,B32 1 end is connected to, the 32nd phase inverter 20,B32 2 ends are with the 32nd trigger 20C32's
Prime input end of clock is connected.Then output voltage adjacent with permanent resistance module 20E the 32nd resistance 20A32 is designated as
In the present invention, when any one region contains noisy power supplyChange, then can cause divider resistance battle array
Arrange the output voltage of adjacent resistor in 20AChange, thereforeAnd
It is change.
Phase inverter array 20B
In the present invention, a phase inverter is connected between the adjacent resistor in divider resistance array 20A, be connected to multiple
Phase inverter between series resistance constitutes phase inverter array；Phase inverter array 20B includes 32 phase inverters, i.e. the first phase inverter
20B1, the second phase inverter 20B2 ..., the 32nd phase inverter 20B32.When some region of voltage in electric power network occurs
Small change is (for example：Change more than 5mV) when, the divider resistance battle array in the power supply noise peak value measurement module in the region
Output voltage between some of 20A adjacent resistor is arranged by the threshold voltage for phase inverter of jumping over so that phase inverter output occurs
Upset.
In the phase inverter array 20B that the present invention is designed, according to phase inverter voltage difference
If Δ V ＞ 0, phase inverter output low level(during using binary expression,It is entered as 0), if Δ V≤0, instead
Phase device exports high level(during using binary expression,It is entered as 1).The VThreshold valueRefer to the input voltage of phase inverter
Equal to the voltage of output voltage.
As shown in Figure 3 B, the phase inverter voltage difference that the first phase inverter 2,0B1 1 termination is received
If Δ V20A1＞ 0, then the first phase inverter 2,0B1 2 ends output low level(during using binary expression,It is entered as
0), if Δ V20A1≤ 0, then the first phase inverter 20B1 2 ends output high level(during using binary expression,Assign
It is worth for 1).
As shown in Figure 3 C, the phase inverter voltage difference that the 32nd phase inverter 20,B32 1 termination is receivedIf Δ V20A32＞ 0, then the 32nd phase inverter 20,B32 2 ends output low level(during using binary expression,It is entered as 0), if Δ V20A32≤ 0, then the 32nd phase inverter 20,B32 2 ends
Export high level(during using binary expression,It is entered as 1).
Flip-flop array 20C
In the present invention, flip-flop array 20C include 32 two-by-two tandem compound trigger constitute, i.e., first group touch
Send out device 20C1, second group of trigger 20C2 ..., the 32nd group of trigger 20C32.Wherein, each group of trigger is previous
Individual trigger is referred to as one-level trigger element, and latter trigger is referred to as two-stage triggering unit.
In the present invention, the one-level trigger element of trigger group is connected in the output end of each phase inverter.Trigger group
Reset terminal links together, and is all first once resetted before measurement is started every time, trigger is output as low level, triggers
The prime input end of clock of the one-level trigger element of device and the output end of phase inverter are connected, data input termination supply voltage
(VDD).The data input pin of the two-stage triggering unit of trigger is connected with the output end of the one-level of trigger, and the two of trigger
Be connected with one and gate cell on the rear class input end of clock of level trigger element, with 1 end and 2 ends of gate cell respectively with integrated circuit
The system clock CLK of chip and work start information EN connections.
In the flip-flop array 20C that the present invention is designed, on the one hand exported according to phase inverterOrCome true
Whether the one-level trigger element for determining trigger starts；On the other hand according to working signal ENWorkWith system clock CLKSystemWhether can
It is enough by with gate cell, to determine whether the two-stage triggering unit of trigger starts.
In the present invention, working signal ENWorkWith system clock CLKSystemThrough with being applied to two grades of trigger after gate cell
On the rear class input end of clock of trigger element.Work as ENWorkDuring for high level, system clock CLKSystemBy with gate cell, now touch
Send out the two-stage triggering unit starting of device；Work as ENWorkDuring for low level, system clock CLKSystemCan not by with gate cell, now touch
The two-stage triggering unit of hair device does not start.
In the present invention, system clock CLKSystemFor square-wave signal, as shown in Figure 1A.
Trigger group exports high level condition：
IfThen the one-level trigger element of trigger starts, and exports high levelWhile ENWorkDuring for high level, system clock CLKSystemBy with gate cell, then the two-stage triggering unit of trigger open
It is dynamic；Now output high level of the two-stage triggering unit of trigger to the one-level trigger element of triggerSampled, and
The assignment numeral 1 of binary expression is exported to suitable solution module 30.
Trigger output low level condition one：
RemoveIn the case of, then the one-level trigger element of trigger does not start, and exports low levelWhile ENWorkDuring for low level, system clock CLKSystemThe two-stage triggering unit with gate cell, then trigger can not be passed through
Do not start；Now output of the two-stage triggering unit of trigger not to the one-level trigger element of trigger is sampled, and exports binary system
The assignment numeral 0 of expression gives suitable solution module 3.
Trigger output low level condition two：
IfThen the one-level trigger element of trigger starts, and exports high levelWhile ENWorkDuring for low level, system clock CLKSystemThe two-stage triggering unit with gate cell, then trigger can not be passed through
Do not start；Now output of the two-stage triggering unit of trigger not to the one-level trigger element of trigger is sampled, output two
The assignment numeral 0 of system expression gives suitable solution module 3.
Trigger output low level condition three：
RemoveIn the case of, then the one-level trigger element of trigger does not start, and exports low levelWhile ENWorkDuring for high level, system clock CLKSystemBy with gate cell, then the two-stage triggering unit of trigger open
It is dynamic；Now output low level of the two-stage triggering unit of trigger to the one-level trigger element of triggerSampled, and
The assignment numeral 0 of binary expression is exported to suitable solution module 3.
As shown in Figure 3 B, when receiving on the prime input end of clock of first group of trigger 20C1 one-level trigger element
It isThen first group of trigger 20C1 one-level trigger element starts, and exports high levelWhile ENWorkDuring for high level, system clock CLKSystemBy first and gate cell AND1, then first group of trigger
20C1 two-stage triggering unit starting；Now output of the first group of trigger 20C1 two-stage triggering unit to one-level trigger element
High levelSampled, and export the assignment numeral 1 of binary expression.Or：
It is not when what is received on the prime input end of clock of first group of trigger 20C1 one-level trigger elementIn the case of, then first group of trigger 20C1 one-level trigger element does not start, and exports low electricity
It is flatWhile ENWorkDuring for low level, system clock CLKSystemFirst and gate cell AND1, then first group of triggering can not be passed through
Device 20C1 two-stage triggering unit does not start；Now first group of trigger 20C1 two-stage triggering unit is not to one-level trigger element
Output sampling, export binary expression assignment numeral 0.Or：
It is when what is received on the prime input end of clock of first group of trigger 20C1 one-level trigger elementThen first group of trigger 20C1 one-level trigger element starts, and exports high level
While ENWorkDuring for low level, system clock CLKSystemCan not by with the first gate cell AND1, then first group of trigger 20C1
Two-stage triggering unit does not start；Now output of the first group of trigger 20C1 two-stage triggering unit not to one-level trigger element is adopted
Sample, exports the assignment numeral 0 of binary expression.Or：
It is not when what is received on the prime input end of clock of first group of trigger 20C1 one-level trigger elementIn the case of, then first group of trigger 20C1 one-level trigger element does not start, and exports low electricity
It is flatWhile ENWorkDuring for high level, system clock CLKSystemBy with the first gate cell AND1, then first group of trigger
20C1 two-stage triggering unit starting；Now output of the first group of trigger 20C1 two-stage triggering unit to one-level trigger element
Low levelSampled, and export the assignment numeral 0 of binary expression.
As shown in Figure 3 C, connect when on the prime input end of clock of the 32nd group of trigger 20C32 one-level trigger element
What is received isThen the 32nd group of trigger 20C32 one-level trigger element starts, and defeated
Go out high levelWhile ENWorkDuring for high level, system clock CLKSystemBy the 32nd and gate cell AND32, then
32 groups of trigger 20C32 two-stage triggering unit starting；Now the 32nd group of trigger 20C32 two-stage triggering unit
To the output high level of one-level trigger elementSampled, and export the assignment numeral 1 of binary expression.Or：
It is not when what is received on the prime input end of clock of the 32nd group of trigger 20C32 one-level trigger elementIn the case of, then the 32nd group of trigger 20C32 one-level trigger element does not start, and defeated
Go out low levelWhile ENWorkDuring for low level, system clock CLKSystemCan not by the 32nd and gate cell AND32,
Then the 32nd group of trigger 20C32 two-stage triggering unit does not start；Now two grades of the 32nd group of trigger 20C32 are touched
Bill member is not sampled to the output of one-level trigger element, exports the assignment numeral 0 of binary expression.Or：
It is when what is received on the prime input end of clock of the 32nd group of trigger 20C32 one-level trigger elementThen the 32nd group of trigger 20C32 one-level trigger element starts, and exports high levelWhile ENWorkDuring for low level, system clock CLKSystemCan not by with the 32nd gate cell AND32, then the 30th
Two groups of trigger 20C32 two-stage triggering unit does not start；Now the 32nd group of trigger 20C32 two-stage triggering unit is not
Output sampling to one-level trigger element, exports the assignment numeral 0 of binary expression.Or：
It is not when what is received on the prime input end of clock of the 32nd group of trigger 20C32 one-level trigger elementIn the case of, then the 32nd group of trigger 20C32 one-level trigger element does not start, and defeated
Go out low levelWhile ENWorkDuring for high level, system clock CLKSystemBy with the 32nd gate cell AND32, then
32 groups of trigger 20C32 two-stage triggering unit starting；Now the 32nd group of trigger 20C32 two-stage triggering unit
To the output low level of one-level trigger elementSampled, and export the assignment numeral 0 of binary expression.
In the present invention, when it is high level that work, which starts information EN, sampling clock CLK can be to the one-level of trigger
The output of trigger element is sampled, and obtains required digital signature；When it is low level that work, which starts information EN, trigger
Two-stage triggering unit can not work, that is, working starts information EN high level time and constitutes a testing window, in testing window
Interior, the flip-flop array 20C in power supply noise peak value measurement module 20 can export digital signature, otherwise can not export.
When entering testing window, (testing window refers to a period of time since the sampling time to end, and work starts letter
Breath EN is high level in testing window, and remaining period is low level) when being tested, trigger group is resetted first.When
Supply voltage, which changes, so that any one node (refers to the company between two resistance being connected in divider resistance array 20A
Contact, the tie point is referred to as node, and the input of phase inverter is connected on tie point) voltage is by the threshold voltage higher than phase inverter
Phase inverter threshold voltage is fallen below, then the phase inverter is overturn, export high level, so that the one-level triggering of the trigger group
The prime input end of clock of unit produces a rising edge so that the output of the trigger is changed into high level from low level, simultaneously
Two-stage triggering unit is sampled to one-level trigger element and exports the digital signature of composition when sampling clock rising edge arrives.Work as test
When window terminates, EN signals are low level, and the two-stage triggering unit of trigger does not work, and the digital signature of output no longer occurs
Change.Because in a testing window, the output of the one-level trigger element of trigger group can only change once, therefore when testing window knot
When beam, the corresponding supply voltage of digital signature of flip-flop array output is the minimum value in the testing window, the testing window
Interior minimum value is the peak value of the power supply noise to be tested.
In the present invention, design power supply noise peak value measurement module (2A, 2B ... and 2N) every one-level only comprising electricity
Resistance, phase inverter and two-stage trigger, are delayed less, and when power supply includes noise, its change can be rapidly in the output of trigger
End is embodied, and produces digital signature.From the foregoing, power supply noise peak value measurement module (2A, 2B ... and 2N) from electricity
Source produces noise and should be a sampling clock cycle to the first digit signature corresponding time is generated.
Influence of the operating ambient temperature to digital signature：
The threshold voltage V of NMOS tubeNMOS-thWith bias voltage VSBFormula (1) relation is there are, therefore regulation can be passed through
Bias voltage VSBTo adjust VNMOS-th。
VTORepresent the threshold voltage of MOSFET during zero-base bottom bias voltage；
γ represents base stage effect parameter；
2φFSurface potential is represented, andWherein k is Boltzmann constant, and T is the ring of work
Border temperature, q is unit charge, NAIt is doping parameters, NiIt is the intrinsically doped parameter of substrate.
The height of the threshold voltage of phase inverter is relied in view of the present invention.The threshold value electricity of NMOS tube is understood by formula (1)
Pressure and the φ of surface potential 2FIt is relevant, and the environment temperature T worked can be to φFInfluence is produced, and then influences the threshold voltage of NMOS tube
VNMOS-th.Due to the threshold voltage of phase inverterProvided by formula (2), VtpAnd VtnRespectively constitute phase inverter PMOS and
NMOS threshold voltage, as shown from the above formula, temperature can produce influence to the threshold voltage of phase inverter.
βnRepresent the amplification coefficient of NMOS tube；
βpRepresent the amplification coefficient of PMOS；
VVDDRepresent power source reference voltage.
In the present invention, in order to offset influence of the operating ambient temperature to phase inverter, the threshold of phase inverter can directly be adjusted
Threshold voltageMakeAll kept under different operating environment temperature stable.From formula (2), the threshold value electricity of phase inverter
PressureWith the PMOS and NMOS that constitute phase inverter threshold voltage Vtp、VtnIt is relevant, and VtnThreshold voltage again can pass through adjust
Save the bias voltage V of NMOS tubeSBIt is adjusted, inverter controlling voltage can be passed throughTo the threshold voltage of phase inverter
Be adjusted, with offset different operating environment temperature to power supply noise peak value measurement module (2A, 2B ... and 2N) influence.
Before measurement：The threshold voltage of phase inverter is carried out firstRegulation, when output real-time digital sign NameIn real time
" the Name of " digital signature row " in=[b] and digital signature inquiry table DSTVDD" it is identical when, stop regulation.Then power supply noise
Peak value measurement module (2A, 2B ... and 2N) normally measured.
In the present invention, power supply noise peak value measurement module (2A, 2B ... and 2N) be by divider resistance array 20A
Partial pressure is carried out to supply voltage, the different node (resistance in divider resistance array 20A will be caused when in power supply containing noise
For cascaded structure, the tie point of resistance is a node two-by-two) output voltage change.It is connected with the node anti-
Phase device, after the output voltage of each node is compared in phase inverter, will cause the output of phase inverter to change.When anti-
When the output of phase device is changed into high potential from low potential, corresponding trigger exports high potential, otherwise exports low potential.Due to partial pressure
The number of series resistance should match with the data operation digit of IC chip in electric resistance array 20A, work as operational bits
During for 32 bits or 64 bit, be connected with 32 or 64 phase inverters and trigger, thus trigger finally output 32 or
64 real-time digitals being made up of the assignment numeral 0 and 1 of binary expression of person are signed.Different real-time digital signatures correspond to not
Same supply voltage.
Power supply noise measuring method of the present invention includes the following steps：
Measuring process one, during integrated design circuit chip, passes through Design Compiler softwares (version number
2008 and more than) region division is carried out to IC chip, and mark each region；
Measuring process two, inserts self-adaptive control module 3, and insert one in each area on an integrated circuit die
Individual power supply noise peak value measurement module (2A, 2B ..., 2N) be connected to the corresponding electric power network in the region；
Measuring process three, during testing integrated circuit chip, using probe (as ACCULOGIC companies produce
Flying Probe Tester probe platforms) obtain the magnitude of voltage in each region on IC chip, and supply voltage
From 1.2V be reduced to 1.0V between digital signature；
Then, magnitude of voltage and digital signature are built into digital signature inquiry table；The digital signature inquiry table is that two row are more
Row tableau format；One is classified as supply voltage arranges value, another to be classified as digital signature identification number；
Finally, digital signature inquiry table is stored in self-adaptive control module 3, and the self-adaptive control module is set
3 threshold informations being adjusted and the threshold information for sending alarm；
Measuring process four, during operation IC chip, when chip is disturbed by power supply noise, adaptive
Control module 3 and power supply noise peak value measurement module (2A, 2B ..., 2N) co-ordination under, can complete to real on chip
When power supply noise peak value detection, and send regulation or alarm signal.
(7) any one power supply noise peak value adjustment module
Referring to shown in Fig. 1 C, in the present invention, electric signal enters from preceding trigger 10A, the door electricity through one or more series connection
After the unit of road, finally from the path of the rear trigger 10D electric signals exported, referred to as delay path.In order to illustrate gate circuit unit
Between annexation, shown in Figure 4, gate circuit unit includes first gate circuit unit 10B, tail-gate circuit unit in figure
10C and A gate circuit unit 40A, the B gate circuit units between first gate circuit unit 10B and tail-gate circuit unit 10C
40B, C gate circuit unit 40C；Wherein, A gate circuit units 40A, B gate circuit unit 40B and C gate circuit units 40C connects for series connection
Connect.
In the present invention, in the electric power network of integrated chip, sampling period T is reached for path delayCycle95%~
100% path, referred to as latency sensitive path.
In with reference to shown in Fig. 1 C, Fig. 4, connected simultaneously in the B gate circuit units 40B in latency sensitive path output end
Adjust trigger 40E and the first data selector 40F, and the first data selector 40F output end and C gate circuit units 40C
Input connection, tail-gate circuit unit 10C output end and rear trigger 10D output end simultaneously be connected to the second data
On selector 40D input, so as to constitute Delay reconstruction path.Regulation trigger 40E is used for gate circuit unit of sampling in advance
Electric signal.Data selector 40D, 40F are used to select which is used export as data flow, play a part of regulation.
Data selector 40D, 40F are controlled by self-adaptive control module 3.
B gate circuit units 40B output end is simultaneously with adjusting trigger 40E input, the first data selector 40F
Another data input pin connection.
C gate circuit units 40C input is connected with the first data selector 40F output end.
Trigger 10D output end is connected with the second data selector 40G another data input pin afterwards.
Therefore, the power supply noise peak value adjustment module designed in the present invention is used to adjust latency sensitive path, makes described
The delay in latency sensitive path changes, so as to offset the path delay caused by power supply noise.
Shown in Figure 4, the power supply noise peak value adjustment module that the present invention is designed is by regulation trigger 40E, the first data
Selector 40F and the second data selector 40D is constituted.Shown in Figure 2, IC chip has according to the different demarcation of function
Described power supply noise peak value adjustment module is provided with N number of region, described N number of region.
On the latency sensitive path of acquisition, by adjust trigger 40E input and any one gate circuit unit (10A,
10C, 40A, 40B, 40C) output end connection, the connection should meet when power supply noise exceed threshold value when, electric signal pass through weight
Structure delay path, and delay should be less than a clock cycle.
In the present invention, power supply noise peak value adjustment module (4A~4X and 5A~5Y and 6A~6Z) is one kind in integrated electricity
Make corresponding regulation to avoid the module that chip operation makes a mistake according to power supply noise on the chip of road.Power supply noise can be caused
Some region of gate circuit unit time delay increase in the electric power network being attached thereto so that the delay in some latency sensitive paths
In more than one sampling period, output error is caused, and then trigger the regional function mistake or failure.
Adjust trigger 40E
Shown in Figure 4, regulation trigger 40E is used for the electric signal of sampling gate circuit unit output in advance.Regulation triggering
Device 40E data input pin is connected with the output end of the gate circuit unit on latency sensitive path, regulation trigger 40E output
End is connected with a first data selector 40F input.
First data selector 40F
Shown in Figure 4, the first data selector 40F is used to realize that the path that flows to of electric signal to be chosen.
A first data selector 40F data input pin is connected with adjusting trigger 40E output end, the choosing of the first data
The output end that device 40F another data input pin is selected with the B gate circuit units 40B on latency sensitive path is connected, the first data
Selector 40F output end is connected with the input of the C gate circuit units 40C on latency sensitive path, the first data selector
40F control end is connected with the control end of self-adaptive control module 3.
Second data selector 40D
Shown in Figure 4, the second data selector 40G is used to realize that the path that flows to of electric signal to be chosen.
A second data selector 40G data input pin is connected with the tail-gate circuit unit 10C on delay path, and second
Data selector 40G another data input pin is connected with rear trigger 40D output end, the second data selector 40G control
End processed is connected with the control end of self-adaptive control module 3, and the second data selector 40G output end is connected with described n-quadrant.
Build Delay reconstruction path：
When the path delay on delay path (as shown in Figure 1 C) reaches sampling period TCycle95%~100% when, this
Delay path is then latency sensitive path.In order to prevent the output error in described latency sensitive path from triggering described N number of area
Capability error or the failure in domain to this latency sensitive path, it is necessary to carry out reconstructing path, so as to obtain Delay reconstruction path.
As shown in figure 4, i.e. insertion adjusts trigger and data selector in the gate circuit unit in described latency sensitive path.Then
Have：Electric signal sequentially premenstrual trigger 10A, first gate circuit unit 10B, A gate circuit unit 40A, first data selector 40F, C
Gate circuit unit 40C, tail-gate circuit unit 10C, rear trigger 10D and the second data selector 40G.
Data flow path on Delay reconstruction path：
When the power supply noise in any one region in described N number of region exceedes threshold value, the regulation of startup power supply noise peak
Module, and the regulation control signal M exported by self-adaptive control module 3NTo carry out data flow to data selector 40D, 40F
To control, its data flow path is：Electric signal sequentially premenstrual trigger 10A, first gate circuit unit 10B, A gate circuit unit
40A, regulation trigger 40E, first data selector 40F, C gate circuit unit 40C, tail-gate circuit unit 10C and the second data
Electric signal is exported after selector 40G.
Power supply noise peak value adjusting method of the present invention includes the following steps：
Regulating step one, when self-adaptive control module receive any one region power supply noise exceed threshold value information,
Then the power supply noise peak value adjustment module in the region is adjusted；
Regulating step two, when any one power supply noise peak value adjustment module receives the regulation that self-adaptive control module is sent
Information, then the power supply noise peak value adjustment module latency sensitive path is adjusted, regulation path be Delay reconstruction path；
Regulating step three, during regulation, when power supply noise is reduced to not less than threshold value, stopping is prolonged to the region
When Path-sensitive adjust.
In the present invention, system clock CLKSystemFor square-wave signal, as shown in Figure 1A.In system clock CLKSystemInside include
Multiple sampling period TCycle。
In the present invention, when IC chip is run, if the path delay time in electric power network during noiseless is designated as(and)；When IC chip is run, if during path delay when there is noise in electric power network
Between be designated as(and).Adjust behind latency sensitive path, if the path delay in electric power network during noiseless
Time is designated as(and)；Adjust behind latency sensitive path, if path when there is noise in electric power network
Time delay is designated as(and).The cycle of control path clock is sampling week in the present invention
Phase TCycle。
WhenWhen, then need that the latency sensitive path that there is noise is adjusted so that
WhenWhen, without the latency sensitive path that there is noise is adjusted.
Embodiment 1
The test that the power supply noise peak value measurement module designed using the present invention is carried out：
Tested using HSPICE softwares (version 2 008 and more than), the test is increased income storehouse using Nangate 45nm,
Electric power network plus noise is given, reference voltage is 1.20V, and noise peak is 1.17V, and the influence of noise time is 1ns.Give birth to first
Into digital signature inquiry table.Power supply plus noise is tested afterwards, (Fig. 3 E are Fig. 3 D coloured silks by simulation result such as Fig. 3 D and Fig. 3 E
Color is shown) shown in, quickly made a response when noise carrys out interim measurement module, as the decline of electric power network voltage, the 4th is anti-phase
Device, the 5th phase inverter and hex inverter are overturn in succession so that the 4th group of trigger, the 5th group of trigger and the 6th group are touched
The output for sending out the one-level trigger element of device is changed into high potential from low potential, and the one-level trigger element output of the trigger of remaining group is not
Become, while output of the two-stage triggering unit of all trigger groups to one-level trigger element is sampled, the 4th group of trigger, the
The two-stage triggering unit output of five groups of triggers and the 6th group of trigger is changed into high potential from low potential, the trigger of remaining group
The output of two-stage triggering unit is constant, so as to produce corresponding digital signature, can be inquired about and learnt according to digital signature inquiry table
This time the peak value of measurement window interior power noise is 1.17V, it was demonstrated that the power supply noise peak value measurement module that the present invention is designed can have
The measurement power supply noise peak value of effect.
Real-time digital signature form：
In Fig. 3 D and Fig. 3 E, in order to more understand phenogram 3D thus using colored Fig. 3 E come comparative illustration.In figure,
Data1 represents the waveform of the primary unit output of the 4th group of trigger.Data2 represents the primary unit output of the 5th group of trigger
Waveform.Data3 represents the waveform of the primary unit output of the 6th group of trigger.Data4 represents system clock.Data5 is represented
Power supply noise.Data6 represents the waveform of the secondary unit output of the 4th group of trigger.Data7 represents the two of the 5th group of trigger
The waveform of level unit output.Data8 represents the waveform of the secondary unit output of the 6th group of trigger.Two grades of 4th group of trigger
The waveform of unit output is overlapped with the waveform of the secondary unit output of five groups of triggers.It was found from from Fig. 3 D and Fig. 3 E, work as appearance
During power supply noise, phase inverter is overturn so that the output of corresponding trigger group is changed into high potential from low potential, and reacts fast
Speed, the reaction time can reach 0.1ns.
By the emulation testing of application HSPICE softwares, when power supply noise peak value measurement module is measured, it is averaged
Power is 1.0646 × 10-11W。
By the emulation testing of application Design Compiler (version number is Design Compiler 2008) software,
Power supply noise peak value measurement system is inserted in ITC ' 99B19 benchmark integrated circuits, and measures power supply noise peak value measurement system
Account for the percentage of the B19 integrated circuit gross areas.When inserting 1 power supply noise peak value measurement module in B19 integrated circuits, power supply
The area of noise peak measuring system accounts for the 0.624% of B19 integrated circuit areas.Insert 2 power supply noise peak value measurement modules
When, the area of power supply noise peak value measurement system accounts for the 1.106% of B19 integrated circuit areas.4 power supply noise peak values of insertion are surveyed
When measuring module, the area of power supply noise peak value measurement system accounts for the 2.071% of B19 integrated circuit areas.
Embodiment 2
The test that the power supply noise peak value adjustment module designed using the present invention is carried out：
Tested using HSPICE softwares (version 2 008 and more than), the supply voltage of the test not Noise is
1.20V, because noise causes supply voltage to drop to 1.08V.
When not Noise in power supply, the output in the latency sensitive path tested is as shown in Fig. 4 A black line segments；Work as electricity
When containing noise in source, the input to the path applies identical input, if not taking regulation measure of the present invention, its is defeated
Go out as shown in Figure 4 B, it is clear that its output there occurs mistake；The path is adjusted using the present invention, it is exported such as Fig. 4 C institutes
Show.
Contrasted through Fig. 4 C and Fig. 4 A, the two low and high level logic is identical in the identical sampling time, and output waveform is not
Identical the reason for, is in power supply to contain noise so that output waveform out-of-flatness and high level amplitude is inconsistent.
It is able to demonstrate that effectively latency sensitive path can be adjusted by the present invention by the embodiment, offsets power supply and make an uproar
Influence of the sound to latency sensitive path, prevents the output error of latency sensitive path.And then weaken power supply noise to ic core
The influence of piece, it is ensured that chip is normally run.
It is a kind of suitable for the on-chip power supply noise peak measuring system of IC chip and measurement side that the present invention is designed
Method, to be solved is under conditions of integrated circuit normal function is not influenceed, how to be measured on piece in IC chip
The technical problem of the power supply noise size of some regions, the system is supervised by adding innovative noise in existing IC chip
Geodesic structure, is measured to power supply noise peak value in real time, realizes and the power supply noise of regional is monitored in real time, if power supply noise
Peak value exceedes threshold value, then sends Regulate signal or alarm signal by adaptation module.
Claims (8)
1. a kind of on-chip power supply noise peak measuring system suitable for IC chip, the IC chip is according to work(
The different demarcation of energy has N number of region；
Electric power network on the IC chip is described N number of block supply；
It is characterized in that：
Power supply noise peak value measurement system by self-adaptive control module (3) and with N number of region on the IC chip
The N number of power supply noise peak value measurement module composition matched somebody with somebody；
The power supply noise peak value measurement module set for a-quadrant is designated as first power supply noise peak value measurement module (2A)；
The power supply noise peak value measurement module set for B regions is designated as second power supply noise peak measurement module (2B)；
The power supply noise peak value measurement module set for n-quadrant is designated as n-th power supply noise peak value measurement module (2N)；
First power supply noise peak value measurement module (2A), second power supply noise peak measurement module (2B) and n-th power supply
The structure of noise peak measurement module (2N) is identical；
Each described power supply noise peak value measurement module by resistance adjustment module (20D), permanent resistance module (20E), point
Piezoresistance array (20A), phase inverter array (20B) and flip-flop array (20C) are constituted；
Self-adaptive control module (3) first aspect receives the real-time digital signature of power supply noise peak value measurement module output
NameIn real time；Second aspect sends measuring control signal W to each power supply noise peak value measurement module (2A, 2B, 2N)N, it is described
Measuring control signal WNIn include work enabling signal ENWork, partial pressure control signal FV3With inverter controlling signal NV3, i.e. WN
={ ENWork,FV3,NV3}；The ENWorkTo set the working time node under collection several sampling periods；
Resistance adjustment module (20D), on the one hand for containing noisy power supply signal by what is receivedCarry out partial pressure；It is another
Aspect offsets environment temperature T by adjusting the resistance of each resistance in resistance adjustment module (20D)EnvironmentTo power supply noise peak value
The influence of measurement module (2A, 2B, 2N)；
Permanent resistance module (20E) cooperates with resistance adjustment module (20D), realizes adjacent in divider resistance array (20A)
Voltage between resistance is in the threshold voltage V of connected phase inverter in phase inverter array (20B)Threshold valueNear；
Divider resistance array (20A) is made up of multiple series resistances；
Phase inverter array (20B) is connected between the adjacent resistor in divider resistance array (20A)；
Flip-flop array (20C) is connected in the output end of phase inverter.
2. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：The structure that resistance adjustment module (20D) is combined using NMOS tube with resistance；The G ends connection partial pressure control signal of NMOS tube,
The D ends of NMOS tube and one end of resistance are connected, and the S ends of NMOS tube are connected on divider resistance array (20A).
3. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：Divider resistance array (20A), phase inverter array (20B) and flip-flop array in power supply noise peak value measurement system
The setting number of (20C) is related to the data operation digit of IC chip.
4. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：In phase inverter array (20B), according to voltage differenceIf Δ V ＞ 0, phase inverter exports low electricity
It is flatDuring using binary expression,It is entered as 0；If Δ V≤0, phase inverter output high levelEnter using two
When tabulation reaches,It is entered as 1；Output voltage between any two resistance is designated asA represents divider resistance array
Previous resistance identification number, b represents the latter resistance identification number of divider resistance array；The VThreshold valueRefer to the input voltage of phase inverter
Equal to the voltage of output voltage.
5. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：The previous trigger of each group of trigger is referred to as one-level trigger element, and latter trigger is referred to as two-stage triggering unit；
The reset terminal of trigger group links together, and is all first once resetted before measurement is started every time, is output as trigger
Low level, the prime input end of clock of the one-level trigger element of trigger and the output end of phase inverter are connected, data input termination
Supply voltage (VDD)；The data input pin of the two-stage triggering unit of trigger is connected with the output end of the one-level of trigger, touches
Be connected with one and gate cell on the rear class input end of clock for the two-stage triggering unit for sending out device, with 1 end and 2 ends of gate cell respectively with
The system clock CLK of IC chip and work start information EN connections.
6. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：In flip-flop array 20C, working signal ENWorkWith system clock CLKSystemThrough with being applied to the two of trigger after gate cell
On the rear class input end of clock of level trigger element；Work as ENWorkDuring for high level, system clock CLKSystemBy with gate cell, now
The two-stage triggering unit starting of trigger；Work as ENWorkDuring for low level, system clock CLKSystemCan not by with gate cell, now
The two-stage triggering unit of trigger does not start.
7. the on-chip power supply noise peak measuring system according to claim 1 suitable for IC chip, its feature
It is：Digital integrated electronic circuit and D/A hydrid integrated circuit can be applied to.
8. the peak that the on-chip power supply noise peak measuring system suitable for IC chip described in application claim 1 is carried out
Threshold voltage measuring method, it is characterised in that include the following steps：
Measuring process one, during integrated design circuit chip, by Design Compiler softwares to IC chip
Region division is carried out, and marks each region；
Measuring process two, inserts self-adaptive control module on an integrated circuit die, and inserts an electricity in each area
Source noise peak value measurement module (2A, 2B, 2N) is connected to the corresponding electric power network in the region；
Measuring process three, during testing integrated circuit chip, each region on IC chip is obtained using probe
Magnitude of voltage, and supply voltage, because of power supply noise, from standard supply voltage 1.2V be reduced to weakening supply voltage 1.0V it
Between digital signature；
Then magnitude of voltage and digital signature are built into digital signature inquiry table；The digital signature inquiry table is two row multirow forms
Structure；One is classified as supply voltage arranges value, another to be classified as digital signature identification number；
Finally digital signature inquiry table is stored in self-adaptive control module (3), and the self-adaptive control module (3) is set
The threshold information that is adjusted and the threshold information for sending alarm；
Measuring process four, during operation IC chip, when chip is disturbed by power supply noise, in Self Adaptive Control
Module (3) is with that under the co-ordination of power supply noise peak value measurement module (2A, 2B, 2N), can complete to live electrical power on chip
The detection of noise peak, and send regulation or alarm signal.
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