CN105044623A - On-chip power source noise peak value measurement system suitable for integrated circuit chip and measurement method of measurement system - Google Patents
On-chip power source noise peak value measurement system suitable for integrated circuit chip and measurement method of measurement system Download PDFInfo
- Publication number
- CN105044623A CN105044623A CN201510496187.3A CN201510496187A CN105044623A CN 105044623 A CN105044623 A CN 105044623A CN 201510496187 A CN201510496187 A CN 201510496187A CN 105044623 A CN105044623 A CN 105044623A
- Authority
- CN
- China
- Prior art keywords
- power supply
- chip
- supply noise
- integrated circuit
- noise peak
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an on-chip power source noise peak value measurement system suitable for an integrated circuit chip and a measurement method. According to the power source noise peak value measurement system, digital signatures can be generated through resistor voltage division, inverter amplification and trigger sampling, so that power source noise peak values at various regions on a power source network on the integrated circuit chip can be measured in real time; and an adaptive control module is used in cooperation, so that adjustment processing can be performed on the measured peak values, and therefore, influence of power source noises on the performance of the integrated circuit chip can be decreased. The power source noise peak value measurement system of the invention has the advantages of high measuring accuracy and little influence on the chip. The power source noise peak value measurement system can be independently used for monitoring or testing the chip so as to reduce the interference of the power source noises to the chip.
Description
Technical field
The present invention relates to a kind of system measuring power supply noise, more precisely, is the measuring system a kind of sheet being applicable to integrated circuit (IC) chip detecting in real time power supply noise peak value.
Background technology
Integrated circuit (integratedcircuit) is a kind of microelectronic device or parts.Adopt certain technique, together with the elements such as transistor (described transistor is the main devices in gate circuit) required in a circuit, resistance, electric capacity and inductance and wire interconnects, be produced on a fritter or a few fritter semiconductor wafer or dielectric substrate, then be encapsulated in a shell, become the microstructure with required circuit function; Wherein all elements structurally form a whole, make electronic component stride forward major step towards microminaturization, low-power consumption, intellectuality and high reliability aspect.Integrated circuit, by the difference of its function, structure, can be divided into Analogous Integrated Electronic Circuits, digital integrated circuit and DA combination integrated circuit three major types.
For the integrated circuit (IC) chip of 55nm and following technique, often integrated hundreds of millions of gate circuit, this just makes the gate circuit a large amount of when chip operation can overturn at the rising edge of clock signal of system or negative edge simultaneously, on electric power network dead resistance and inductance impact under, can generation current/resistance drop (i.e. IR-Drop) and simultaneous switching noise (namely
) two kinds of comparatively serious power supply noises.
At application number 200910052451.9, disclose " method of designing power supply network quickly " on 06 03rd, 2009 applying date.The schematic diagram of electric power network is disclosed in Fig. 1 of this document.
The voltage peak of the power supply noise in usual electric power network can reach 20% ~ 30% of reference voltage, and gate circuit unit operating rate can be caused to reduce, and may cause some delay path sequential disorderly, function breaks down.Especially in some integrated circuit (IC) chip, in order to reach operating rate faster, the mos field effect transistor (PMOS/NMOS) of the P raceway groove adopting threshold value lower in chip and N raceway groove, the low-threshold circuitry unit such as used in some chip, its threshold voltage can be low to moderate 10% ~ 15% of reference voltage, if power supply noise occurs among these unit, by the probability increasing circuit greatly and make mistakes.
Due to the factor such as manufacturing process error of integrated circuit (IC) chip, be difficult to the size that simple use wiring simulation software predicts the contingent power supply noise of each part in chip, this just needs to carry out actual measurement to chip.Normally used method can be divided on sheet external pelivimetry and sheet measures two kinds.Sheet external pelivimetry does not need to modify to the layout of chip, but its limitation is also larger, is mainly reflected in:
A () is difficult to measure in real time when chip real work;
B () is difficult to measure the power supply noise at some position of chip internal;
C () to be difficult to when chip real work and on sheet other system and to coordinate to prevent chip from causing malfunction because of power supply noise.
For these reasons, if need the power supply noise of Real-Time Monitoring chip and make corresponding process, a good scheme is measuring system on using sheet.On sheet, the advantage of measuring system is just: can when chip real work Real-Time Monitoring chip electric power network in the power supply noise of regional, and can coordinate with other system and regulate.
Find through carrying out retrieval to existing technical literature, Z.Abuhamdeh equals to have delivered at IEEEInternationalTestConference (international testing meeting) method that " Separatingtemperatureeffectsfromring-oscillatorrdadingst omeasuretrueir-droponachip (remove the impact of temperature on ring oscillator and carry out IR-Drop noise on detection lug) " proposes to be detected by the change of the frequency of detection ring oscillator power supply noise in 2007, but this method can only provide the average electrical source noise in a period of time, do not relate to the peak value of power supply noise.The people such as T.Okumoto in 2005 deliver on IEEEJournalofSolid-StateCircuits (solid-state circuit journal) " Abuilt-intechniqueforprobingpower-supplynoisedistributio nwithinlarge-scaledigitalintegratedcircuits (a kind of be built in large-scale integrated circuit the technology being used for detecting power supply noise distribution) ", the method in a kind of AD of use sampling of proposing is to obtain the method for power supply instantaneous noise, usually its sample frequency should be the several times of system clock frequency, this will cause larger power consumption, be difficult to produce so high frequency on chip simultaneously.Chen-HsiangHsu equals 2013 at InternationalSymposiumonVLSIDesign, AutomationandTest (international VLSI (very large scale integrated circuit) designs, robotization and test annual meeting) on delivered " Worst-caseIR-dropmonitoringwith1GHzsamplingrate (under 1GHz sampling rate condition, monitoring IR-Drop) ", the peak value of power supply noise is converted into the width of pulsating wave, reduces the loss of requirement to sampling rate and power.
Although above-mentioned document have employed measuring system on sheet, lower to the measuring accuracy of power supply noise peak value, during operation, power consumption is comparatively large, measures speed slow.
Summary of the invention
The present invention devises a kind of system of the on-chip power supply noise peak for measuring integrated circuit (IC) chip, this power supply noise peak value measurement system can the work of Real-Time Monitoring integrated circuit (IC) chip time the intensity of power supply noise peak value that is subject to, and coordinating by self-adaptive control module and power supply noise peak value adjustment module, real-time adjustment sheet is easily subject to the unit of power supply noise impact.Integrated circuit (IC) chip can be avoided because being subject to power consumption exception in larger power supply noise lead sheet, making some Elementary Function on sheet lose efficacy or make a mistake.
A kind of on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip of the present invention, described integrated circuit (IC) chip has N number of region according to the different demarcation of function;
Electric power network in described integrated circuit (IC) chip is described N number of block supply;
It is characterized in that:
Power supply noise peak value measurement system forms by self-adaptive control module (3) with N number of power supply noise peak value measurement module of the N number of Region Matching in described integrated circuit (IC) chip;
The power supply noise peak value measurement module arranged for a-quadrant is designated as first power supply noise peak value measurement module (2A);
The power supply noise peak value measurement module arranged for B region is designated as second power supply noise peak measurement module (2B);
The power supply noise peak value measurement module arranged for n-quadrant is designated as N number of power supply noise peak value measurement module (2N);
Described power supply noise peak value measurement module (2A, 2B ... and 2N) structure be identical; That is:
Power supply noise peak value measurement module is made up of resistance adjustment module (20D), permanent resistance module (20E), divider resistance array (20A), phase inverter array (20B) and flip-flop array (20C);
Self-adaptive control module (3) first aspect receives the real-time digital signature Name that power supply noise peak value measurement module exports
in real time; Second aspect to each power supply noise peak value measurement module (2A, 2B ..., 2N) send measuring control signal W
n, described measuring control signal W
nin include work enabling signal EN
work, dividing potential drop control signal FV
3with inverter controlling signal NV
3, i.e. W
n={ EN
work, FV
3, NV
3; Described EN
workfor arranging the working time node gathered under several sampling period;
Resistance adjustment module (20D), is used for containing noisy power supply signal by what receive on the one hand
carry out dividing potential drop; Environment temperature T is offset on the other hand by the resistance of each resistance in regulating resistance adjustment module (20D)
environmentto power supply noise peak value measurement module (2A, 2B ..., 2N) impact;
Permanent resistance module (20E) cooperates with resistance adjustment module (20D), and the voltage realized between the adjacent resistor in divider resistance array (20A) is in the threshold voltage V of connected phase inverter in phase inverter array (20B)
threshold valuenear;
Divider resistance array (20A) is made up of multiple resistance in series;
Phase inverter array (20B) is connected between the adjacent resistor in divider resistance array (20A);
Flip-flop array (20C) is connected on the output terminal of phase inverter.
The advantage of the power supply noise peak value system of the present invention's design is:
1. utilize power supply noise peak value system to detect in real time the power supply noise in integrated circuit (IC) chip, its measuring accuracy is high, and minimum measurement is spaced apart 10mV.
2. by the resistance of regulating resistance adjustment module, control power supply noise peak value measurement module and whether enter duty; When without the need to working, the resistance of resistance adjustment module is adjusted to maximum; Make power supply noise peak value measurement module from service, thus system power dissipation is extremely low.
3. power supply noise peak value measurement module adopts the design of resistance, phase inverter, trigger, takies integrated circuit chip area very little.
4. adopt the adjustment of the threshold voltage to phase inverter, the environment temperature of system is compensated, offset environment temperature to the impact of measuring accuracy.
5. adopt the fit system of digital signature and supply voltage, use power supply noise peak value measurement module measuring accuracy of the present invention minimum by the impact of integrated circuit (IC) chip manufacture craft difference.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of electric power network and regional in traditional integrated circuit chip.
Figure 1A is the clock signal of system square wave schematic diagram of integrated circuit (IC) chip.
Figure 1B is the mains voltage waveform schematic diagram of ic core on-chip power supply network when there is noise.
Fig. 1 C is the structural representation of delay path in integrated circuit (IC) chip.
Fig. 2 the present invention is directed to the structured flowchart that ic core on-chip power supply noise peak carries out monitoring Yu regulating.
Fig. 3 is the connection diagram of power supply noise peak value measurement module multilink of the present invention.
Fig. 3 A is the structural drawing of resistance adjustment module in power supply noise peak value measurement module of the present invention.
Fig. 3 B is the structural representation that in power supply noise peak value measurement module of the present invention, first bit digital signature generates.
Fig. 3 C is the structural representation that in power supply noise peak value measurement module of the present invention, 30 binary digit signature generates.
Fig. 3 D is that power supply noise peak value measurement module of the present invention is to the waveform artwork master of the different nodes that power supply noise is measured.
Fig. 3 E is that power supply noise peak value measurement module of the present invention is to the waveform cromogram of the different nodes that power supply noise is measured.
Fig. 4 is the structural drawing of power supply noise peak value adjustment module of the present invention.
Fig. 4 A is the output waveform figure in the latency sensitive path when not making adjustment containing noise and power supply noise peak value adjustment module in power supply.
Fig. 4 B is the output waveform figure in the latency sensitive path when the noise contained in power supply exceedes threshold value and power supply noise peak value adjustment module does not make adjustment.
Fig. 4 C exceedes threshold value and power supply noise peak value adjustment module makes the output waveform figure in certain latency sensitive path after corresponding adjustment when the noise contained in power supply.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
The present invention design power supply noise peak value measurement module (2A, 2B ... and 2N), power supply noise peak value adjustment module (4A ~ 4X and 5A ~ 5Y and 6A ~ 6Z) and self-adaptive control module 3 be embedded in existing integrated circuit (IC) chip.Shown in Figure 2, power supply noise peak value measurement module (2A, 2B ... and 2N) form power supply noise peak value measurement system with self-adaptive control module 3.Power supply noise peak value adjustment module (4A ~ 4X and 5A ~ 5Y and 6A ~ 6Z) and self-adaptive control module 3 form power supply noise peak value regulating system.
Programming Control for integrated circuit (IC) chip have employed HSPICE2009 software.The HSPICE steady-state analysis that to be Synopsys company be in integrated circuit (IC) design, the sunykatuib analysis of the circuit performance such as transient analysis and frequency-domain analysis and the commercialization universal circuit simulator program developed.It is compared to SPICE (SimulationProgramwithICEmphasis) software of Berkeley, the PSPICE of MicroSim company and other circuit analysis software, add again the function that some are new, through constantly improving, at present by many companies, university and research and development organization's widespread use.
Shown in Figure 3, wherein, power supply noise peak value measurement module (2A, 2B ... and 2N) by electric resistance partial pressure, phase inverter amplify, trigger sampling testing process, measure the power supply noise peak value of the regional in the electric power network in integrated circuit (IC) chip in real time, and coordinate self-adaptive control module to carry out adjustment process to measurement peak value, thus reduce power supply noise to the impact of ic core piece performance.The power supply noise peak value measurement the measuring precision of the present invention's design is higher, less on chip impact, thus can be used alone as chip monitoring or test use, reduce power supply noise to the interference of chip.
Shown in Figure 4, wherein, power supply noise peak value adjustment module (4A ~ 4X and 5A ~ 5Y and 6A ~ 6Z) by increasing trigger and data selector forms Delay reconstruction path on latency sensitive path, thus the gate circuit time delay the be attached thereto increase solved because power supply noise causes, make some latency sensitive path because the long output that makes the mistake of time delay; Under cooperation self-adaptive control module, the size according to the power supply noise of regional regulates region in real time, prevents from causing regional function to lose efficacy because of power supply noise or producing mistake exporting.
(1) noise waveform in the electric power network of integrated circuit (IC) chip:
The integrated circuit (IC) chip reference voltage tested is 1.2V, voltage is digitally 0V, overturn when there being a large amount of gate circuit unit in circuit simultaneously, or when being subject to outside electromagnetic interference, its electric power network can produce noise, this power supply noise makes supply voltage fluctuate, and its waveform as shown in Figure 1B.
(2) Region dividing in integrated circuit (IC) chip:
Shown in Figure 1, integrated circuit (IC) chip is N number of region (region) according to the different demarcation of function, as a-quadrant, B region, C region ..., n-quadrant.Then a-quadrant is designated as in FIG 1A, B region be designated as 1B ... n-quadrant is designated as 1N.
In the present invention, shown in Figure 2, due to an integrated circuit (IC) chip having N number of region, then the power supply noise peak value measurement module matched also is provided with N number of.Namely the power supply noise peak value measurement module arranged for a-quadrant is designated as first power supply noise peak value measurement module 2A; The power supply noise peak value measurement module arranged for B region is designated as second power supply noise peak measurement module 2B; The power supply noise peak value measurement module arranged for n-quadrant is designated as N number of power supply noise peak value measurement module 2N.The structure of each power supply noise peak value measurement module is identical.
Electric power network (powersupplynetwork) in integrated circuit (IC) chip is each block supply.The present invention design power supply noise peak value measurement module (2A, 2B ... and 2N) be connected to as each block supply electric power network on.Judge whether described power supply noise impacts this region by the power supply noise (powersupplynoise) measuring each region in real time.The voltage signal of the power supply noise of a-quadrant is designated as
the voltage signal of the power supply noise in B region is designated as
the voltage signal of the power supply noise of n-quadrant is designated as
for convenience of description, described in
also referred to as the voltage signal of any power supply noise.
Each region (region) in integrated circuit (IC) chip has mulitpath (paths), any paths (path) is made up of the gate circuit unit of front trigger 10A, rear trigger 10D and 2 or multiple series connection as shown in Figure 1 C, and gate circuit unit is between front trigger 10A and rear trigger 10D.Electric signal in turn premenstrual trigger 10A, first gate circuit unit 10B ... electric signal is exported after tail-gate circuit unit 10C and rear trigger 10D.
The time that voltage signal arrives needed for terminating point from the starting point in path is designated as path delay.Under the condition not having power supply noise, the path delay for any paths (path) reaches sampling period T
cycle95% ~ 100%, be called latency sensitive path (delay-sensitivepath).
Shown in Figure 2, due to an integrated circuit (IC) chip having N number of region, if having P paths in a-quadrant, wherein there is X paths to be latency sensitive path, and X ∈ P.Article 1 latency sensitive path in a-quadrant is designated as 4A, the last item latency sensitive path is designated as 4X.The power supply noise peak value adjustment module (4A ~ 4X) of the present invention's design is connected on latency sensitive path (delay-sensitivepath).
Shown in Figure 2, due to an integrated circuit (IC) chip having N number of region, if having Q paths in B region, wherein there is Y paths to be latency sensitive path, and Y ∈ Q.Article 1 latency sensitive path in B region is designated as 5A, the last item latency sensitive path is designated as 5Y.The power supply noise peak value adjustment module (5A ~ 5Y) of the present invention's design is connected on latency sensitive path (delay-sensitivepath).
Shown in Figure 2, due to an integrated circuit (IC) chip having N number of region, if having R paths in n-quadrant, wherein there is Z paths to be latency sensitive path, and Z ∈ R.Article 1 latency sensitive path in n-quadrant is designated as 6A, the last item latency sensitive path is designated as 6Z.The power supply noise peak value adjustment module (6A ~ 6Z) of the present invention's design is connected on latency sensitive path (delay-sensitivepath).
The power supply noise peak value adjustment module of the present invention's design is made up of adjustment trigger 40E, the first data selector 40F and the second data selector 40D, as shown in Figure 4.Described power supply noise peak value adjustment module is provided with in described N number of region.
(3) system clock in integrated circuit (IC) chip:
Shown in Figure 1A, the peak value of the clock signal of system of integrated circuit (IC) chip is the square-wave signal of 1.2V.At system clock T
systemunder, form a sampling period T between clock signal of system two rising edges
cycle, therefore will have M sampling period T
cycle.If by described sampling period T
cyclethe beginning sampling time point be designated as t
1(also referred to as first sampling time point), is respectively t in turn
2,, t
m-1, t
m, t
m+1,, then t
2being the end time in first sampling period, is again second sampling time point t
2start time.T
2represent that second starts sampling time point; t
mrepresenting that M starts sampling time point, is also system clock T
systemunder last start sampling time point.In the present invention, for convenience of description, by t
mbe called that any one starts sampling time point; t
m-1represent described t
mprevious beginning sampling time point; t
m+1represent described t
mrear one start sampling time point.
(4) digital signature question blank:
In the electric power network (powersupplynetwork) of designing integrated circuit chip, reference temperature is designated as T
reference, the reference voltage in electric power network during power supply noiseless is designated as V
vDD.Often reduce by one for power supply noise in electric power network and measure interval V
intervalwill produce supply voltage settings, these supply voltage settings are designated as MV
arrange, described MV
arrangecorresponding digital signature identification number is designated as Name
arrange; Described MV
arrangewith described Name
arrangeform the digital signature question blank DST (digitalsignaturetable) of two row multirows.When running integrated circuit (IC) chip, by real-time digital signature identification number Name
in real time=[b] searches Name
arrangecorresponding MV
arrange, thus the impact of the power supply noise peak value be subject to when monitoring integrated circuit chip runs.In the present invention, described V
intervalcan be 10mV or for 5mV.When the data operation figure place of integrated circuit (IC) chip is 32, select V
interval=10mV.When the data operation figure place of integrated circuit (IC) chip is 64, select V
interval=5mV.
Digital signature question blank DST (digitalsignaturetable):
S represents that power supply noise is from reference voltage V
vDDreduce how many and measure interval V
intervalmultiple.
(A) if the data operation figure place of monitored integrated circuit (IC) chip is 32, from reference voltage V during power supply noiseless
vDDhave dropped 9mV, then supply voltage settings are designated as
digital signature identification number is designated as
and
(B) if the data operation figure place of monitored integrated circuit (IC) chip is 32, from reference voltage V during power supply noiseless
vDDhave dropped 50mV, then supply voltage settings are designated as
digital signature identification number is designated as
, and
(5) self-adaptive control module 3
Shown in Figure 2, self-adaptive control module 3 first aspect receive power supply noise peak value measurement module (2A, 2B ... and 2N) export real-time digital signature Name
in real time.
In the present invention, self-adaptive control module 3 record power supply noise peak value measurement module (2A, 2B ... and 2N) the scale-of-two assignment numeral [01] matched with the data operation figure place of integrated circuit (IC) chip that exports is (if operational bits is 32,32 " 0 and/or 1 " are then had to form this scale-of-two assignment numeral [01]), and scale-of-two assignment numeral [01] forms digital signature information [b], described [b] characterizes with real-time digital signature, i.e. Name
in real time=[b].Real-time digital signature Name
in real timeb in=[b] is the data operation figure place individual 0 and/or 1 of integrated circuit (IC) chip.
In the present invention, the digital signature question blank DST (digitalsignaturetable) of two row multirows is prestored in self-adaptive control module 3.When running integrated circuit (IC) chip, to be signed Name by real-time digital
in real time=[b] searches Name
arrangecorresponding MV
arrange, thus the impact of the power supply noise peak value be subject to when monitoring integrated circuit chip runs.
In the present invention, by realizing real-time digital signing messages Name
in real timedigital signature information during=[b] and the digital signature in digital signature question blank DST arrange compares, and obtains the digital signature identification number identical with digital signature information; Then supply voltage corresponding to this signature identification number is inquired by described digital signature identification number.Whether the value according to supply voltage judges, determine to send to power supply noise peak value adjustment module to carry out signal that is that regulate or alarm.
Self-adaptive control module 3 second aspect to each power supply noise peak value measurement module (2A, 2B ..., 2N) send measuring control signal W
n, described measuring control signal W
ain include work enabling signal EN
work, dividing potential drop control signal FV
3with inverter controlling signal NV
3, i.e. W
n={ EN
work, FV
3, NV
3.Described EN
workfor arranging the working time node gathered under several sampling period.
Shown in Figure 2, self-adaptive control module 3 third aspect sends regulable control signal M to data selector 40D, the 40F in the power supply noise peak value adjustment module (4A ~ 4X and 5A ~ 5Y and 6A ~ 6Z) in each region
n, described regulable control signal M
nfor carrying out data flow control to data selector 40D, 40F.
(6) any one power supply noise peak value measurement module 2N
Shown in Fig. 2, Fig. 3, any one power supply noise peak value measurement module 2N is made up of resistance adjustment module 20D, permanent resistance module 20E, divider resistance array 20A, phase inverter array 20B and flip-flop array 20C.
Wherein, divider resistance array 20A, phase inverter array 20B and flip-flop array 20C to arrange number relevant to the data operation figure place of integrated circuit (IC) chip.If the data operation figure place of integrated circuit (IC) chip is 32, then divider resistance array 20A arranges 32 divider resistances, matches and also has 32 phase inverters and trigger.If the data operation figure place of integrated circuit (IC) chip is 64, then divider resistance array 20A arranges 64 divider resistances, matches and also has 64 phase inverters and trigger.
Resistance adjustment module 20D
Resistance adjustment module 20D, is used for containing noisy power supply signal by what receive on the one hand
carry out dividing potential drop, the voltage that dividing potential drop obtains is designated as
(referred to as branch pressure voltage
), this branch pressure voltage
act on divider resistance array 20A;
In the present invention, the structure that resistance adjustment module 20D adopts NMOS tube and resistance to combine, as shown in Figure 3A.
Dividing potential drop control signal FV
3hold with the G of first NMOS1 pipe respectively, the G of second NMOS2 pipe holds and the G of z NMOSz pipe holds and is connected; The S end of the S end of first NMOS1 pipe, second NMOS2 pipe and the S end of z NMOSz pipe are connected on divider resistance array 20A; The D end of first NMOS1 pipe and resistance
1 end connect; The D end of second NMOS2 pipe and resistance
1 end connect; The D end of z NMOSz pipe and resistance
1 end connect; Resistance
resistance
and resistance
be connected to after series connection on divider resistance array 20A.Power supply U
noisethrough the D end input of first NMOS1 pipe.
In the present invention, when a certain road dividing potential drop control signal
during for high level, the G end of NMOS tube carries the resistance in series after disconnection contact, and the resistance making resistance adjustment module 20D total is the resistance sum of the resistance in series before the G end year disconnection contact of NMOS tube, thus plays the effect of resistance adjustment.During the power supply noise peak value measurement module work designed when not needing the present invention, can, by the resistance of regulating resistance adjustment module 20D, make its resistance maximum.Thus reduce the power consumption using power supply noise peak value measurement module.
Permanent resistance module 20E
In the present invention, permanent resistance module 20E cooperates with resistance adjustment module 20D the voltage realizing in divider resistance array 20A between adjacent resistor
be in the threshold voltage of phase inverter in phase inverter array 20B
near, namely
q represents the voltage difference between adjacent resistor, and value can be q=50mV.
Divider resistance array 20A
In the present invention, in order to meet the requirement of the data operation figure place of integrated circuit (IC) chip, then divider resistance array 20A is made up of 32 resistance of connecting (resistance is 50 Ω), or is made up of series connection 64 resistance (resistance is 25 Ω).
In divider resistance array 20A, according to branch pressure voltage
make the output voltage between the adjacent resistor in divider resistance array 20A
be in the threshold voltage value of connected phase inverter in phase inverter array 20B
near.
output voltage between the first adjacent resistance 20A1 in expression divider resistance array 20A and the second resistance 20A2; In like manner can obtain, the output voltage between any two resistance is designated as
a represents the last resistance identification number in divider resistance array 20A, and b represents the rear resistance identification number in divider resistance array 20A.
As shown in Figure 3 B, be connected with the input end of the first phase inverter 20B1 between the first resistance 20A1 of series connection and the second resistance 20A2, the output terminal of the first phase inverter 20B1 is connected with the prime clock signal input terminal of the first trigger 20C1.The output voltage that then the first resistance 20A1 is adjacent with the second resistance 20A2 is designated as
In like manner can obtain, be connected with 1 end of the second phase inverter 20B2 between the second resistance 20A2 of series connection and the 3rd resistance 20A3,2 ends of the second phase inverter 20B2 are connected with the prime input end of clock of the second trigger 20C2.The output voltage that then the second resistance 20A2 is adjacent with the 3rd resistance 20A3 is designated as
In like manner can obtain, as shown in Figure 3 C, be connected with 1 end of the 32 phase inverter 20B32 between 32 resistance 20A32 of series connection and permanent resistance module 20E, 2 ends of the 32 phase inverter 20B32 are connected with the prime input end of clock of the 32 trigger 20C32.The output voltage that then the 32 resistance 20A32 is adjacent with permanent resistance module 20E is designated as
In the present invention, when any region is containing noisy power supply
change, then can cause the output voltage of adjacent resistor in divider resistance array 20A
change, therefore
and
it is change.
Phase inverter array 20B
In the present invention, be connected with a phase inverter between the adjacent resistor in divider resistance array 20A, the phase inverter be connected between multiple resistance in series forms phase inverter array; Phase inverter array 20B includes 32 phase inverters, namely the first phase inverter 20B1, the second phase inverter 20B2 ..., the 32 phase inverter 20B32.When there is small change (such as: the change being greater than 5mV) in the voltage in a certain region in electric power network, output voltage between some adjacent resistor in divider resistance array 20A in power supply noise peak value measurement module in this region, by the threshold voltage of phase inverter of jumping over, makes phase inverter export and overturns.
In the phase inverter array 20B of the present invention's design, according to phase inverter voltage difference
if Δ V > 0, then phase inverter output low level
(when adopting binary expression,
assignment is 0), if Δ V≤0, then phase inverter exports high level
(when adopting binary expression,
assignment is 1).Described V
threshold valuerefer to that the input voltage of phase inverter equals the voltage of output voltage.
As shown in Figure 3 B, the phase inverter voltage difference that receives of 1 termination of the first phase inverter 20B1
if Δ V
20A1> 0, the then 2 end output low levels of the first phase inverter 20B1
(when adopting binary expression,
assignment is 0), if Δ V
20A1≤ 0, then 2 ends of the first phase inverter 20B1 export high level
(when adopting binary expression,
assignment is 1).
As shown in Figure 3 C, the phase inverter voltage difference that receives of 1 termination of the 32 phase inverter 20B32
if Δ V
20A32> 0, the then 2 end output low levels of the 32 phase inverter 20B32
(when adopting binary expression,
assignment is 0), if Δ V
20A32≤ 0, then 2 ends of the 32 phase inverter 20B32 export high level
(when adopting binary expression,
assignment is 1).
Flip-flop array 20C
In the present invention, the trigger that flip-flop array 20C includes 32 tandem compounds is between two formed, namely first group of trigger 20C1, second group of trigger 20C2 ..., the 32 group of trigger 20C32.Wherein, the previous trigger of each group trigger is called one-level trigger element, and a rear trigger is called two-stage triggering unit.
In the present invention, the output terminal of each phase inverter connects the one-level trigger element of trigger group.The reset terminal of trigger group links together, all first once reset before starting measurement at every turn, make the output of trigger be low level, the prime input end of clock of the one-level trigger element of trigger is connected with the output terminal of phase inverter, and data input pin connects supply voltage (VDD).The data input pin of two-stage triggering unit of trigger is connected with the output terminal of the one-level of trigger, the rear class input end of clock of the two-stage triggering unit of trigger is connected with one and gate cell, is connected with the system clock CLK of integrated circuit (IC) chip and the log-on message EN that works respectively with 1 end of gate cell and 2 ends.
In the flip-flop array 20C of the present invention's design, export according to phase inverter on the one hand
or
determine whether the one-level trigger element of trigger starts; On the other hand according to working signal EN
workwith system clock CLK
systemwhether can by with gate cell, determine whether the two-stage triggering unit of trigger starts.
In the present invention, working signal EN
workwith system clock CLK
systemthrough with gate cell after be applied on the rear class input end of clock of the two-stage triggering unit of trigger.Work as EN
workduring for high level, system clock CLK
systemby with gate cell, now the two-stage triggering unit starting of trigger; Work as EN
workduring for low level, system clock CLK
systemnot by with gate cell, now the two-stage triggering unit of trigger does not start.
In the present invention, system clock CLK
systemfor square-wave signal, as shown in Figure 1A.
Trigger group exports high level condition:
If
then the one-level trigger element of trigger starts, and exports high level
eN simultaneously
workduring for high level, system clock CLK
systemby with gate cell, then the two-stage triggering unit starting of trigger; Now the two-stage triggering unit of trigger is to the output high level of the one-level trigger element of trigger
sample, and export binary expression assignment numeral 1 give suitable solution module 30.
Trigger output low level condition one:
Remove
in situation, then the one-level trigger element of trigger does not start, and output low level
eN simultaneously
workduring for low level, system clock CLK
systemnot by with gate cell, then the two-stage triggering unit of trigger does not start; Now the two-stage triggering unit of trigger is not sampled to the output of the one-level trigger element of trigger, exports the assignment numeral 0 of binary expression to suitable solution module 3.
Trigger output low level condition two:
If
then the one-level trigger element of trigger starts, and exports high level
eN simultaneously
workduring for low level, system clock CLK
systemnot by with gate cell, then the two-stage triggering unit of trigger does not start; Now the two-stage triggering unit of trigger is not sampled to the output of the one-level trigger element of trigger, exports the assignment numeral 0 of binary expression to suitable solution module 3.
Trigger output low level condition three:
Remove
in situation, then the one-level trigger element of trigger does not start, and output low level
eN simultaneously
workduring for high level, system clock CLK
systemby with gate cell, then the two-stage triggering unit starting of trigger; Now the two-stage triggering unit of trigger is to the output low level of the one-level trigger element of trigger
sample, and export binary expression assignment numeral 0 give suitable solution module 3.
As shown in Figure 3 B, what receive on the prime input end of clock of the one-level trigger element of first group of trigger 20C1 is
then the one-level trigger element of first group of trigger 20C1 starts, and exports high level
eN simultaneously
workduring for high level, system clock CLK
systemby first and gate cell AND1, then the two-stage triggering unit starting of first group of trigger 20C1; Now the two-stage triggering unit of first group of trigger 20C1 is to the output high level of one-level trigger element
sample, and export the assignment numeral 1 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of first group of trigger 20C1 is not
in situation, then the one-level trigger element of first group of trigger 20C1 does not start, and output low level
eN simultaneously
workduring for low level, system clock CLK
systemnot by first and gate cell AND1, then the two-stage triggering unit of first group of trigger 20C1 does not start; Now the two-stage triggering unit of first group of trigger 20C1 is not sampled to the output of one-level trigger element, exports the assignment numeral 0 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of first group of trigger 20C1 is
then the one-level trigger element of first group of trigger 20C1 starts, and exports high level
eN simultaneously
workduring for low level, system clock CLK
systemnot by with the first gate cell AND1, then the two-stage triggering unit of first group of trigger 20C1 does not start; Now the two-stage triggering unit of first group of trigger 20C1 is not sampled to the output of one-level trigger element, exports the assignment numeral 0 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of first group of trigger 20C1 is not
in situation, then the one-level trigger element of first group of trigger 20C1 does not start, and output low level
eN simultaneously
workduring for high level, system clock CLK
systemby with the first gate cell AND1, then the two-stage triggering unit starting of first group of trigger 20C1; Now the two-stage triggering unit of first group of trigger 20C1 is to the output low level of one-level trigger element
sample, and export the assignment numeral 0 of binary expression.
As shown in Figure 3 C, what receive on the prime input end of clock of the one-level trigger element of the 32 group of trigger 20C32 is
then the one-level trigger element of the 32 group of trigger 20C32 starts, and exports high level
eN simultaneously
workduring for high level, system clock CLK
systemby the 32 and gate cell AND32, then the two-stage triggering unit starting of the 32 group of trigger 20C32; Now the two-stage triggering unit of the 32 group of trigger 20C32 is to the output high level of one-level trigger element
sample, and export the assignment numeral 1 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of the 32 group of trigger 20C32 is not
in situation, then the one-level trigger element of the 32 group of trigger 20C32 does not start, and output low level
eN simultaneously
workduring for low level, system clock CLK
systemnot by the 32 and gate cell AND32, then the two-stage triggering unit of the 32 group of trigger 20C32 does not start; Now the two-stage triggering unit of the 32 group of trigger 20C32 is not sampled to the output of one-level trigger element, exports the assignment numeral 0 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of the 32 group of trigger 20C32 is
then the one-level trigger element of the 32 group of trigger 20C32 starts, and exports high level
eN simultaneously
workduring for low level, system clock CLK
systemnot by with the 32 gate cell AND32, then the two-stage triggering unit of the 32 group of trigger 20C32 does not start; Now the two-stage triggering unit of the 32 group of trigger 20C32 is not sampled to the output of one-level trigger element, exports the assignment numeral 0 of binary expression.Or:
What receive on the prime input end of clock of the one-level trigger element of the 32 group of trigger 20C32 is not
in situation, then the one-level trigger element of the 32 group of trigger 20C32 does not start, and output low level
eN simultaneously
workduring for high level, system clock CLK
systemby with the 32 gate cell AND32, then the two-stage triggering unit starting of the 32 group of trigger 20C32; Now the two-stage triggering unit of the 32 group of trigger 20C32 is to the output low level of one-level trigger element
sample, and export the assignment numeral 0 of binary expression.
In the present invention, when the log-on message EN that works is high level, sampling clock CLK can sample to the output of the one-level trigger element of trigger, obtains required digital signature; When the log-on message EN that works is low level, the two-stage triggering unit of trigger can not work, namely the high level time of log-on message EN of working forms a testing window, in testing window, flip-flop array 20C in power supply noise peak value measurement module 20 can export digital signature, otherwise can not export.
, first trigger group is resetted when testing when entering testing window (described testing window refers to a period of time terminated from the sampling time, and work log-on message EN is high level in testing window, and all the other time periods are low level).Any one node is made (to refer to the tie point between two resistance of connecting in divider resistance array 20A when supply voltage changes, this tie point is called node, tie point connects the input end of phase inverter) voltage drops to lower than phase inverter threshold voltage by the threshold voltage higher than phase inverter, then this phase inverter overturns, export high level, thus the prime input end of clock of the one-level trigger element of this trigger group produces a rising edge, the output of this trigger is made to become high level from low level, when sampling clock rising edge arrives simultaneously, two-stage triggering unit is sampled to one-level trigger element and exports the digital signature formed.When testing window terminates time, EN signal is low level, and the two-stage triggering unit of trigger does not work, and the digital signature of output no longer changes.Due in a testing window, the output of the one-level trigger element of trigger group can only change once, therefore when testing window terminates time, supply voltage corresponding to digital signature that flip-flop array exports is the minimum value in this testing window, and the minimum value in this testing window is the peak value of the power supply noise that will test.
In the present invention, design power supply noise peak value measurement module (2A, 2B ... and 2N) every one-level only comprise resistance, phase inverter and two-stage trigger, time delay is less, when power supply comprises noise, its change can be embodied at the output terminal of trigger rapidly, produces digital signature.From the above, power supply noise peak value measurement module (2A, 2B ... and 2N) shoulding be a sampling clock cycle from power supply generation noise to the time generating first digit signature corresponding.
Operating ambient temperature is on the impact of digital signature:
The threshold voltage V of NMOS tube
nMOS-thwith bias voltage V
sBhave formula (1) relation, therefore can by regulating bias voltage V
sBregulate V
nMOS-th.
V
tOrepresent the threshold voltage of MOSFET during bias voltage at the bottom of zero-base;
γ represents base stage effect parameter;
2 φ
fpresentation surface electromotive force, and
wherein k is Boltzmann constant, and T is the environment temperature of work, and q is unit charge, N
adoping parameters, N
iit is the intrinsic doping parameters of substrate.
Consider that the present invention relies on the height of the threshold voltage of phase inverter.By threshold voltage and surface potential 2 φ of formula (1) known NMOS tube
frelevant, and the environment temperature T of work can to φ
fhave an impact, and then affect the threshold voltage V of NMOS tube
nMOS-th.Due to the threshold voltage of phase inverter
provided by formula (2), V
tpand V
tnbe respectively the threshold voltage of PMOS and NMOS forming phase inverter, as shown from the above formula, temperature can have an impact to the threshold voltage of phase inverter.
β
nrepresent the amplification coefficient of NMOS tube;
β
prepresent the amplification coefficient of PMOS;
V
vDDrepresent power source reference voltage.
In the present invention, in order to offset the impact of operating ambient temperature on phase inverter, the threshold voltage of phase inverter can directly be regulated
make
under different operating environment temperature, all keep stable.From formula (2), the threshold voltage of phase inverter
with the threshold voltage V of PMOS and NMOS of formation phase inverter
tp, V
tnrelevant, and V
tnthreshold voltage again can by regulating the bias voltage V of NMOS tube
sBregulate, by inverter controlling voltage
to the threshold voltage of phase inverter
regulate, with offset different operating environment temperature to power supply noise peak value measurement module (2A, 2B ... and 2N) impact.
Before measurement: the threshold voltage first carrying out phase inverter
adjustment, when export real-time digital signature Name
in real time" the Name of " digital signature arranges " in=[b] and digital signature question blank DST
vDD" identical time, stop regulate.Then power supply noise peak value measurement module (2A, 2B ... and 2N) normally measure.
In the present invention, power supply noise peak value measurement module (2A, 2B ... and 2N) be, by divider resistance array 20A, dividing potential drop is carried out to supply voltage, when the output voltage of the different nodes in divider resistance array 20A (resistance is cascaded structure, and the tie point of resistance is a node between two) being caused to change containing during noise in power supply.Be connected with phase inverter at described Nodes, after the output voltage of each node compares in phase inverter, the output of phase inverter will be made to change.When the output of phase inverter becomes noble potential from electronegative potential, corresponding trigger exports noble potential, otherwise exports electronegative potential.Because the number of resistance in series in divider resistance array 20A should match with the data operation figure place of integrated circuit (IC) chip, when operational bits be 32 bits or 64 bit time, be connected with 32 or 64 phase inverters and trigger, therefore trigger finally exports 32 or 64 real-time digitals signatures be made up of the assignment numeral 0 and 1 of binary expression.Different real-time digital signatures correspond to different supply voltages.
Power supply noise measuring method of the present invention includes the following step:
Measuring process one, in designing integrated circuit chip processes, carries out Region dividing by DesignCompiler software (version number 2008 and more than) to integrated circuit (IC) chip, and marks each region;
Measuring process two, inserts self-adaptive control module 3 on an integrated circuit die, and insert in each area power supply noise peak value measurement module (2A, 2B ..., 2N) be connected to electric power network corresponding to this region;
Measuring process three, in testing integrated circuit chip process, adopt probe (as the FlyingProbeTester probe platform that ACCULOGIC company produces) to obtain the magnitude of voltage in each region in integrated circuit (IC) chip, and supply voltage is reduced to the digital signature between 1.0V from 1.2V;
Then, magnitude of voltage and digital signature are built digital signature question blank; Described digital signature question blank is two row multirow tableau formats; One is classified as supply voltage settings, and another is classified as digital signature identification number;
Finally, digital signature question blank is stored in self-adaptive control module 3, and described self-adaptive control module 3 is set carries out the threshold information regulated and the threshold information given the alarm;
Measuring process four, in operation integrated circuit (IC) chip process, when chip is subject to power supply noise interference, self-adaptive control module 3 and power supply noise peak value measurement module (2A, 2B ..., 2N) co-ordination under, the detection to live electrical power noise peak on chip can be completed, and send adjustment or alerting signal.
(7) any one power supply noise peak value adjustment module
Shown in Fig. 1 C, in the present invention, electric signal in the past trigger 10A enters, and after the gate circuit unit of one or more series connection, finally from the path of the electric signal of rear trigger 10D output, is called delay path.In order to the annexation between gate circuit unit is described, shown in Figure 4, in figure, gate circuit unit includes first gate circuit unit 10B, tail-gate circuit unit 10C and the A gate circuit unit 40A between first gate circuit unit 10B and tail-gate circuit unit 10C, B gate circuit unit 40B, C gate circuit unit 40C; Wherein, A gate circuit unit 40A, B gate circuit unit 40B and C gate circuit unit 40C are for being connected in series.
In the present invention, in the electric power network of integrated chip, sampling period T is reached for path delay
cycle95% ~ 100% path, be called latency sensitive path.
In shown in composition graphs 1C, Fig. 4, the output terminal of the B gate circuit unit 40B in latency sensitive path connects simultaneously and regulates trigger 40E and the first data selector 40F, and the output terminal of the first data selector 40F is connected with the input end of C gate circuit unit 40C, be connected on the input end of the second data selector 40D at the output terminal of tail-gate circuit unit 10C and the output terminal of rear trigger 10D simultaneously, thus form Delay reconstruction path.Trigger 40E is regulated to be used for the electric signal of sampling gate circuit unit in advance.Data selector 40D, 40F export which for choice for use as data flow, play the effect of adjustment.Data selector 40D, 40F are controlled by self-adaptive control module 3.
The output terminal of B gate circuit unit 40B is connected with the input end of adjustment trigger 40E, another data input pin of the first data selector 40F simultaneously.
The input end of C gate circuit unit 40C is connected with the output terminal of the first data selector 40F.
The output terminal of rear trigger 10D is connected with another data input pin of the second data selector 40G.
Therefore, the power supply noise peak value adjustment module designed in the present invention, for regulating latency sensitive path, makes the time delay in described latency sensitive path change, thus offsets the path delay because power supply noise causes.
Shown in Figure 4, the power supply noise peak value adjustment module of the present invention's design is formed by regulating trigger 40E, the first data selector 40F and the second data selector 40D.Shown in Figure 2, integrated circuit (IC) chip has N number of region according to the different demarcation of function, is provided with described power supply noise peak value adjustment module in described N number of region.
On the latency sensitive path obtained, be connected regulating the input end of trigger 40E with the output terminal of any gate circuit unit (10A, 10C, 40A, 40B, 40C), this connection should meet when power supply noise exceedes threshold value, electric signal is by reconstruct delay path, and time delay should be less than a clock period.
In the present invention, power supply noise peak value adjustment module (4A ~ 4X and 5A ~ 5Y and 6A ~ 6Z) is that a kind of making according to power supply noise on an integrated circuit die regulates accordingly to avoid chip to run the module made a mistake.Power supply noise can cause the gate circuit unit time delay in a certain region in the electric power network be attached thereto to increase, and makes the time delay in some latency sensitive path more than a sampling period, causes output error, and then cause this regional function mistake or inefficacy.
Regulate trigger 40E
Shown in Figure 4, regulate trigger 40E to be used for the electric signal of sampling gate circuit unit output in advance.Regulate the data input pin of trigger 40E to be connected with the output terminal of the gate circuit unit on latency sensitive path, regulate the output terminal of trigger 40E to be connected with an input end of the first data selector 40F.
First data selector 40F
Shown in Figure 4, the first data selector 40F chooses for the path that flows to realizing electric signal.
One data input pin of the first data selector 40F is connected with regulating the output terminal of trigger 40E, another data input pin of first data selector 40F is connected with the output terminal of the B gate circuit unit 40B on latency sensitive path, the output terminal of the first data selector 40F is connected with the input end of the C gate circuit unit 40C on latency sensitive path, and the control end of the first data selector 40F is connected with the control end of self-adaptive control module 3.
Second data selector 40D
Shown in Figure 4, the second data selector 40G chooses for the path that flows to realizing electric signal.
One data input pin of the second data selector 40G is connected with the tail-gate circuit unit 10C on delay path, another data input pin of second data selector 40G is connected with the output terminal of rear trigger 40D, the control end of the second data selector 40G is connected with the control end of self-adaptive control module 3, and the output terminal of the second data selector 40G is connected with described n-quadrant.
Build Delay reconstruction path:
When the path delay on delay path (as shown in Figure 1 C) reaches sampling period T
cycle95% ~ 100% time, this delay path is then latency sensitive path.In order to stop the output error in described latency sensitive path cause described in the capability error in N number of region or inefficacy, need to carry out reconstructing path to this latency sensitive path, thus obtain Delay reconstruction path.As shown in Figure 4, namely in the gate circuit unit in described latency sensitive path, adjustment trigger and data selector is inserted.Then have: electric signal is premenstrual trigger 10A, first gate circuit unit 10B, A gate circuit unit 40A, first data selector 40F, C gate circuit unit 40C, tail-gate circuit unit 10C, rear trigger 10D and the second data selector 40G in turn.
Data flow path on Delay reconstruction path:
The power supply noise in any region in described N number of region exceedes threshold value, starts power supply noise peak value adjustment module, and by regulable control signal M that self-adaptive control module 3 exports
ncarry out data flow control to data selector 40D, 40F, its data flow path is: electric signal in turn premenstrual trigger 10A, first gate circuit unit 10B, A gate circuit unit 40A, regulate trigger 40E, first data selector 40F, C gate circuit unit 40C, tail-gate circuit unit 10C and the second data selector 40G after export electric signal.
Power supply noise peak value control method of the present invention includes the following step:
Regulating step one, the power supply noise receiving any region when self-adaptive control module exceedes the information of threshold value, then regulate the power supply noise peak value adjustment module in this region;
Regulating step two, when any power supply noise peak value adjustment module receives the adjustment information that self-adaptive control module sends, then described power supply noise peak value adjustment module regulates latency sensitive path, regulates path to be Delay reconstruction path;
Regulating step three, in adjustment process, when power supply noise be reduced to do not exceed threshold value time, stop regulating the latency sensitive path in this region.
In the present invention, system clock CLK
systemfor square-wave signal, as shown in Figure 1A.At system clock CLK
systeminside include multiple sampling period T
cycle.
In the present invention, when integrated circuit (IC) chip is run, if the path delay time in electric power network during noiseless is designated as
(and
); When integrated circuit (IC) chip is run, if path delay time when there is noise in electric power network is designated as
(and
).After regulating latency sensitive path, if the path delay time in electric power network during noiseless is designated as
(and
); After regulating latency sensitive path, if path delay time when there is noise in electric power network is designated as
(and
).The cycle of controllability path clock is sampling period T in the present invention
cycle.
When
time, then needing the latency sensitive path to there is noise to regulate, making
When
time, without the need to regulating the latency sensitive path that there is noise.
embodiment 1
The test that the power supply noise peak value measurement module that application the present invention designs is carried out:
Adopt HSPICE software (version 2 008 and more than) to test, this test uses Nangate45nm to increase income storehouse, and to electric power network plus noise, reference voltage is 1.20V, and noise peak is 1.17V, and the noise effect time is 1ns.First digital signature question blank is generated.Afterwards power supply plus noise is tested, simulation result is as shown in Fig. 3 D and Fig. 3 E (Fig. 3 E is the colour display of Fig. 3 D), make a response fast when noise carrys out interim measurement module, along with the decline of electric power network voltage, 4th phase inverter, 5th phase inverter and hex inverter overturn in succession, make the 4th group of trigger, the output of the one-level trigger element of the 5th group of trigger and the 6th group of trigger becomes noble potential from electronegative potential, the one-level trigger element of the trigger of all the other groups exports constant, the output of two-stage triggering unit to one-level trigger element of all trigger groups is simultaneously sampled, 4th group of trigger, the two-stage triggering unit of the 5th group of trigger and the 6th group of trigger exports and becomes noble potential from electronegative potential, the two-stage triggering unit of the trigger of all the other groups exports all constant, thus produce corresponding digital signature, can inquire about according to digital signature question blank and learn that the peak value of power supply noise in this measurement window is 1.17V, prove that the power supply noise peak value measurement module of the present invention's design can effectively measure power supply noise peak value.
Real-time digital signature form:
In Fig. 3 D and Fig. 3 E, colored Fig. 3 E is adopted to carry out comparative illustration in order to clearly phenogram 3D.In figure, data1 represents the waveform that the primary unit of the 4th group of trigger exports.Data2 represents the waveform that the primary unit of the 5th group of trigger exports.Data3 represents the waveform that the primary unit of the 6th group of trigger exports.Data4 represents system clock.Data5 represents power supply noise.Data6 represents the waveform that the secondary unit of the 4th group of trigger exports.Data7 represents the waveform that the secondary unit of the 5th group of trigger exports.Data8 represents the waveform that the secondary unit of the 6th group of trigger exports.The waveform that the secondary unit of the 4th group of trigger exports overlaps with the waveform that the secondary unit of five groups of triggers exports.Known from Fig. 3 D and Fig. 3 E, when there is power supply noise, phase inverter overturns, and make the output of corresponding trigger group become noble potential from electronegative potential, and be swift in response, the reaction time can reach 0.1ns.
By the emulation testing of application HSPICE software, when power supply noise peak value measurement module is measured, its average power is 1.0646 × 10
-11w.
By applying the emulation testing of DesignCompiler (version number is DesignCompiler2008) software, power supply noise peak value measurement system is inserted in ITC ' 99B19 benchmark integrated circuit, and measure the number percent that power supply noise peak value measurement system accounts for the B19 integrated circuit total area.When inserting 1 power supply noise peak value measurement module in B19 integrated circuit, the area of power supply noise peak value measurement system accounts for 0.624% of B19 integrated circuit area.When inserting 2 power supply noise peak value measurement modules, the area of power supply noise peak value measurement system accounts for 1.106% of B19 integrated circuit area.When inserting 4 power supply noise peak value measurement modules, the area of power supply noise peak value measurement system accounts for 2.071% of B19 integrated circuit area.
embodiment 2
The test that the power supply noise peak value adjustment module that application the present invention designs is carried out:
Adopt HSPICE software (version 2 008 and more than) to test, the supply voltage of this test not Noise is 1.20V, because noise causes supply voltage to drop to 1.08V.
When in power supply not Noise time, the output in the latency sensitive path tested is as shown in Fig. 4 A black line segment; When containing noise in power supply, apply identical input to the input end in this path, if do not take regulation measure of the present invention, it exports as shown in Figure 4 B, and obviously its output there occurs mistake; Use the present invention to regulate to this path, it exports as shown in Figure 4 C.
Contrast through Fig. 4 C and Fig. 4 A, the two low and high level logic is identical in the identical sampling time, and the incomplete same reason of output waveform to be in power supply containing noise, makes output waveform out-of-flatness and high level amplitude is inconsistent.
Can prove that the present invention can effectively regulate latency sensitive path by this embodiment, offset power supply noise to the impact in latency sensitive path, prevent the output error of latency sensitive path.And then weaken power supply noise to the impact of integrated circuit (IC) chip, ensure that chip normally runs.
A kind of on-chip power supply noise peak measuring system and measuring method being applicable to integrated circuit (IC) chip of the present invention's design, to be solved is under the condition not affecting integrated circuit normal function, on sheet, how to measure the technical matters of the power supply noise size in some region in integrated circuit (IC) chip, this system by adding innovative noise monitoring of structures in existing integrated circuit (IC) chip, in real time power supply noise peak value is measured, realize monitoring in real time the power supply noise of regional, if power supply noise peak value exceedes threshold value, then send conditioning signal or alerting signal by adaptation module.
Claims (8)
1. be applicable to an on-chip power supply noise peak measuring system for integrated circuit (IC) chip, described integrated circuit (IC) chip has N number of region according to the different demarcation of function;
Electric power network in described integrated circuit (IC) chip is described N number of block supply;
It is characterized in that:
Power supply noise peak value measurement system forms by self-adaptive control module (3) with N number of power supply noise peak value measurement module of the N number of Region Matching in described integrated circuit (IC) chip;
The power supply noise peak value measurement module arranged for a-quadrant is designated as first power supply noise peak value measurement module (2A);
The power supply noise peak value measurement module arranged for B region is designated as second power supply noise peak measurement module (2B);
The power supply noise peak value measurement module arranged for n-quadrant is designated as N number of power supply noise peak value measurement module (2N);
Described power supply noise peak value measurement module (2A, 2B ... and 2N) structure be identical; That is:
Power supply noise peak value measurement module is made up of resistance adjustment module (20D), permanent resistance module (20E), divider resistance array (20A), phase inverter array (20B) and flip-flop array (20C);
Self-adaptive control module (3) first aspect receives the real-time digital signature Name that power supply noise peak value measurement module exports
in real time; Second aspect to each power supply noise peak value measurement module (2A, 2B ..., 2N) send measuring control signal W
n, described measuring control signal W
nin include work enabling signal EN
work, dividing potential drop control signal FV
3with inverter controlling signal NV
3, i.e. W
n={ EN
work, FV
3, NV
3; Described EN
workfor arranging the working time node gathered under several sampling period;
Resistance adjustment module (20D), is used for containing noisy power supply signal by what receive on the one hand
carry out dividing potential drop; Environment temperature T is offset on the other hand by the resistance of each resistance in regulating resistance adjustment module (20D)
environmentto power supply noise peak value measurement module (2A, 2B ..., 2N) impact;
Permanent resistance module (20E) cooperates with resistance adjustment module (20D), and the voltage realized between the adjacent resistor in divider resistance array (20A) is in the threshold voltage V of connected phase inverter in phase inverter array (20B)
threshold valuenear;
Divider resistance array (20A) is made up of multiple resistance in series;
Phase inverter array (20B) is connected between the adjacent resistor in divider resistance array (20A);
Flip-flop array (20C) is connected on the output terminal of phase inverter.
2. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, it is characterized in that: the structure that resistance adjustment module (20D) adopts NMOS tube and resistance to combine, namely the G end of NMOS tube connects branch pressure voltage signal, the D end of NMOS tube is connected with one end of resistance, and the S end of NMOS tube is connected on divider resistance array (20A).
3. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, is characterized in that: the divider resistance array (20A) in power supply noise peak value measurement system, phase inverter array (20B) and flip-flop array (20C) to arrange number relevant to the data operation figure place of integrated circuit (IC) chip.
4. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, is characterized in that: in phase inverter array (20B), according to voltage difference
if Δ V > 0, then phase inverter output low level
when adopting binary expression,
assignment is 0; If Δ V≤0, then phase inverter exports high level
when adopting binary expression,
assignment is 1; Described V
threshold valuerefer to that the input voltage of phase inverter equals the voltage of output voltage.
5. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, is characterized in that: the previous trigger of each group trigger is called one-level trigger element, and a rear trigger is called two-stage triggering unit; The reset terminal of trigger group links together, all first once reset before starting measurement at every turn, make the output of trigger be low level, the prime input end of clock of the one-level trigger element of trigger is connected with the output terminal of phase inverter, and data input pin connects supply voltage (VDD); The data input pin of two-stage triggering unit of trigger is connected with the output terminal of the one-level of trigger, the rear class input end of clock of the two-stage triggering unit of trigger is connected with one and gate cell, is connected with the system clock CLK of integrated circuit (IC) chip and the log-on message EN that works respectively with 1 end of gate cell and 2 ends.
6. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, is characterized in that: in flip-flop array 20C, working signal EN
workwith system clock CLK
systemthrough with gate cell after be applied on the rear class input end of clock of the two-stage triggering unit of trigger; Work as EN
workduring for high level, system clock CLK
systemby with gate cell, now the two-stage triggering unit starting of trigger; Work as EN
workduring for low level, system clock CLK
systemnot by with gate cell, now the two-stage triggering unit of trigger does not start.
7. the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip according to claim 1, is characterized in that: can be applied to digital integrated circuit and DA combination integrated circuit.
8. application rights requires to it is characterized in that the crest voltage measuring method that the on-chip power supply noise peak measuring system being applicable to integrated circuit (IC) chip described in 1 is carried out including the following step:
Measuring process one, in designing integrated circuit chip processes, carries out Region dividing by DesignCompiler software to integrated circuit (IC) chip, and marks each region;
Measuring process two, inserts self-adaptive control module on an integrated circuit die, and insert in each area power supply noise peak value measurement module (2A, 2B ..., 2N) be connected to electric power network corresponding to this region;
Measuring process three, in testing integrated circuit chip process, probe is adopted to obtain the magnitude of voltage in each region in integrated circuit (IC) chip, and supply voltage, because of for electrical noise, the digital signature between the supply voltage 1.0V being reduced to weakening from standard supply voltage 1.2V;
Then magnitude of voltage and digital signature are built digital signature question blank; Described digital signature question blank is two row multirow tableau formats; One is classified as supply voltage settings, and another is classified as digital signature identification number;
Finally digital signature question blank is stored in self-adaptive control module (3), and described self-adaptive control module (3) is set carries out the threshold information regulated and the threshold information given the alarm;
Measuring process four, in operation integrated circuit (IC) chip process, when chip is subject to power supply noise interference, self-adaptive control module (3) and power supply noise peak value measurement module (2A, 2B ..., 2N) co-ordination under, the detection to live electrical power noise peak on chip can be completed, and send adjustment or alerting signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510496187.3A CN105044623B (en) | 2015-08-13 | 2015-08-13 | A kind of on-chip power supply noise peak measuring system and its measuring method suitable for IC chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510496187.3A CN105044623B (en) | 2015-08-13 | 2015-08-13 | A kind of on-chip power supply noise peak measuring system and its measuring method suitable for IC chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105044623A true CN105044623A (en) | 2015-11-11 |
| CN105044623B CN105044623B (en) | 2017-09-05 |
Family
ID=54451305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510496187.3A Active CN105044623B (en) | 2015-08-13 | 2015-08-13 | A kind of on-chip power supply noise peak measuring system and its measuring method suitable for IC chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105044623B (en) |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106055841A (en) * | 2016-06-30 | 2016-10-26 | 张升泽 | Noise preprocessing method and system of electronic chip |
| CN106055831A (en) * | 2016-06-20 | 2016-10-26 | 张升泽 | Signal drawing method and system for electronic chip |
| CN106056837A (en) * | 2016-06-27 | 2016-10-26 | 张升泽 | Noise alarm method and system of electronic chip |
| CN106096174A (en) * | 2016-06-22 | 2016-11-09 | 张升泽 | The noise method for drafting of electronic chip and system |
| CN106124877A (en) * | 2016-07-12 | 2016-11-16 | 张升泽 | The noise information sending method of electronic chip and system |
| CN106202773A (en) * | 2016-07-19 | 2016-12-07 | 张升泽 | The noise modulated method and system of electronic chip |
| CN106597249A (en) * | 2016-10-10 | 2017-04-26 | 中国电子科技集团公司第五十五研究所 | On-chip test system and method of W-waveband low-noise power amplification chip |
| CN106658302A (en) * | 2016-11-02 | 2017-05-10 | 北京中星微电子有限公司 | Method of suppressing Pop noise in chip audio processing |
| WO2017219194A1 (en) * | 2016-06-20 | 2017-12-28 | 张升泽 | Electronic chip signal drawing method and system |
| WO2017219277A1 (en) * | 2016-06-22 | 2017-12-28 | 张升泽 | Method and system for drawing noise of electronic chip |
| WO2018000124A1 (en) * | 2016-06-27 | 2018-01-04 | 张升泽 | Method and system for noise alarm for electronic chip |
| WO2018010087A1 (en) * | 2016-07-12 | 2018-01-18 | 张升泽 | Electronic chip noise information sending method and system |
| WO2018010154A1 (en) * | 2016-07-15 | 2018-01-18 | 张升泽 | Electronic chip voltage modulation method and system |
| WO2018014183A1 (en) * | 2016-07-19 | 2018-01-25 | 张升泽 | Noise modulation method and system for electronic chip |
| WO2018014184A1 (en) * | 2016-07-19 | 2018-01-25 | 张升泽 | Power modulation method and system for electronic chip |
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
| CN109581184A (en) * | 2018-11-13 | 2019-04-05 | 北京航空航天大学 | A kind of screening technique and on piece measuring system for aging of integrated circuit reliability |
| CN109716709A (en) * | 2016-09-27 | 2019-05-03 | 住友电气工业株式会社 | Switching device and determining method |
| CN112379185A (en) * | 2020-11-06 | 2021-02-19 | 海光信息技术股份有限公司 | Power noise test structure of bare chip |
| CN113125941A (en) * | 2021-04-19 | 2021-07-16 | 海光信息技术股份有限公司 | Detection method, detection system and detection device for chip design |
| TWI789239B (en) * | 2022-02-14 | 2023-01-01 | 瑞昱半導體股份有限公司 | Voltage monitoring system and voltage monitoring device of automatically adjusting scaling degree of input signal and related method of voltage monitoring |
| CN116897291A (en) * | 2021-06-08 | 2023-10-17 | 科磊股份有限公司 | System and method for Z-PAT defect guidance statistical outlier detection for semiconductor reliability failure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514491A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Layered power source noise monitoring device of ultra large scale integrated circuit and system |
| CN1523662A (en) * | 2003-09-12 | 2004-08-25 | 清华大学 | Quick method for implementing noise optimization of integrated circuit supply network using decoupling capacitor |
| WO2005020324A1 (en) * | 2003-08-22 | 2005-03-03 | The New Industry Reserch Organization | Circuit for detecting and measuring noise in semiconductor integrated circuit |
| JP2005196406A (en) * | 2004-01-06 | 2005-07-21 | Matsushita Electric Ind Co Ltd | Method for designing semiconductor integrated circuit with reduced power source noise |
| KR20100089521A (en) * | 2009-02-04 | 2010-08-12 | 엘에스산전 주식회사 | Noise mesurement system in power stabilazation network, varialbe filter applied in the same, and method for mesuring noise in power stabilazation network |
-
2015
- 2015-08-13 CN CN201510496187.3A patent/CN105044623B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514491A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Layered power source noise monitoring device of ultra large scale integrated circuit and system |
| WO2005020324A1 (en) * | 2003-08-22 | 2005-03-03 | The New Industry Reserch Organization | Circuit for detecting and measuring noise in semiconductor integrated circuit |
| CN1523662A (en) * | 2003-09-12 | 2004-08-25 | 清华大学 | Quick method for implementing noise optimization of integrated circuit supply network using decoupling capacitor |
| JP2005196406A (en) * | 2004-01-06 | 2005-07-21 | Matsushita Electric Ind Co Ltd | Method for designing semiconductor integrated circuit with reduced power source noise |
| KR20100089521A (en) * | 2009-02-04 | 2010-08-12 | 엘에스산전 주식회사 | Noise mesurement system in power stabilazation network, varialbe filter applied in the same, and method for mesuring noise in power stabilazation network |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106055831A (en) * | 2016-06-20 | 2016-10-26 | 张升泽 | Signal drawing method and system for electronic chip |
| WO2017219194A1 (en) * | 2016-06-20 | 2017-12-28 | 张升泽 | Electronic chip signal drawing method and system |
| CN106096174A (en) * | 2016-06-22 | 2016-11-09 | 张升泽 | The noise method for drafting of electronic chip and system |
| WO2017219277A1 (en) * | 2016-06-22 | 2017-12-28 | 张升泽 | Method and system for drawing noise of electronic chip |
| CN106056837A (en) * | 2016-06-27 | 2016-10-26 | 张升泽 | Noise alarm method and system of electronic chip |
| WO2018000124A1 (en) * | 2016-06-27 | 2018-01-04 | 张升泽 | Method and system for noise alarm for electronic chip |
| CN106055841A (en) * | 2016-06-30 | 2016-10-26 | 张升泽 | Noise preprocessing method and system of electronic chip |
| CN106124877A (en) * | 2016-07-12 | 2016-11-16 | 张升泽 | The noise information sending method of electronic chip and system |
| WO2018010087A1 (en) * | 2016-07-12 | 2018-01-18 | 张升泽 | Electronic chip noise information sending method and system |
| WO2018010154A1 (en) * | 2016-07-15 | 2018-01-18 | 张升泽 | Electronic chip voltage modulation method and system |
| CN106202773A (en) * | 2016-07-19 | 2016-12-07 | 张升泽 | The noise modulated method and system of electronic chip |
| WO2018014183A1 (en) * | 2016-07-19 | 2018-01-25 | 张升泽 | Noise modulation method and system for electronic chip |
| WO2018014184A1 (en) * | 2016-07-19 | 2018-01-25 | 张升泽 | Power modulation method and system for electronic chip |
| CN109716709A (en) * | 2016-09-27 | 2019-05-03 | 住友电气工业株式会社 | Switching device and determining method |
| CN109716709B (en) * | 2016-09-27 | 2022-01-11 | 住友电气工业株式会社 | Switching device and determination method |
| CN106597249A (en) * | 2016-10-10 | 2017-04-26 | 中国电子科技集团公司第五十五研究所 | On-chip test system and method of W-waveband low-noise power amplification chip |
| CN106658302A (en) * | 2016-11-02 | 2017-05-10 | 北京中星微电子有限公司 | Method of suppressing Pop noise in chip audio processing |
| CN106658302B (en) * | 2016-11-02 | 2020-01-03 | 北京中星微电子有限公司 | Method for suppressing Pop noise in chip audio processing |
| CN108761310B (en) * | 2018-05-25 | 2021-03-12 | 合肥本源量子计算科技有限责任公司 | Quantum chip test method |
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
| CN109581184A (en) * | 2018-11-13 | 2019-04-05 | 北京航空航天大学 | A kind of screening technique and on piece measuring system for aging of integrated circuit reliability |
| CN109581184B (en) * | 2018-11-13 | 2020-08-25 | 北京航空航天大学 | Screening method for aging reliability of integrated circuit and on-chip measurement system |
| CN112379185A (en) * | 2020-11-06 | 2021-02-19 | 海光信息技术股份有限公司 | Power noise test structure of bare chip |
| CN112379185B (en) * | 2020-11-06 | 2023-03-21 | 海光信息技术股份有限公司 | Bare chip power supply noise test structure |
| CN113125941A (en) * | 2021-04-19 | 2021-07-16 | 海光信息技术股份有限公司 | Detection method, detection system and detection device for chip design |
| CN113125941B (en) * | 2021-04-19 | 2022-09-09 | 海光信息技术股份有限公司 | Detection method, detection system and detection device for chip design |
| CN116897291A (en) * | 2021-06-08 | 2023-10-17 | 科磊股份有限公司 | System and method for Z-PAT defect guidance statistical outlier detection for semiconductor reliability failure |
| CN116897291B (en) * | 2021-06-08 | 2024-05-24 | 科磊股份有限公司 | System and method for Z-PAT defect guidance statistical outlier detection for semiconductor reliability failure |
| TWI789239B (en) * | 2022-02-14 | 2023-01-01 | 瑞昱半導體股份有限公司 | Voltage monitoring system and voltage monitoring device of automatically adjusting scaling degree of input signal and related method of voltage monitoring |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105044623B (en) | 2017-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105044623A (en) | On-chip power source noise peak value measurement system suitable for integrated circuit chip and measurement method of measurement system | |
| CN105095592A (en) | Independent adjustment system of on-chip power noise of novel integrated circuit chip and adjustment method thereof | |
| CN105445569B (en) | Nanosecond power supply noise transient waveform measuring system and its measuring method on a kind of piece suitable for high speed integrated circuit | |
| CN100401461C (en) | Semiconductor circuit device simulation method and semiconductor circuit device simulator | |
| CN101485088B (en) | Very low power analog compensation circuit | |
| CN104425411B (en) | The operating method of semiconductor devices and semiconductor devices | |
| CN104579263B (en) | A kind of reset circuit of high response speed, low-temperature coefficient | |
| CN105445648A (en) | Testing trimming circuit and integrated circuit | |
| US20090206821A1 (en) | Process variation on-chip sensor | |
| CN102017008B (en) | Localized calibration of programmable digital logic cells | |
| JP7116375B2 (en) | Systems and methods for increasing resolution of on-chip timing uncertainty measurements | |
| CN101196754B (en) | Automatic self-adapting system and method for forming the same | |
| CN102436529B (en) | Modeling method for metal oxide semiconductor (MOS) transistor reliability statistics models distributed based on Weibull | |
| CN104967095A (en) | Over-temperature protection circuit | |
| US20100037191A1 (en) | Method of generating reliability verification library for electromigration | |
| CN103294100A (en) | Reference current source circuit compensating resistor temperature drift coefficient | |
| CN107526883B (en) | The evaluation method of the total channel width of MOS transistor in cmos digital logic circuit | |
| US7779376B2 (en) | Operation analysis method of semiconductor integrated circuit | |
| US7679394B2 (en) | Power supply noise resistance testing circuit and power supply noise resistance testing method | |
| CN108107343B (en) | Aging sensor based on real SH time | |
| CN109974877A (en) | A kind of temperature sensor and chip | |
| CN106960802A (en) | The test device and method of testing of a kind of semiconductor static electric current | |
| CN106374886B (en) | Non-repeatable triggering CMOS integrated monostable circuit | |
| CN105988038B (en) | The measuring device and method of chip pressure drop | |
| CN100431038C (en) | Control time pulse generator and control time pulse generation method for high-speed sensing amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |