CN1523662A - Quick method for implementing noise optimization of integrated circuit supply network using decoupling capacitor - Google Patents

Abstract

A method for noise optimization to IC supply network with decoupling capacitance characterizes in that it utilizes a computer to model the optimization of a supply network against ASIC diagram location structure feature and the supply network based on a standard diagram and applies a nonlinear program method In this invention, area of the decoupling capacitance is the target of optimization to minimize its area to reserve enough blank space for latter stage of work such as buffer plug. Equivalent circuit method is used in the resolving process to reduce the resolving scale greatly to increase speed and save memory.

Description

Realize the fast method that integrated circuit electricity supply network noise is optimized with decoupling capacitance

Technical field

With decoupling capacitance the method that integrated circuit electricity supply network carries out noise optimization is belonged to VLSI physical Design field, especially the technology category of RLC power line/earth cord network noise optimization in the placement-and-routing field.

Background technology

The wiring stage in the integrated circuit physical Design can be divided into two parts: distinct line screen cloth line and holding wire screen cloth line.The power/grounding line network design just is included in distinct line screen cloth line part.Along with the raising of very lagre scale integrated circuit (VLSIC) integrated level and operating frequency, the design and optimization problem of its power/grounding line network becomes more and more important, and it directly influences the performance of entire circuit.Because the live width of power/grounding line network is more much bigger than holding wire, and can change, and has taken a lot of chip areas, therefore, it has been endowed the highest priority in the wiring stage.

Along with the continuous progress of technology, the characteristic line breadth of very lagre scale integrated circuit (VLSIC) is constantly dwindling, and the density of chip is also corresponding with operating frequency simultaneously is greatly improved.Thereby the powerup issue that makes chip becomes a major issue in VLSI deep-submicron (DSM) and sub-micro (VDSM) integrated circuit (IC) design.Unsuitable power/grounding line network design can produce excessive voltage drop and voltage fluctuation, greatly influences the performance of circuit, even makes circuit malfunction, and chip can't operate as normal.Therefore, supply network is analyzed and done on this basis suitable optimization accurately and just become very necessary.

Causing that the reason of voltage fluctuation in the supply network is wired goes up the Ldi/dt voltage drop that inductance causes on IR voltage drop that resistance causes and the line.Parasitic capacitance in supply network and the circuit elements device also can exert an influence to the voltage of each node in the network.The influence of the resistance in the supply network has mainly been considered in traditional power/grounding line network analysis, just supply network is modeled as resistor network and it is carried out dc analysis.Yet along with the continuous increase of electric current in operating frequency and the circuit, the electric capacity in the supply network and the influence of inductance are remarkable day by day.Therefore, we need set up more accurate RLC model to supply network, and it is carried out transient analysis, with voltage fluctuation information more accurately on each node in the acquisition circuit.

Along with the density of chip and increasing substantially of operating frequency, the noise threshold of supply network significantly reduces.Noise on the supply network can reduce the driving force of device, even makes circuit malfunction, and chip can't operate as normal.Therefore, we must be optimized it on the basis of supply network transient analysis, the voltage noise of each node is limited within the range of permission, and the chip area resource that makes supply network take are the least possible.

Under standard cell cloth chart-pattern, general netted (MESH) structure that adopts of the topological structure of power/ground.In the topological structure of this MESH, power/ground can be divided into two kinds: prewiring and " bus is strengthened in power supply ".As shown in Figure 1.Wherein, prewiring comprises the peripheral power supply bus, voltage supplied welding block and power supply rail.The unit is placed on the cell row, by power supply rail they is powered.Because the scale of circuit is increasing, depend merely on power supply rail and can not satisfy power reguirements far away, therefore, the notion of power supply reinforcement bus is suggested to increase the reliability and the performance of power supply.

At first, we set up accurate RCL model to power/grounding line network.As shown in Figure 2.Consider the dead resistance in the network, the influence of electric capacity and inductance, and with each circuit module receive electric current to regard as the time current source that becomes and its piecewise linearity represented (as Fig. 3 and Fig. 4).Secondly, we are divided into several time steps with each clock cycle, put in each regular time network is found the solution, with the variation waveform of voltage in the clock cycle that obtains each node.Said process is exactly the process of power/grounding line network being carried out transient analysis.At ASIC circuit based on the standard cell design, consider the regularity characteristics of its electric power network, in our work formerly structure and design realized accurately, efficiently based on the ic power network transients analysis and solution device of equivalent electric circuit, under the prerequisite of not losing accuracy and save memory, increased substantially the speed of analysis and solution, enlarged the chip-scale of analysis and solution,, obtained best up to now result for handling large-scale chip.

On the basis of transient analysis solver, we have realized one by adding the fast algorithm that decoupling capacitance is optimized supply network among the present invention.In order to reach the purpose that supply network is optimized, present most widely used optimization method has three kinds.They are the optimization (topology optimization) of network topology structure, live width optimization (wire sizing) and placement decoupling capacitance (decoupling capacitance deployment).The present invention is conceived to add the effective ways of voltage fluctuation in this reduction supply network of decoupling capacitance on supply network.Decoupling capacitance is equivalent to local interim voltage source in supply network, receiving electric current to increase suddenly or when reducing, can play sustaining voltage and act on stably at device.Because decoupling capacitance has taken a large amount of chip areas, therefore also need the area of decoupling capacitance is optimized.

About adding decoupling capacitance supply network is optimized, forefathers have done some research work.Have and mention the iterative process that the power/grounding line network optimization of adding decoupling capacitor is a breadboardin and adjustment layout in the document.Need take area of chip owing on chip, add decoupling capacitance, need under many circumstances existing cell layout is adjusted, for decoupling capacitor is vacateed enough placement spaces.Like this, optimizing process just becomes the iterative process analyzing supply network and adjust chip layout.Used the method for circuit sensitivity analysis to determine the placement location and the size of decoupling capacitance in the work that has, reduced voltage drop in the supply network with this.The circuit sensitivity analysis can be carried out in frequency domain or time domain respectively.Meter sensitivity has respectively been avoided on each time point in the sensitivity analysis of frequency domain, therefore can significantly reduce operand, but time domain has the loss of precision in the conversion of frequency domain and the inverse conversion process, so there is bigger error in the result of frequency-domain analysis.

Based on the characteristics of different cloth chart-patterns, forefathers have also done a lot of work.There is document to mention, under BBL cloth chart-pattern, adopts the method for linear programming to determine the placement location of decoupling capacitance, and in fixed layout, insert blank module with heuristic and come to obtain the space for adding decoupling capacitor.Also there is document that the supply network optimization method that adds decoupling capacitance is applied to ASIC Design under the standard cell cloth chart-pattern.Use the method for adjoint network to find the solution sensitivity in the literary composition, and used the method for quadratic programming that problem is carried out iterative.

Some problems of ubiquity in the work that this area forefathers have done cause the time of algorithm and space complexity all higher, and it is unsatisfactory to optimize effect, therefore, can not be applied to the power/grounding line network optimization work of industrial quarters reality.In order to address these problems, the present invention has following characteristics:

Make full use of the structural characteristics of power/grounding line network, use the method for equivalent electric circuit, when the process of solution node voltage equation, reduced the scale of finding the solution, thereby reduced running time and memory consumption, time and space complexity are significantly descended, optimize quality simultaneously and also can improve.

Penalty function method (Penalty Method), equivalent electric circuit (Equivalent Circuit), conjugate gradient method (Conjugate GradientMethod) and expansion Teller root adjoint network (Tellegen Adjoint Network) are four chief components of the present invention.These four methods combine, and form system's acting in conjunction on the area-optimized problem of power/ground, have obtained good optimization effect.

Because more than, the present invention has the ability of optimizing large-scale circuit and can well be optimized effect.We have adopted the side circuit of industrial quarters as test case.It can be optimized having the big circuit that surpasses 1,000,000 nodes in 7.38 hours time.And the area of the placement decoupling capacitance that obtains after the optimization is more much smaller than the area that heuristic obtains.

Summary of the invention

The present invention has designed a kind of network optimization of ic power efficiently algorithm, and the white space that utilization is present among the standard cell placement adds decoupling capacitance on the additional sheet, plays the purpose that supply network is optimized.Nonlinear programming approach is searched for optimal solution in solution space; The method of equivalent electric circuit greatly reduces the scale that circuit is found the solution by merging a large amount of intermediate nodes that exist in the supply network, and the speed of finding the solution and optimizing is significantly improved; The application of expansion Teller root adjaiont network method makes that in each step of iteration a demand separates primitive network and expansion Teller root network respectively once just can obtain the gradient of penalty function about electric derived vector, has saved a large amount of running times; Conjugate gradient method only needs memory source seldom in the middle of numerous unconstrained optimization methods, and its convergence rate is than comparatively fast.The optimized Algorithm that the present invention is based on these four kinds of methods realizations has obtained good optimization effect.

Do following explanation about the adjoint network of setting up former network.We need set up a series of adjoint networks of violating obligatory point corresponding to all to former network in the algorithmic procedure.For example, i is a node of violating the voltage drop constraint, sets up the adjoint network corresponding to the i node, and promptly the current source of other nodes is opened a way, and E is got in the current source excitation of i node _i(t) (E _i(t) definition is referring to the 7th page in specification).Find the solution this adjoint network and obtain the magnitude of voltage of each node, thus can be in the hope of the magnitude of voltage of i node Grad with respect to all decoupling capacitances.Other violates obligatory point such as p, and q node etc. in like manner.These Grad are applied to ask the Grad of target function with respect to each decoupling capacitance again.So just need find the solution a plurality of adjoint networks.We do some conversion by the current source excitation to each node, make that finding the solution an adjoint network just can obtain the Grad of target function with respect to all decoupling capacitors.Can be with reference to following document about the adjoint network method: (1) L.O.Chua and P.M.Lin, Computer-Aided Analysis ofElectronic Circuits, Englewood Clifss:Prentice-Hall, Inc.1975. (2) appoint blunt, Gan Shuzhen, " computer-assisted analysis of circuit and design ", publishing house of Beijing Institute of Technology, 1989.

1. realize the fast method that integrated circuit electricity supply network noise is optimized with decoupling capacitance, contain useful placement decoupling capacitance step with raising supply network reliability in the blank area of Butut, it is characterized in that, it is that a kind of computer that utilizes is at based on the layouts characteristics of the application-specific integrated circuit (ASIC) (ASIC) of standard cell cloth chart-pattern and the design feature of supply network thereof, will in order to keep node voltage stably the area of decoupling capacitance as the target of optimizing, the method that the method for employing Non-Linear Programming is effectively found the solution the electricity supply network noise optimization problem, it is penalty function method, equivalent electric circuit, the method of conjugate gradient method and expansion Teller root adjoint network forms a whole acting in conjunction on power/grounding line network is optimized, and obtains good optimization effect; Particularly, it contains following steps successively:

(1) computer reads in the file that comprises supply network information and cell layout's information: supply network information comprises the relational structure between the supply network node; The time dependent current waveform (utilizing PWL to represent) that receives of the unit module that intrinsic decoupling capacitance value (capacitance characteristic that shows when unit module is static), electric capacity initial voltage and current value and each node are connected on resistance value between the node, inductance value, inductance initial voltage and current value, the sheet, in computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node); Cell layout's information comprises the relative position relation between number of unit, unit coordinate and the unit in each cell row, according to these information, we can obtain the long-pending distribution situation of blank face on the information of the blank area between the unit and each cell row, and additional decoupling capacitance just is added on these white spaces;

(2) parameter information that utilizes input carries out transient analysis based on equivalent electric circuit to supply network, obtains the voltage waveform of each node;

(3) if the voltage of each node is not violated the situation of constraint to be occurred, then do not need supply network is done optimization;

Otherwise execution following steps:

(4) with the voltage waveform piecewise linearity record of each node, be used for the calculating of optimizing process gradient;

(5) determine that the target function of optimizing is the area of the decoupling capacitor of interpolation, under the constraints of correspondence, minimize:

$\min A=\underset{j\∈M}{\mathrm{\Σ}}(w_j\×H)------\left(1\right),$

M is the node set that allows to add decoupling capacitance, M={1 ..., m), M N; N is the set of all nodes in the supply network, N={1 ..., n}; H is the height of standard cell, w _jBe the decoupling capacitor c that is added on the node j _jWidth;

Constraints is as follows:

(5.1) voltage drop constraint:

Be of the voltage drop of each node,, promptly be lower than the integrated value S of the voltage segment of voltage threshold on each node with the value that can effectively weigh the voltage drop noise with respect to supply voltage _iExpression:

$s_i={\∫}_0^T\max (V_{\min }-v_i\left(t\right),0)\mathrm{dt}={\∫}_{t_1}^{t_2}(V_{\min }-v_i\left(t\right))\mathrm{dt}------\left(2\right),$

[t ₁, t ₂] violate the time interval of voltage drop constraint, V for the i node _MinBe voltage threshold, v _i(t) be the magnitude of voltage of i node;

(5.2) electromigration constraint:

With [t ' ₁, t ' ₂] in the time, supply network branch (p, when q) maximum current density that allows of the absolute value of two ends node voltage difference and technology is σ at branch length l _QpOn the integrated value of difference of voltage drop represent:

$u_{p,q}={\∫}_0^T\max [\left(\right|v_p\left(t\right)-v_q\left(t\right)|-{\mathrm{\ρl}}_{p,q}\mathrm{\σ}),0]\mathrm{dt}={\∫}_{{t^{\′}}_1}^{{t^{\′}}_2}\left(\right|v_p\left(t\right)-v_q\left(t\right)|-{\mathrm{\ρl}}_{p,q}\mathrm{\σ})\mathrm{dt}------\left(3\right),$

Wherein, v _pAnd v _qBe respectively power supply branch (P, the q) voltage of two end nodes, v _p-v _qI.e. voltage difference on this branch; ρ is a square resistance; l _PqBe branch (p, length q);

(5.3) decoupling capacitor is area-constrained:

Be in every cell row, the decoupling capacitor area of interpolation is smaller or equal to the blank area in this cell row, and the height H of cell row is a definite value, therefore can directly use width means area size:

${\mathrm{dw}}_r=\max (\underset{j\∈\mathrm{ND}\left(r\right)}{\mathrm{\Σ}}{w}_{r,y}-{\mathrm{rw}}_r,0),r\∈\mathrm{NR},-----\left(4\right),$

NR is the set of cell row; ND (r) be r capable in the location sets of decoupling capacitor; w _{R, y}Be meant the width of the decoupling capacitor that is positioned at the capable y of r position; Rw _rIt is the overall width of the blank area of r on capable; Dw _rBe that r violates the area-constrained punishment amount of decoupling capacitor on capable, will in the penalty function method of back, use;

(5.4) decoupling capacitor Breadth Maximum constraint:

The width of any one decoupling capacitor that adds in certain cell row is less than or equal to the long-pending width of maximum empty fine flour in the one's own profession;

ew _r，y＝max(w _r，y-rw _r，0)，r∈NR，y∈ND(r)，——(5)，

Ew _{R, y}Be the punishment amount of violating the constraint of decoupling capacitor Breadth Maximum on capable y the position of r, will in the penalty function method of back, use;

(6) structure penalty function f is converted into unconstrained optimization problem with the nonlinear constrained optimization problem:

$\min f=A+p_t$

$=A+\mathrm{\&alpha;}\&CenterDot;(\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i^2+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{<figure-callout\; id="2"\; label="pq"\; filenames="A0315705200171.png"\; state="\{\{state\}\}">pq</figure-callout>}}^2+\underset{r\&Element;\mathrm{<figure-callout\; id="2"\; label="NR\; dw\; r"\; filenames="A0315705200171.png"\; state="\{\{state\}\}">NR</figure-callout>}}{\mathrm{\&Sigma;}}{\mathrm{dw}}_r^{}{}_2^{}+\underset{r\&Element;\mathrm{NR},y\&Element;\mathrm{ND}\left(r\right)}{\mathrm{\&Sigma;}}{\mathrm{ew}}_{r,y}^2),------\left(6\right),$

Wherein, A is the decoupling capacitor gross area, and B is the set of all branches in the electric power network, P _tBe that to penalize item, α be penalty factor;

(7) initial value of penalty factor α is set; Each locational decoupling capacitor initial value that can add decoupling capacitor all is made as the minimum capacity width of permission, obtains the initial solution of electric capacity width vector as following unconstrained optimization; Provide limits of error ε in addition ₁＞0:

(8) find the solution current unconstrained optimization problem, obtain current optimal solution electric capacity width vector W ^(l)

(8.1) initial solution of establishing current unconstrained optimization problem is electric capacity width vector W ⁽⁰⁾, error is limited to ε ₂＞0;

(8.2) the initial optimization direction is made as penalty function about electric capacity width vector W ⁽⁰⁾The negative gradient direction:

If the initial optimization direction is P ⁽⁰⁾, gradient direction is f (W ⁽⁰⁾),

Get P ⁽⁰⁾=- f (W ⁽⁰⁾)-(7),

(8.3) ask the gradient of penalty function with the adjaiont network method of expansion with respect to electric capacity width vector:

$\&dtri;f\left(W\right)={[\frac{\&PartialD;f}{{\&PartialD;w}_1},\frac{\&PartialD;f}{\&PartialD;w_2},\&CenterDot;\&CenterDot;\&CenterDot;,\frac{\&PartialD;f}{{\&PartialD;w}_j},\&CenterDot;\&CenterDot;\&CenterDot;,\frac{\&PartialD;f}{{\&PartialD;w}_m}]}^T,j\&Element;\mathrm{\&Nu;}------\left(8\right),$

Width is w _jElectric capacity c _jBe connected on the node j of supply network, suppose that node j is positioned at r _jThe y of row _jThe position, then penalty function f is with respect to w _jPartial derivative can be expressed as:

$\frac{\&PartialD;f}{\&PartialD;w_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+2\mathrm{\&alpha;}[\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{\&PartialD;s_i}{{\&PartialD;w}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{\&PartialD;w_j}],---\left(9\right),$

fj∈NR，yj∈ND(rj)

Relation according to capacitance size and width:

$c=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{T_{\mathrm{ox}}}\&times;w\&times;H------\left(10\right),$

ε _OxAnd T _OxBe respectively the dielectric constant and the thickness of an oxide layer;

$\frac{\&PartialD;f}{{\&PartialD;w}_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+\frac{{2\mathrm{\&alpha;\&epsiv;}}_{\mathrm{ox}}H}{T_{\mathrm{ox}}}[\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{\&PartialD;s_i}{\&PartialD;c_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{\&PartialD;c_j}]-----\left(11\right),$

rj∈nr，yj∈ND(rj)

By the primary circuit network being set up a series of adjoint networks of each node in the corresponding circuits, and after making circuit sensitivity and analyzing, obtain:

$\frac{\&PartialD;s_i}{\&PartialD;c_j}={\&Integral;}_0^T{v}_{j,E_i}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}-----\left(12\right),$

$\frac{\&PartialD;u_{\mathrm{pq}}}{\&PartialD;c_j}={\&Integral;}_0^T{v}_{j,t_{\mathrm{pq}}}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}-----\left(13\right),$

$={\&Integral;}_0^T[v_{j,E_p}^{\&prime;}\left(t\right)-v_{j,E_p}^{\&prime;}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}$

Wherein, ${\stackrel{.}{v}}_j(T-t)=\frac{{\mathrm{dv}}_j(T-t)}{\mathrm{dt}}$ Be the derivative of the voltage of j node in the primary circuit network to time t; V ' _{J, Ei}(t) be j node in the adjoint network of setting up corresponding to node i voltage (v ' _{J, Ep}(t), v ' _{J, Eq}(t) in like manner), it can be expressed as follows:

$v_{j,E_i}^{\&prime;}\left(t\right)=Z\left(j\right)v_{E_i}^{\&prime;}\left(t\right)=Z\left(j\right)G^{-1}[E_i\left(t\right)+{\mathrm{EC}}_i\left(t\right)+{\mathrm{EL}}_i\left(t\right)]-----\left(14\right),$

Wherein, Z (j) is a choice of location vector, and this vector is 1 except the locational element value of j, and other element all is 0, promptly Z (j)=[0,0 ..., 0,1,0 ..., 0];

G is the relational matrix among the nodal voltage equation group G*V=I;

E _i(t) be the current source vector, its value is except that the element value of node i correspondence, and remaining element value all is 0, and the element value of node i correspondence is-1 when this node is violated the voltage drop constraint, is 0 when this node is not violated constraint;

EG _i(t) and EL _i(t) be to do the current source vector that obtains after the equivalence corresponding to electric capacity and inductance element in the adjoint network of node i foundation;

So obtain:

$\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{\&PartialD;s_i}{\&PartialD;c_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{\&PartialD;u_{\mathrm{pq}}}{\&PartialD;c_j}$

$=\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\left(\right[{\&Integral;}_0^T{v}_{j,E_i}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt})+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\left({\&Integral;}_0^T\right[v_{j,E_i}^{\&prime;}\left(t\right)-v_{j,E_i}^{\&prime;}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt})----\left(15\right),$

${=\&Integral;}_0^T\{{\stackrel{.}{v}}_j(T-t)\&times;\{\underset{i\&Element;N}{\mathrm{\&Sigma;}}(s_i\&times;v_{j,E_i}^{\&prime;}\left(t\right))+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}\{u_{\mathrm{pq}}\&times;[v_{j,E_p}^{\&prime;}\left(t\right)-v_{j,E_p}^{\&prime;}\left(t\right)\left]\right\}\left\}\right\}\mathrm{dt}$

According to formula (14), (15) obtain:

$\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{\&PartialD;s_i}{{\&PartialD;c}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{\&PartialD;c_j}=Z\left(j\right)G^{-1}{I}_{\mathrm{total}}\left(t\right)------\left(16\right),$

I wherein _Total=I _New(t)+EC (t)+EL (t)---(17),

$I_{\mathrm{new}}\left(t\right)=\underset{i\&Element;N}{\mathrm{\&Sigma;}}[s_i\&times;E_i\left(t\right)]+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}\{u_{\mathrm{pq}}\&times;[E_p\left(t\right)-E_q\left(t\right)\left]\right\}----\left(18\right),$

Wherein, EC (t) and EL (t) are with I _NewDuring as the current excitation of adjoint network, electric capacity and inductance element are done the current source vector that obtains after the equivalence;

Thereby obtain:

$\frac{\&PartialD;f}{{\&PartialD;w}_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+\frac{{2\mathrm{\&alpha;\&epsiv;}}_{\mathrm{ox}}H}{T_{\mathrm{ox}}}{\&Integral;}_0^T\left\{\right[Z\left(j\right)\&times;G^{-1}\&times;I_{\mathrm{total}}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\}\mathrm{dt}----\left(19\right),$

rj∈NR，yj∈ND(rj)，j∈M

(8.4) establish iteration and proceeded to the k step, it is respectively to be w that current electric capacity width vector sum is optimized direction ^(k)And P ^(k), along P ^(k)Carry out linear search, find non-negative linear search factor lambda _k, make penalty function at P ^(k)Reach optimum on the direction, that is:

f(W ^(k)+λ _kP ^(k))＝minf(W ^(k)+λP ^(k)) ——(20)，

(8.5) upgrade electric capacity width vector W according to following formula ^(k+l):

W ^(k+1)＝W ^(k)+λ _kP ^(k) ——(21)，

(8.6) if ‖ f is (W ^(k+1)) ‖＜ε ₂, this unconstrained optimization finishes to withdraw from, and changes step 9;

Otherwise the dimension of establishing electric capacity width vector is m,

If k=m, then W ⁽⁰⁾=W ^(k+1), f (G ⁽⁰⁾)= f (G ^(k+1)), turn to step 8.2;

If k＜m upgrades the optimization direction according to following formula, get back to step 8.4 and continue to optimize;

(9) calculate the value of penalizing item according to optimizing the result, if p _t＜ε ₁, current electric capacity width vector promptly is the optimal solution of asking, algorithm finishes to withdraw from; Otherwise upgrade penalty factor α, establish l=l+1, get back to step 8 and continue to optimize;

(10) because the actual decoupling capacitor value that can add is not continuous, have the restriction of least unit numerical value, we adjust the optimization result who finally obtains; If the decoupling capacitor value that add certain position then merges to it on contiguous node less than minimum value, forming bigger electric capacity, and these electric capacity are adjusted into the multiple of least unit numerical value;

Wherein, the i node is represented the arbitrary node of violating the voltage drop constraint in the network.P, two end nodes of the branch of current density constraint are violated in the representative of q node.The j node is represented the arbitrary node that can add decoupling capacitance in the network.During the Grad of the decoupling capacitance size that we add on respect to the j node at calculating target function, because target function and s _iAnd t _PqRelevant, so need use i, p, the parameters such as voltage of q node during compute gradient.The position of j node and i, p, it doesn't matter in the position of q node.

Node in the whole supply network is numbered total n node.Decoupling capacitance c _jBe positioned at the j node location of supply network, j ∈ M.M is the node set that allows to add decoupling capacitance, M={1 ..., m}, M N; N is the set of all nodes in the supply network, N={1 ..., n}; The j node is arranged in the capable yj position of supply network rj again simultaneously, and wherein, yj is the capable interior node serial number of rj, and is different with j.

When describing the area-constrained condition of decoupling capacitor, represented that with the capable y of r position all have added the position of decoupling capacitance, be a kind of method for expressing, the position of not refering in particular to some decoupling capacitances.And the capable yj of rj position is the decoupling capacitor c that is added on the node j _jDefinite position.

Experiment showed, that method optimal speed proposed by the invention is fast, it is excellent to optimize the result, and saves the internal memory of computer, has the ability of optimizing large-scale circuit.

Description of drawings:

Fig. 1: the power line pessimistic concurrency control of integrated circuit,

The 1-supply rings,

Bus is strengthened in the 2-power supply,

The 3-power rail,

4-standard cell block (cell).

Fig. 2: the RLC analytical model of power-line network.

Fig. 3: the unit receives the time time-dependent current source model of electric current.

Fig. 4: the time time-dependent current source piecewise linearity represent.

Fig. 5: the voltage waveform of supply network node and the situation of violating constraint.

Fig. 6: when asking the gradient of the relative electric capacity width of penalty function vector, the current excitation in the adjoint network on the i node.

Fig. 7: the chip layout behind the interpolation decoupling capacitor,

5-standard cell block (cell),

6-decoupling capacitance (deccp).

Fig. 8: main program flow chart of the present invention.

Fig. 9: the program flow diagram of using among the present invention of finding the solution unconstrained optimization problem.

Figure 10: example u_cnt100 is carried out the result that obtains after the transient analysis, have 91 points in violation of rules and regulations.White nodes among the figure i.e. the violation point.

Figure 11: cell layout and decoupling capacitance distribution situation that example u_cnt100 finally obtains after optimizing.

Embodiment:

With the def that industrial quarters provides, the test circuit example u_cnt100 of 1ef form does example adds decoupling capacitance with method of the present invention in conjunction with Fig. 8 optimization.

1. read in file---comprise the u_cnt100.lef of library unit information, comprise the u_cnt100.def of cell interconnection information, Parameter File power.params and comprise the file current.dat that receives current information.Set up the structure of circuit according to the information of reading in;

2. the supply network of setting up is carried out transient analysis based on equivalent electric circuit, obtain the voltage waveform of 806 nodes on the network;

3. the result that this supply network is carried out transient analysis exists 91 to violate obligatory points, as shown in figure 10, need add the optimization of decoupling capacitance to this network;

4. with the voltage waveform piecewise linearity record on 744 leaf nodes, be used for the calculating of optimizing process gradient;

5. determine optimization aim and constraints;

6. the structure penalty function is converted into unconstrained optimization problem with the nonlinear constrained optimization problem;

7. it is α=2 that the penalty factor initial value is set; Can add on the position of decoupling capacitance at each, just on the position of leaf node the initial value of decoupling capacitance is made as the minimum capacity width of permission, be 1/3rd of minimum unit width in the present example, obtains electric capacity width vector as initial solution; Provide limits of error ε ₁=1e-6;

8. establish be solved to the l time of this unconstrained optimization problem, find the solution current unconstrained optimization problem, obtain current optimal solution electric capacity width vector W ^(l)

8.1 establish initial solution is W ⁽⁰⁾, error is limited to ε ₂=1e-2;

8.2 the initial optimization direction is made as the negative gradient direction of penalty function about electric capacity width vector;

8.3 set up the adjoint network of former supply network, concrete grammar is that the topological structure of adjoint network is identical with former network; Each resistance, electric capacity and inductive branch remain unchanged; Original independent voltage source short circuit, the independent current source open circuit; Current excitation on each leaf node is value as shown in Figure 6.Adjoint network is carried out transient state find the solution, obtain the voltage waveform on each node, find the solution each the node voltage waveform that obtains, bring into and solve the gradient of penalty function in the formula 19 for electric capacity width vector in conjunction with former network;

8.4 carry out linear search along the current optimization direction of being asked, find the non-negative linear search factor, make the value of penalty function on current optimization direction, reach optimum;

8.5 upgrade electric capacity width vector according to formula 21;

If 8.6 ‖ f (W ^(k+1)) ‖＜ε ₂, this unconstrained optimization finishes to release, and changes step 9;

In this example, the dimension m=744 of electric capacity width vector,

If k=744, then W ⁽⁰⁾=W ^(k+1), f (G ⁽⁰⁾)= f (G ^(k+1)), turn to step 8.2;

If the optimization direction is upgraded according to formula 22 in k＜744, get back to step 8.4 and continue to optimize;

9. calculate p according to optimizing the result _tValue, if p _t＜ε ₁, current electric capacity width vector promptly is the optimal solution of asking, algorithm finishes to withdraw from; Otherwise upgrade penalty factor α, establish l=l+1, get back to step 8 and continue to optimize; Found the solution unconstrained optimization problem in this example altogether 13 times;

10. finally carry out the capacitance values adjustment; Through adjusting, 744 decoupling capacitances that obtain after the optimization finally are adjusted into 195;

11. suitably adjust the cell layout in every row, the decoupling capacitance of interpolation can be positioned in the white space of layout, cell layout that obtains at last and decoupling capacitance distribution situation are as shown in figure 11.

This algorithm is at CPU 450M, realizes on the Sun Solaris V880 work station of internal memory 2G and moves, and all codes utilize C language and C++ to write.

Claims (1)

1. realize the fast method that integrated circuit electricity supply network noise is optimized with decoupling capacitance, contain useful placement decoupling capacitance step with raising supply network reliability in the blank area of Butut, it is characterized in that, it is that a kind of computer that utilizes is at based on the layouts characteristics of the application-specific integrated circuit (ASIC) (ASIC) of standard cell cloth chart-pattern and the design feature of supply network thereof, will in order to keep node voltage stably the area of decoupling capacitance as the target of optimizing, the method that the method for employing Non-Linear Programming is effectively found the solution the electricity supply network noise optimization problem, it is penalty function method, equivalent electric circuit, the method of conjugate gradient method and expansion Teller root adjoint network forms a whole acting in conjunction on power/grounding line network is optimized, and obtains good optimization effect; Particularly, it contains following steps successively:

(1) computer reads in the file that comprises supply network information and cell layout's information: supply network information comprises the relational structure between the supply network node; The time dependent current waveform (utilizing PWL to represent) that receives of the unit module that intrinsic decoupling capacitance value (capacitance characteristic that shows when unit module is static), electric capacity initial voltage and current value and each node are connected on resistance value between the node, inductance value, inductance initial voltage and current value, the sheet, in computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node); Cell layout's information comprises the relative position relation between number of unit, unit coordinate and the unit in each cell row, according to these information, we can obtain the long-pending distribution situation of blank face on the information of the blank area between the unit and each cell row, and additional decoupling capacitance just is added on these white spaces;

(2) parameter information that utilizes input carries out transient analysis based on equivalent electric circuit to supply network, obtains the voltage waveform of each node;

(3) if the voltage of each node is not violated the situation of constraint to be occurred, then do not need supply network is done optimization;

Otherwise execution following steps:

(4) with the voltage waveform piecewise linearity record of each node, be used for the calculating of optimizing process gradient;

(5) determine that the target function of optimizing is the area of the decoupling capacitor of interpolation, under the constraints of correspondence, minimize:

$\min A=\underset{j\&Element;M}{\mathrm{\&Sigma;}}(w_j\&times;H)--\left(1\right),$

M is the node set that allows to add decoupling capacitance, M={1 ..., m}, M N; N is the set of all nodes in the supply network, N={1 ..., n}; H is the height of standard cell, w _jBe the decoupling capacitor c that is added on the node j _jWidth;

Constraints is as follows:

(5.1) voltage drop constraint:

Be of the voltage drop of each node,, promptly be lower than the integrated value S of the voltage segment of voltage threshold on each node with the value that can effectively weigh the voltage drop noise with respect to supply voltage _iExpression:

$s_i={\&Integral;}_0^T\max (V_{\min }-v_i\left(t\right),0)\mathrm{dt}={\&Integral;}_{t_1}^{t_2}(V_{\min }-v_i\left(t\right))\mathrm{dt}--\left(2\right)$

[t ₁, t ₂] violate the time interval of voltage drop constraint, V for the i node _MinBe voltage Fujian value, v _i(t) be the magnitude of voltage of i node;

(5.2) electromigration constraint:

With [t ' ₁, t ' ₂] in the time, supply network branch (p, when q) maximum current density that allows of the absolute value of two ends node voltage difference and technology is σ at branch length l _PqOn the integrated value of difference of voltage drop represent:

$u_{p,q}={\&Integral;}_0^T\max [\left({|v}_p\left(t\right){-v}_q\left(t\right)\right|-\mathrm{\&rho;}{l}_{p,q}\mathrm{\&sigma;}),0]\mathrm{dt}={\&Integral;}_{{t^{\&prime;}}_1}^{{t^{\&prime;}}_2}\left(\right|v_p\left(t\right)-v_q\left(t\right)|-\mathrm{\&rho;}{l}_{p,q}\mathrm{\&sigma;})\mathrm{dt}--\left(3\right)$

Wherein, v _pAnd v _qBe respectively power supply branch (p, the q) voltage of two end nodes, v _p-v _qI.e. voltage difference on this branch; ρ is a square resistance; l _PqBe branch (p, length q);

(5.3) decoupling capacitor is area-constrained:

Be in every cell row, the decoupling capacitor area of interpolation is smaller or equal to the blank area in this cell row, and the height H of cell row is a definite value, therefore can directly use width means area size:

${\mathrm{dw}}_r=\max (\underset{y\&Element;\mathrm{ND}\left(r\right)}{\mathrm{\&Sigma;}}{w}_{r,y}-{\mathrm{rw}}_r,0),r\&Element;\mathrm{NR}--\left(4\right)$

NR is the set of cell row; ND (r) be r capable in the location sets of decoupling capacitor; w _{R, y}Be meant the width of the decoupling capacitor that is positioned at the capable y of r position; Rw _rIt is the overall width of the blank area of r on capable; Dw _rBe that r violates the area-constrained punishment amount of decoupling capacitor on capable, will in the penalty function method of back, use;

(5.4) decoupling capacitor Breadth Maximum constraint:

The width of any one decoupling capacitor that adds in certain cell row is less than or equal to the long-pending width of maximum empty fine flour in the one's own profession;

ew _r，y＝max(w _r，y-rw _r，0)，r∈NR，y∈ND(r)，——(5)，

Ew _{R, y}Be the punishment amount of violating the constraint of decoupling capacitor Breadth Maximum on capable y the position of r, will in the penalty function method of back, use;

(6) structure penalty function f is converted into unconstrained optimization problem with the nonlinear constrained optimization problem:

$\min f=A+p_t$

$=A+\mathrm{\&alpha;}\&CenterDot;(\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i^2+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}^2+\underset{r\&Element;\mathrm{NR}}{\mathrm{\&Sigma;}}d{w}_r^2+\underset{r\&Element;\mathrm{NR},y\&Element;\mathrm{ND}\left(r\right)}{\mathrm{\&Sigma;}}e{w}_{r,y}^2),--\left(6\right),$

Wherein, A is the decoupling capacitor gross area, and B is the set of all branches in the electric power network, P _tBe that to penalize item, α be penalty factor;

(7) initial value of penalty factor α is set; Each locational decoupling capacitor initial value that can add decoupling capacitor all is made as the minimum capacity width of permission, obtains the initial solution of electric capacity width vector as following unconstrained optimization; Provide limits of error ε in addition ₁＞0;

(8) find the solution current unconstrained optimization problem, obtain current optimal solution electric capacity width vector W ⁽¹⁾

(8.1) initial solution of establishing current unconstrained optimization problem is electric capacity width vector W ⁽⁰⁾, error is limited to ε ₂＞0;

(8.2) the initial optimization direction is made as penalty function about electric capacity width vector W ⁽⁰⁾The negative gradient direction:

If the initial optimization direction is P ⁽⁰⁾, gradient direction is f (W ⁽⁰⁾),

Get P ⁽⁰⁾=- f (W ⁽⁰⁾)-(7),

(8.3) ask the gradient of penalty function with the adjaiont network method of expansion with respect to electric capacity width vector:

$\&dtri;f\left(W\right)=[\frac{\&PartialD;f}{{\&PartialD;w}_1},\frac{\&PartialD;f}{{\&PartialD;w}_2},\&CenterDot;\&CenterDot;\&CenterDot;,\frac{\&PartialD;f}{{\&PartialD;w}_j},\&CenterDot;\&CenterDot;\&CenterDot;,\frac{\&PartialD;f}{{\&PartialD;w}_m}{]}^T,j\&Element;M--\left(8\right),$

Width is w _jElectric capacity c _jBe connected on the node j of supply network, suppose that node j is positioned at the capable yj position of rj, then penalty function f is with respect to w _jPartial derivative can be expressed as:

$\frac{\&PartialD;f}{{\&PartialD;w}_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+2\mathrm{\&alpha;}[\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{{\&PartialD;s}_i}{{\&PartialD;w}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{{\&PartialD;w}_j}]--\left(9\right),$

rj∈NR，yj∈ND(rj)

Relation according to capacitance size and width:

$c=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{T_{\mathrm{ox}}}\&times;w\&times;H---\left(10\right),$

ε _OxAnd T _OxBe respectively the dielectric constant and the thickness of an oxide layer;

$\frac{\&PartialD;f}{{\&PartialD;w}_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+\frac{2\mathrm{\&alpha;}{\mathrm{\&epsiv;}}_{\mathrm{ox}}H}{T_{\mathrm{ox}}}[\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{{\&PartialD;s}_i}{{\&PartialD;c}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{{\&PartialD;c}_j}]--\left(11\right),$

rj∈NR，yj∈ND(rj)

By the primary circuit network being set up a series of adjoint networks of each node in the corresponding circuits, and after making circuit sensitivity and analyzing, obtain:

$\frac{{\&PartialD;s}_i}{{\&PartialD;c}_j}={\&Integral;}_0^T{v}_{j,E_i}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}--\left(12\right),$

$\frac{{\&PartialD;u}_{\mathrm{pq}}}{{\&PartialD;c}_j}={\&Integral;}_0^T{v}_{j,t_{\mathrm{pq}}}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}--\left(13\right),$

$={\&Integral;}_0^T[v_{j,E_p}^{\&prime;}\left(t\right)-v_{j,E_q}^{\&prime;}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt}$

Wherein, ${\stackrel{.}{v}}_j(T-t)=\frac{{\mathrm{dv}}_j(T-t)}{\mathrm{dt}}$ Be the derivative of the voltage of j node in the primary circuit network to time t; V ' _{J, Ei}(t) be j node in the adjoint network of setting up corresponding to node i voltage (v ' _{J, Ep}(t), v ' _{J, Eq}(t) in like manner), it can be expressed as follows:

$v_{j,E_i}^{\&prime;}\left(t\right)=Z\left(j\right)v_{E_i}^{\&prime;}\left(t\right)=Z\left(j\right)G^{-1}[E_i\left(t\right)+{\mathrm{EC}}_i\left(t\right)+{\mathrm{EL}}_i\left(t\right)]--\left(14\right),$

Wherein, Z (j) is a choice of location vector, and this vector is 1 except the locational element value of j, and other element all is 0, promptly Z (j)=[0,0 ..., 0,1,0 ..., 0];

G is the relational matrix among the nodal voltage equation group G*V=I;

E _i(t) be the current source vector, its value is except that the element value of node i correspondence, and remaining element value all is 0, and the element value of node i correspondence is-1 when this node is violated the voltage drop constraint, is 0 when this node is not violated constraint;

EC _i(t) and EL _i(t) be to do the current source vector that obtains after the equivalence corresponding to electric capacity and inductance element in the adjoint network of node i foundation;

So obtain:

$\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{{\&PartialD;s}_i}{{\&PartialD;c}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{{\&PartialD;c}_j}$

$=\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i({\&Integral;}_0^T{v}_{j,E_i}^{\&prime;}\left(t\right)\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt})+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\left({\&Integral;}_0^T\right[v_{j,E_p}^{\&prime;}\left(t\right)-v_{j,E_q}^{\&prime;}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\mathrm{dt})--\left(15\right),$

$={\&Integral;}_0^T\{{\stackrel{.}{v}}_j(T-t)\&times;\{\underset{i\&Element;N}{\mathrm{\&Sigma;}}(s_i\&times;v_{j,E_i}^{\&prime;}\left(t\right))+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}\{u_{\mathrm{pq}}\&times;[v_{j,E_p}^{\&prime;}\left(t\right)-v_{j,E_q}^{\&prime;}\left(t\right)\left]\right\}\left\}\right\}\mathrm{dt}$

According to formula (14), (15) obtain:

$\underset{i\&Element;N}{\mathrm{\&Sigma;}}{s}_i\frac{{\&PartialD;s}_i}{{\&PartialD;c}_j}+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}{u}_{\mathrm{pq}}\frac{{\&PartialD;u}_{\mathrm{pq}}}{{\&PartialD;c}_j}=Z\left(j\right)G^{-1}{I}_{\mathrm{total}}\left(t\right)--\left(16\right),$

I wherein _Total=I _New(t)+EC (t)+EL (t)---(17),

$I_{\mathrm{new}}\left(t\right)=\underset{i\&Element;N}{\mathrm{\&Sigma;}}[s_i+E_i\left(t\right)]+\underset{(p,q)\&Element;B}{\mathrm{\&Sigma;}}\{u_{\mathrm{pq}}\&times;[E_p\left(t\right)-E_q\left(t\right)\left]\right\}--\left(18\right),$

Wherein, EC (t) and EL (t) are with I _NewDuring as the current excitation of adjoint network, electric capacity and inductance element are done the current source vector that obtains after the equivalence;

Thereby obtain:

$\frac{\&PartialD;f}{{\&PartialD;w}_j}=H+2\mathrm{\&alpha;}({\mathrm{dw}}_{\mathrm{rj}}+{\mathrm{ew}}_{\mathrm{rj},\mathrm{yj}})+\frac{2{\mathrm{\&alpha;\&epsiv;}}_{\mathrm{ox}}H}{T_{\mathrm{ox}}}{\&Integral;}_0^T\left\{\right[Z\left(j\right)\&times;G^{-1}\&times;I_{\mathrm{total}}\left(t\right)]\&times;{\stackrel{.}{v}}_j(T-t)\}\mathrm{dt}--\left(19\right),$

rj∈NR，yj∈ND(rj)，j∈M

(8.4) establish iteration and proceeded to the k step, it is respectively to be W that current electric capacity width vector sum is optimized direction ^(k)And P ^(k), along P ^(k)Carry out linear search, find non-negative linear search factor lambda _k, make penalty function at P ^(k)Reach optimum on the direction, that is:

f(W ^(k)+λ _kP ^(k))＝minf(W ^(k)+λP ^(k)) ——(20)，

(8.5) upgrade electric capacity width vector W according to following formula ^(k+1):

W ^(k+1)＝W ^(k)+λ _kP ^(k) ——(21)，

(8.6) if ‖ f is (W ^(k+1)) ‖＜ε ₂, this unconstrained optimization finishes to withdraw from, and changes step 9;

Otherwise the dimension of establishing electric capacity width vector is m,

If k=m, then W ⁽⁰⁾=W ^(k+1), f (G ⁽⁰⁾)= f (G ^(k+1)), turn to step 8.2;

If k＜m upgrades the optimization direction according to following formula, get back to step 8.4 and continue to optimize;

(9) calculate the value of penalizing item according to optimizing the result, if p _t＜ε ₁, current electric capacity width vector promptly is the optimal solution of asking, algorithm finishes to withdraw from; Otherwise upgrade penalty factor α, establish l=l+1, get back to step 8 and continue to optimize;

(10) because the actual decoupling capacitor value that can add is not continuous, have the restriction of least unit numerical value, we adjust the optimization result who finally obtains; If the decoupling capacitor value that add certain position then merges to it on contiguous node less than minimum value, forming bigger electric capacity, and these electric capacity are adjusted into the multiple of least unit numerical value.

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