CN1206722C - Solving method for transient analysis of power source network based on equivalent circuit - Google Patents

Abstract

The present invention relates to a method for transient analysis of a power source network of an integrated circuit on the basis of an equivalent circuit, which belongs to the design field of placement and routing in VLSI physical design. The present invention is characterized in that the method aims at the characteristics that the power source wire/ground wire of a special integrated circuit (ASIC) comprises large quantity of chain topological structures by using a computer. The parameters R, L and C of an RLC circuit for the intermediate node of a link, and a current source are equivalent to the nodes at both ends of the link. A linear equation is listed according to an equivalent circuit only composed of the nodes at both ends of all links. The voltage of each end of all links of the equivalent circuit is quickly solved by the existing method at this point. The method solves the voltage value of combined nodes of all the links according to the voltage value at this point. The present invention has the advantages of rapidness and internal storage saving, and not only can expand the scale for chip processing, but also can meet precision requirements.

Description

Method based on the ic power network transients analysis and solution of equivalent electric circuit

Technical field

Method based on the ic power network transients analysis and solution of equivalent electric circuit belongs to VLSI physical Design field, especially RLC power line in the layout routing field/earth cord network transient analysis solution technique category.

Background technology

In the chip physical Design, the wiring of power line/ground wire belongs to the wiring portion of special gauze, designing improperly, power line/earth cord network can cause a series of serious problems, can not get the damage of the excessive caused supply network of current density of a certain branch road in the caused logic error of enough supply power voltages, the supply network etc. as semiconductor device, therefore in the wiring stage, the wiring of power line/ground wire has limit priority.

Along with the manufacturing process of integrated circuit enters into sub-micro (VDSM) by present deep-submicron (DSM), the design scale of integrated circuit is also by ultra-large (VLSI), and very extensive (ULSI) is to G extensive (GSI) development.Because chip power-consumption sharply increases and chip power supply voltage constantly reduces, and makes supply network that increasing operating current must be provided.Simultaneously along with being increased sharply of working frequency of chip, make parasitic capacitance, inductance to the increase day by day of supply network influence, power line/earth cord network analysis has been converted to complicated transient analysis from better simply dc analysis.All these make the safe power supply problem of chip become one of topmost thorny problem in the chip design manufacture process, also are that restriction chip performance and scale continue one of main bottleneck that improves, and therefore are subjected to the unprecedented attention of academic and industrial quarters.

Because the improving constantly of production technology, constantly the dwindling of semiconductor device, the density of line becomes increasing, makes increasing to the demand of interconnection resource.Simultaneously because supply network need provide increasing operating current, thus supply network for the supply power voltage that guarantees each unit greater than minimum normal working voltage, also must widen the width of power line/ground wire, strengthened demand to interconnection resource.Like this, design one and occupy the least possible safe power supply network of interconnection resource, just become wires design stage important target.After the power line of circuit/earth cord network design is finished, for the supply power voltage that guarantees each unit greater than minimum normal working voltage, also must carry out analysis verification to whole design, promptly power line/earth cord network is carried out transient analysis and finds the solution.Therefore the transient analysis solver of efficient, an accurate power line/earth cord network is the basis of supply network design optimization in the chip, also is the verification tool of power supply gauze design correctness, and it can shorten the design cycle of chip simultaneously.Background knowledge and technology that following portions introduction is mainly relevant.

At the ASIC circuit based on the standard cell design, its power-line network as shown in Figure 1 and Figure 2.Circuit is the standard cell power supply by the power supply loop wire with the power rail that connects thereon, for the supply power voltage that guarantees each unit greater than minimum normal working voltage, generally also to increase some power supplies and strengthen buses.

Power line/ground wire roughly becomes the fully connected topology of a grid (Mesh), and following Fig. 3 is one and considers resistance (R), inductance (L), the rlc circuit analytical model of the power-line network of electric capacity (C) influence.

Wherein utilize in current source (PWL) analog chip that segmentation represents modular unit (cell) to go up the time dependent current value that receives.Power-line network just to these unit power supplies, guarantees that each unit can operate as normal.The purpose of power supply gauze sunykatuib analysis be exactly solve all unit modules each the time magnitude of voltage that engraves, the basis is provided for the verification of correctness of power-line network and optimization.

Because the electric current that receives of unit module changes the continuous variation that causes unit module voltage in time continuously, so the electric power network analysis and solution is a transient analysis problem.For the ease of in time domain, carrying out analysis and solution, generally transient problem must be converted into the quasi-static analysis problem, an enough little time step promptly is set, the transient simulation in the one-period is converted to enough a plurality of quasistatic direct currents finds the solution problem.

It is an On Solving System of Linear Equations problem that the quasistatic direct current is found the solution in the question essence.At first according to the topological structure and kirchhoff (Kirchhoff) law of circuit network, set up circuit equation for each node, the equations simultaneousness with all obtains system of linear equations.Power-line network is by electric capacity, inductance, and resistance, current source and voltage source are formed, and character sparse, symmetrical, positive definite that the coefficient matrix of linear equations of power-line network has can utilize more existing highly effective algorithms directly to find the solution.

To sum up, the power-line network transient analysis solution procedure of integrated circuit is as follows: the step-length of (1) selected transient analysis and the total step number of definite required simulation, (2) on each simulation steps, earlier according to topology of networks and Kirchhoff's law, set up the system of linear equations of circuit, utilize the derivation algorithm of equation group to solve each magnitude of voltage of each node constantly again.

Along with the increase day by day of integrated circuit integrated level, the raising gradually of technology, the transient analysis of power-line network are found the solution also to become and are become more and more important and complexity.Recently academia has done a lot of important breakthrough research work that have in this respect, and multi-grid method (multi grid), stratification (hierarchical method), pre-excellent conjugation tonsure method (PreconditionConjugate Gradient-PCG), the hierarchical model depression of order (hierarchical model order reduction) are wherein arranged.Though these new methods have very much progress for the analysis of the electric power network of large-scale circuit, but they do not have fully to investigate the characteristic of the electric power network structure of chip, do not make full use of the regularity of supply network structure, therefore mostly have the shortcoming that computational speed is slow, committed memory is many.For this reason, at ASIC circuit based on the standard cell design, consider the regularity characteristics of its electric power network, our structure and design realized accurately, efficiently based on the ic power network transients analysis and solution device of equivalent electric circuit, under the prerequisite of not losing accuracy and save memory, increased substantially the speed of analysis and solution, enlarged the chip-scale of analysis and solution,, obtained best up to now result for handling large-scale chip.

Summary of the invention

The objective of the invention is to design a kind of ic power network transients analysis and solution device, under the situation of not losing accuracy, increase substantially the speed of analysis and solution, the chip-scale that expansion can be found the solution based on equivalent electric circuit.The basis of invention is the ordered structure of power line/earth cord network, wherein a large amount of RLC chain structure circuit that exist shown in figure (4):

The main thought of invention is: (1) at the characteristics of the power-line network chain topological structure (as shown in Figure 4) of ASIC circuit, with the electrical parameter equivalence of node in the chain to two end nodes of this chain.(2) for the equivalent electric circuit that only constitutes by two end nodes of all chains, since very little according to the listed system of linear equations scale of this equivalent circuit, existing derivation algorithm can be adopted, calculate the magnitude of voltage of this each end points of equivalent electric circuit constantly fast.(3) according to this two ends node voltage of all chains constantly, solve all chains by this magnitude of voltage constantly of merge node, to reach the purpose of sunykatuib analysis.Because in whole process, finding the solution system of linear equations is a step the most consuming time and the consumption internal memory, thus reduce the process that the scale of equation group can shorten whole analysis and solution significantly, and the expense of compression memory significantly.

In the present invention, we will be only with the node definition of two other node connections be intermediate point (Middle Node), such as N ₂, N ₃N _iAnd N _nCorresponding with it, with node definition more than two other node connections be joint (CrossNode), as N ₁And N _N+1Node.The core content of invention is exactly for the such long-chain of each bar, and the Cross Node that all Middle Node is merged to two ends gets on, and making circuit reduction is the equivalent electric circuit of only being made up of Cross Node.After the circuit equation group of finding the solution equivalent electric circuit again obtains this voltage constantly of each Cross Node, further recover to find the solution this magnitude of voltage constantly of all MiddleNode.

1, method based on the ic power network transients analysis and solution of equivalent electric circuit, it contains the step that power line/network of wires is carried out transient analysis based on dc analysis, it is characterized in that, it may further comprise the steps: utilize computer to contain the characteristics of a large amount of chain topological structures at the power line/earth cord network of application-specific integrated circuit (ASIC), the parameters R of the rlc circuit of link intermediate node, L, C and current source equivalence are to this both link ends node, again for the equivalent electric circuit that only constitutes by two end nodes of all links, list system of linear equations, solve this magnitude of voltage of all each end points of link of equivalent electric circuit constantly more in view of the above, obtain in view of the above again in all links by this magnitude of voltage constantly of merge node.

2, according to the method for 1 described ic power network transients analysis and solution based on equivalent electric circuit, its characteristics are that it contains following steps successively:

The 1st step: computer reads in the message file of circuit, comprises the relational structure between the node in the file; The changing in time of the supply module unit that resistance value between the node, inductance value, inductance initial voltage and current value, capacitance, electric capacity initial voltage and current value and each node are connected utilizes the current waveform that receives that PWL represents, in computer, set up the information of circuit in view of the above, and all intermediate points of mark and joint;

The 2nd step: according to the work period of circuit and the periodicity of needs simulation, computer reads in corresponding time step h and total simulation step number M respectively;

The 3rd step: the electric capacity in the discretization ifq circuit, inductance obtain the circuit of being made up of resistance, current source:

The 3.1st step: capacitor C in the discretization circuit or resistance L,

The time step of given simulation is utilized trapezoidal difference formula, and K+1 moment electric capacity disperses and turns to an equivalent resistance With an equivalent current source $\frac{2C}{h}{V}_{c,k}+I_{c,k}$ Model in parallel,

$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})---\left(1\right),$

V _{C, k}, I _{C, k}, V _{C, k+1}, I _{C, k+1}Represent the voltage and current on K and the K+1 moment electric capacity respectively, its direction is consistent;

The time step of given simulation is utilized trapezoidal difference formula, and K+1 moment inductance disperses and turns to an equivalent resistance

With an equivalent current source $\frac{h}{}$ $\frac{}{2L}{V}_{L,k}+I_{L,k}$ Model in parallel,

$I_{L,k+1}=\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k+1}+(\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k}+I_{L,k})---\left(2\right),$

V _{L, k}, I _{L, k}, V _{L, k+1}, I _{L, k+1}Represent the voltage and current on k and the k+1 moment inductance respectively, its direction is consistent;

The 3.2nd step:, set up the discretization model of ifq circuit according to the discretization process in (3.1);

The 4th step: merge all intermediate nodes, set up the equivalent electric circuit of forming by the node that crosses:

The 4.1st step: utilize the Norton equivalent law to merge current source with the simplification circuit,

For a link that contains N+1 node, be vertex ticks 1 to N+1 from left to right, (the resistance R between 1＜i＜N) of adjacent node i and i+1 on the link _iThe series circuit of forming with K+1 moment discretization inductance is reduced to by equivalent resistance R _i ^*With equivalent current source el _{I, k+1}The parallel circuits of forming:

$R_i^{*}=2L_i/h+R_i---\left(3\right),$

${\mathrm{el}}_{i,k+1}=(\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L_i/h+R_i}---\left(4\right),$

R _i, L _iBe respectively resistance and inductance value between node i and node i+1;

V _{L, i, k}, E _{I, k}Be respectively K L constantly _iOn electric current and magnitude of voltage, direction by the i+1 node to the i node;

El _{I, k+1}Be behind the equivalent-simplification and R _i ^*Equivalent current source in parallel;

The 4.2nd step: the current source over the ground on the merge node i,

Constantly for node i, modular unit received electric current e at K+1 _{I, k+1}With the discretization capacitor C _iThe effect circuit that obtains is merged into by current source ec _{I, k+1}With resistance r _iThe circuit that composes in parallel:

${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right),$

$r_i=\frac{h}{2C_i}---\left(6\right)$

C _iBe respectively node i associated capacitance value over the ground;

V _{I, k}, I _{I, k}Be respectively K constantly magnitude of voltage on the node i and the current value by electric capacity, direction over the ground;

Ec _{I, k+1}Expression constantly self receive electric current by i node K+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (5), the sense of current over the ground;

The 4.3rd step: Y type circuit is to the equivalent transformation of pi-network:

Be two end points by three adjacent successively nodes and the Y type conversion of circuits formed of ground with form pi-network;

General, three nodes establishing the Y circuit are x, y, z, wherein node Z ground connection), intermediate node is o, the structure of Y type circuit is:

Between end points x, o: by resistance R _xWith current source I _x, compose in parallel to the x direction from o,

Between end points y, o: by resistance R _yWith current source I _y, from composing in parallel to the y direction for o,

Between end points z, o: by resistance R _zWith current source I _z, compose in parallel to the z direction from o,

The structure of the pi-network that equivalence posterior nodal point x, y and z form is:

Between node x, the y by equivalent resistance R _XyWith equivalent current source I _XyCompose in parallel, wherein:

$R_{\mathrm{xy}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_z},$ $I_{\mathrm{xy}}=\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}---\left(7.1\right),$

Between node x, the z by equivalent resistance R _XzWith equivalent current source I _XzCompose in parallel, wherein:

$R_{\mathrm{xz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_y},$ $I_{\mathrm{xz}}=\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xy}}}---\left(7.2\right),$

Between node y, the z by equivalent resistance R _YzWith equivalent current source I _YzCompose in parallel, wherein:

$R_{\mathrm{yz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_x},$ $I_{\mathrm{xz}}=\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}---\left(7.3\right),$

Therefore, the size of current of inflow node x is:

$E_x=\frac{V_y-V_x}{R_{\mathrm{xy}}}-\frac{V_x}{R_{\mathrm{xz}}}+\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xz}}}\right)---\left(8\right),$

The size of current that flows into node y is:

$E_y=\frac{V_x-V_y}{R_{\mathrm{xy}}}-\frac{V_y}{R_{\mathrm{yz}}}-\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}\right)---\left(9\right),$

The 4.4th step: the equivalent transformation of parallel circuits:

Parallel circuits between two nodes is done to merge the simplification conversion:

r _total＝1/(1/r _left+1/r _right) ——(10)，

i _total＝i _left+i _right ——(11)，

r _Left, r _Right, i _Left, i _Right, represent the size of two resistance and current source respectively;

r _Total, i _TotalThe all-in resistance after expression merges respectively and the size in total current source;

The 4.5th step: merge intermediate node, simplify obtaining final equivalent electric circuit:

Recycle top principle and step, merge the intermediate node of every link, obtain the π type equivalent electric circuit of every link, for a link that contains N+1 node, be labeled as 1 to N+1 from left to right, final π type equivalent circuit structure is as follows:

End points 1 is between N+1: equivalent resistance R _{1, n+1} ^EquivWith equivalent current source I _{1, n+1, k+1} ^Equiv, from N+1 to 1 direction parallel connection;

End points 1 is between ground: equivalent resistance R ₁ ^EquivWith equivalent current source I _{1, k+1} ^Equiv, from 1 to the place to parallel connection;

End points N+1 is between ground: equivalent resistance R _N+1 ^EquivWith equivalent current source I _{N+1, k+1} ^EquivFrom N+1 to the place to parallel connection;

Circuit reduction is the equivalent electric circuit of the simplification of the node composition that only crosses the most at last;

The 5th step: the nodal voltage equation group of setting up the equivalent electric circuit that obtains by step (4.5) according to Kirchhoff's law $G\&CenterDot;\stackrel{\mathrm{\&rho;}}{V}=\stackrel{\mathrm{\&rho;}}{I},$ Thereby obtain only relevant sparse coefficient matrix G with circuit structure and resistance;

The 6th step: beginningization simulation, make step counter K=0, obtain the initial voltage value of each node by the PWL oscillogram of each node, this value should equal the initial voltage value of each node associated capacitance, thus structure

The 7th step: if K＞M, then end simulation;

Otherwise execution following steps:

The 8th step: the PWL waveform extracting K+1 step by each node constantly each node supply module unit receive electric current, calculate the K+1 current vector on equation group the right constantly Bring the system of linear equations that obtains by step (5) into:

$G\&CenterDot;{\stackrel{\mathrm{\&rho;}}{V}}_{k+1}={\stackrel{\mathrm{\&rho;}}{I}}_{k+1}$

This step is received the PWL waveform of electric current according to the supply module unit of each node, extracts this their current value size constantly, utilizes then

Merge the size that obtains equivalent current by electric capacity, inductance discretization then through equivalent transformation according to formula (1) (2) (4) (5) (7) (11), finally obtain each this equivalence constantly of node that crosses and receive electric current, constitute vector

The 9th step: with existing method solving equation group $G\&CenterDot;{\stackrel{\mathrm{\&rho;}}{V}}_{k+1}={\stackrel{\mathrm{\&rho;}}{I}}_{k+1},$ Obtain cross the constantly magnitude of voltage vector of node of K+1

The 10th step: recover to find the solution this magnitude of voltage constantly of each intermediate node:

${\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n+1,k+1}-{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">I</figure-callout>}}_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}},$

V _{1, k+1}, V _{N+1, k+1}Be the magnitude of voltage of the K+1 moment two joints,

Then by node i from 2 to N, obtain the K+1 magnitude of voltage constantly of these all intermediate nodes of link:

$V_{i,k+1}=V_{i-1,k+1}+R_{i-1}^{*}(E_{i-1,k+1}-{\mathrm{el}}_{i-1,k+1}),$

$E_{i,k+1}=E_{i-1,k+1}+\frac{V_{i,k+1}}{r_i}+{\mathrm{ec}}_{i,k+1},$

V _{I, k+1}Expression i node is at the K+1 voltage in step, i ∈ [1, n+1];

R _i ^*Resistance between expression i node and node i+1, $R_i^{*}={2L}_i/h+R_i;$

r _iThe equivalent resistance that expression is obtained by electric capacity i discretization, r _i=h/2C _i

El _{I, k+1}The equivalent current that expression obtains after by inductance i discretization, the current value that obtains through resulting electric current discretization after the Norton equivalent conversion is tried to achieve by formula (4) again, direction by node i+1 to node i;

Ec _{I, k+1}Expression constantly self receive electric current by i node K+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (6), the sense of current by node i to ground;

E _{I, k+1}Expression K+1 step flows into the current value of i node, direction by node i+1 to node i;

The 11st step: the magnitude of voltage of K+1 all nodes is constantly preserved in output, puts K=K+1, forwards step (7) to, carries out next step simulation process.

Not only speed is fast under the situation of precision satisfying to experiment showed, method proposed by the invention, thereby and the internal memory that can save computer enlarge and can find the solution the scale of chip.

Description of drawings

Fig. 1: the power line pessimistic concurrency control of integrated circuit,

The 1-supply rings,

Bus is strengthened in the 2-power supply,

The 3-power rail,

4-standard module unit (cell).

Fig. 2: based on the ASIC circuit supply network diagram of standard cell design,

The 1-power rail,

The 2-power supply is strengthened bus,

The 3-ground wire is strengthened bus,

The 4-standard cell,

5-ground wire rail,

6-power supply loop wire,

7-ground wire loop wire.

Fig. 3: the RLC analytical model of power-line network.

Fig. 4: common RLC chain circuit in the power-line network.

Fig. 5: the discretization model of electric capacity, inductance,

1-K+1 is the discretization model of electric capacity constantly,

2-K+1 is the discretization model of inductance constantly.

Fig. 6: the model before the RLC link discretization.

Fig. 7: the model after the RLC link discretization.

Fig. 8: Nuo Dun (Norton) law of equivalence,

Before the 1-conversion,

After the 2-conversion.

Fig. 9: merge current source,

Before 1-merges,

After 2-merges.

Figure 10: utilize the link after the Norton law is simplified.

Figure 11: Y type circuit is to the equivalent transformation of pi-network,

Before the 1-conversion,

After the 2-conversion.

Figure 12: the equivalent transformation of parallel circuits,

Before the 1-conversion,

After the 2-conversion.

Figure 13: begin to do the equivalent transformation of Y type circuit to pi-network from an end of link.

Figure 14: the equivalent transformation of making parallel circuits.

Figure 15: continue to do the equivalent transformation of Y type circuit to pi-network.

Figure 16: a link is simplified the final equivalent electric circuit in back.

Figure 17: h receives current value constantly according to PWL waveform extracting (K+1).

Figure 18: 8 * 8 test example, * represents Cross Node, expression Middle Node, outer thick line is represented the power supply power supply rail, the internal layer fine rule is represented the gauze of powering.

Figure 19: a link illustration in the test example.

Figure 20: the discretization model of illustration.

Figure 21: the method simplification circuit that utilizes promise to pause (Norton) law and merge current source.

Figure 22: link is simplified the final equivalent electric circuit in back.

Figure 23: the final equivalent model of 8 * 8 test examples.

Figure 24: program flow chart of the present invention.

Embodiment

Now the present invention is described in detail according to step once in conjunction with figure (4):

1. read in the circuit information file, set up the ifq circuit structure

This is an input process, and the description document of ifq circuit is read in, and comprises the relational structure between the node in the file; The time dependent size of current of receiving of the supply module unit that the resistance value between the node, inductance value, capacitance and each node connect.In computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node).

2. set the time step h of simulation, the total step number N of simulation

This step is set the parameter of simulation, time step h and total step number M.The setting of time step h will be according to the circuit working cycle; The work week issue of needs simulation is depended in the setting of total step number.

3. discretization electric capacity, inductance obtain by resistance, current source, the circuit that voltage source is formed

Because the existence of electric capacity, inductance need utilize time step and difference formula to carry out the discretization process.Introduce the discretization process of electric capacity, inductance below.

3.1 electric capacity, the discretization of inductance

The time step of given simulation, according to the trapezoid formula of backward difference:

Electric capacity: $I_{c,k+1}=\frac{2c}{h}{V}_{c,k+1}-(\frac{2c}{h}{V}_{c,k}+I_{c,k})---\left(1\right)$

Inductance: $I_{L,k-1}=\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k+1}+(\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L}{V}_{L,k}+I_{L,k})---\left(2\right)$

Electric capacity, inductance can be by the discrete equivalent models that turns to resistance and current source parallel connection.As shown in Figure 5

V _{C, k}, I _{C, k}, V _{C, k+1}, I _{C, k+1}Represent the voltage and current on k and the k+1 moment electric capacity respectively, symbol and arrow mark among its direction such as Fig. 5.

V _{L, k}, I _{L, k}, V _{L, k+1}, I _{L, k+1}Represent the voltage and current on k and the k+1 moment inductance respectively, symbol and arrow mark among its direction such as Fig. 5.

C and L represent the value of electric capacity and inductance respectively, the simulated time step-length that the h representative is selected.

Like this, ifq circuit is the equivalent electric circuit of being made up of resistance, current source, voltage source by discretization.

3.2 the discretization model of electrical chain in the circuit

Be as drag wherein, see Fig. 6 as the RLC chain transformaiton among Fig. 4

4. merge all Middle Node, set up the equivalent electric circuit of forming by Cross Node

This is core of the present invention, exactly all Middle Node is merged to the CrossNode at two ends, the equivalent electric circuit that obtains simplifying.Give detailed introduction below.

4.1 the method for utilizing promise to pause (Norton) law of equivalence and merging current source is simplified circuit

On the basis of Fig. 5, utilize the Norton law, with of the conversion of the do of the local circuit in the electrical chain as Fig. 8.

$R_i^{*}=2L_i/h+R_i---\left(3\right)$

${\mathrm{el}}_{i,k+1}=(\frac{\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{2L_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/\mathrm{<figure-callout\; id="2L"\; label="h"\; filenames="C0310477000221.png"\; state="\{\{state\}\}">h</figure-callout>}}{{2L}_i/h+R_i}---\left(4\right)$

4.2 the merging current source, as shown in Figure 9.

${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right)$

$r_i=\frac{h}{2C_i}---\left(6\right)$

Through above-mentioned two steps, obtain circuit model as Figure 10.

The meaning of letter is as follows among Figure 10:

V _{I, k+1}Expression i node is at the k+1 voltage in step, i ∈ [1, n+1]

R _i ^*Resistance between expression i node and node i+1, $R_i^{*}={2L}_i/h+R_i$

r _iThe equivalent resistance that expression is obtained by electric capacity i discretization, r _i=h/2C _i

El _{I, k+1}The equivalent current that expression obtains after by inductance i discretization, the current value through obtaining behind the Norton equivalent transformation is tried to achieve by formula (4) again, and direction is shown in Figure 10 arrow.

Ec _{I, k+1}Expression constantly self receive electric current by i node k+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (5), the sense of current is shown in Figure 10 arrow.

E _{I, k+1}The expression k+1 step flows into the current value of i node, and direction is shown in arrow among Figure 10.

4.3 Y type circuit is to the equivalent transformation of pi-network

General, for a Y type circuit, we can have conversion shown in Figure 11

Wherein:

$E_a=\frac{V_b-V_a}{R_{\mathrm{ab}}}-\frac{V_a}{R_{\mathrm{ac}}}+(\frac{R_a{I}_a}{R_{\mathrm{ab}}}-\frac{R_b{I}_b}{R_{\mathrm{ab}}})-(\frac{R_c{I}_c}{R_{\mathrm{ac}}}-\frac{R_a{I}_a}{R_{\mathrm{ac}}})---\left(8\right)$

$E_b=\frac{V_a-V_b}{R_{\mathrm{ab}}}-\frac{V_b}{R_{\mathrm{bc}}}-(\frac{R_a{I}_a}{R_{\mathrm{ab}}}-\frac{R_b{I}_b}{R_{\mathrm{ab}}})-(\frac{R_c{I}_c}{R_{\mathrm{bc}}}-\frac{R_b{I}_b}{R_{\mathrm{bc}}})---\left(9\right)$

4.4 the equivalent transformation of parallel circuits is seen Figure 12

r _total＝1/(1/r _left+1/r _ight) ——(10)

i _total＝i _left+i _right ——(11)

4.5 merge Middle Node, simplify obtaining final equivalent electric circuit

Recycle top conversion, a final electrical chain can be reduced to equivalent electric circuit shown in Figure 16.Describe its process (saving the mark of formula in the diagram) below in detail.

From chain, a Y type circuit part is transformed into pi-network, the part shown in circle frame among Figure 13.

Merge the parallel circuits part then, the part shown in roundlet frame among Figure 14.

After obtaining circuit, continue to do the equivalent transformation of Y type circuit to pi-network as Figure 15.

Repeat above step, up to the equivalent electric circuit that link is reduced to final following Figure 16.

Intermediate node (Middle Node) is all merged like this, and circuit is reduced to the equivalent electric circuit of only being made up of joint (Cross Node).

5. obtain the sparse matrix of the circuit equation group of equivalent electric circuit

From formula (1) (2) (3) (6) (7) (10) (11) we as can be seen, by electric capacity and inductance discretization equivalent resistance only and electric capacity, the step-length of inductance and setting is relevant.Because these three parameters can not change in the dynamic analog analysis, so the value of all resistance can not change in the circuit after the discretization.

The circuit equation group shape of setting up according to kirchhoff as $G\&CenterDot;\stackrel{\mathrm{\&rho;}}{V}=\stackrel{\mathrm{\&rho;}}{I},$ Wherein G is a sparse matrix, only lead with electricity (inverse of resistance) relevant with the structure of circuit, so a demand gets once and gets final product.

6. step counter K=0 is put in initialization simulation.Obtain the initial voltage value (this value should equal the initial voltage value of each node associated capacitance) of each node by the PWL oscillogram of each node, make up thus

7. if K＞M, then end simulation;

Otherwise execution following steps.

8. extract the electric current that receives of each unit of the K+1 step moment, and by calculating current vector

According to each unit receive electric current PWL waveform, utilize then Merge the size that obtains equivalent current by electric capacity, inductance discretization then through equivalent transformation according to step (4) and formula (1) (2) (4) (5) (7) (11), final calculating is obtained each this equivalence constantly of node that crosses and is received electric current, obtains the K+1 current vector on equation group the right constantly Bring the system of linear equations that obtains by step (5) into $G\&CenterDot;{\stackrel{\mathrm{\&rho;}}{V}}_{k+1}={\stackrel{\mathrm{\&rho;}}{I}}_{k+1}.$

Because the electric current that receives of unit changes in time, it is current time that the extraction K+1 step big or small process of receiving electric current constantly can be utilized (K+1) h, according to the corresponding PWL parameter in each unit, obtain it and receive current value accordingly then, detailed process as shown in figure 17.

9. the group of solving an equation obtains the K+1 step magnitude of voltage of all Cross Node constantly

Find the solution coefficient matrix and have system of linear equations sparse, symmetrical, positive definite character, the algorithm of a lot of existing efficient maturations is arranged at present.We adopt is a kind of conjugation tonsure method ICCG (Incomplete Cholesky ConjugateGradient) that decomposes pre-excellent matrix based on incomplete Qiao Laisiji in the pre-excellent conjugation tonsure method (PCG, Precondition Conjugate Gradient).Find the solution finish after, obtain this magnitude of voltage of each Cross Node constantly, utilize vector Expression.

10. recover to find the solution this magnitude of voltage constantly of each Middle Node

After obtaining this step of all Cross Node voltage constantly, recover to find the solution this step of two Middle Node between Cross Node magnitude of voltage constantly one by one according to following formula and process, reach purpose to all node sunykatuib analyses.Utilize following processes and formula to realize:

${\mathrm{<figure-callout\; id="1"\; label="E"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">E</figure-callout>}}_{1,k+1}=\frac{V_{n+1,k+1}-{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">I</figure-callout>}}_{1,k+1}^{\mathrm{equiv}}-\frac{{\mathrm{<figure-callout\; id="1"\; label="V"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">V</figure-callout>}}_{1,k+1}}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="C0310477000221.png,C0310477000223.png"\; state="\{\{state\}\}">R</figure-callout>}}_1^{\mathrm{equiv}}};---\left(12\right)$

By j from 2 to N:

$V_{j,k+1}=V_{j-1,k+1}+R_{j-1}^{*}(E_{j-1,k+1}-{\mathrm{el}}_{j-1,k+1});---\left(13\right)$

$E_{j,k+1}=E_{j-1,k+1}+\frac{V_{j,k+1}}{r_j}+{\mathrm{ec}}_{j,k+1};---\left(14\right)$

So far, recovery calculates intermediate node (Middle Node) magnitude of voltage this moment between two nodes that cross (Cross Node).

11. the K+1 node voltage value in step is preserved in output, this step sunykatuib analysis finishes.Put K=K+1, carry out next step simulation.

Again, we adopt one to generate ourselves, but the example that does not lose general proxy property illustrates the specific embodiment of the present invention, carries out according to top flow chart.

This example vertical view (18) of 8 * 8, the working cell (cell) in each point among the figure (be labeled as * or) indication circuit, just we want the node of analysis mode, and they have the electric current of receiving and associated capacitance over the ground.On each bar line resistance and inductance are arranged, shown in following partial enlarged drawing.In this example, we utilize a supply rings of outside to represent power supply, and it can logic is seen as a node.According to the definition on top, obviously be labeled as the MiddleNode that () is, be labeled as the Cross Node that (*) is.Be the part in the middle of two Cross Node points in the circle frame among the figure, its side circuit is shown in figure (19), and following explanation will illustrate that mainly other parts by that analogy round this section local circuit.

1. read in the circuit information file, comprise in the file: the relational structure between the node; The time dependent current waveform (utilizing PWL to represent) that receives of the supply module unit that the resistance value between the node, inductance value, inductance initial voltage and current value, capacitance, electric capacity initial voltage and current value and each node are connected.In computer, set up the information of circuit in view of the above, and all intermediate points of mark (Middle Node) and joint (Cross Node).

2. set the time step h=T/120 of simulation, T is the work period of circuit.The total step number M=240 of simulation is equivalent to simulate two cycles

3. according to 3.1 and 3.2 process discrete circuit.Link in the illustration is transformed to (20) model as figure.

4. merge all intermediate nodes (Middle Node), set up the equivalent electric circuit of forming by the node that crosses (Cross Node)

The method of utilizing promise in 4.1 and 4.2 the process to pause (Norton) law of equivalence and merging current source is simplified circuit, obtains the circuit model as figure (21)

Utilize 4.3,4.4 and 4.5 processes to simplify link, form final equivalent electric circuit, shown in figure (22).

To all links, make above process.Merge all Middle Node, obtain the equivalent electric circuit of only forming by Cross Node.Original 65 points are reduced to 17 points, significantly dwindle circuit scale, thereby improve the speed of finding the solution and reduce memory requirements.Shown in figure (23).

5. obtain the sparse matrix G of the circuit equation group of equivalent electric circuit, according to the circuit structure of figure (21) and resistance value wherein, the sparse matrix G of equationof structure group.

6. beginningization simulation makes step counter K=0.Obtain the initial voltage value (this value should equal the initial voltage value of each node associated capacitance) of each node by the PWL oscillogram of each node, make up thus

7. if K＞M, end simulation then,

Otherwise execution following steps.

8. extract the electric current that receives of each unit of the K+1 step moment, and obtain current vector

According to time parameter (K+1) h, extract the current value that receives in this moment of each supply node, then according to the process and the formula (1) (2) (4) (5) (7) (11) of (4.3), (4.4) and (4.5), calculate the equivalent associated current value of each Cross Node, merging obtains current vector then Set up the circuit system of linear equations $G\&CenterDot;{\stackrel{\mathrm{\&rho;}}{V}}_{k+1}={\stackrel{\mathrm{\&rho;}}{I}}_{k+1}$

9. utilize ICCG method solving equation group, obtain the magnitude of voltage of all nodes that cross (Cross Node) among K+1 moment Figure 22

10. recover to find the solution this magnitude of voltage constantly of each Middle Node

After obtaining this voltage constantly of all Cross Node, recover to find the solution this magnitude of voltage constantly of all Middle Node, reach the purpose of analyzing all nodes.

11. output is preserved this moment node voltage to output file.The simulation of this step finishes, and K=K+1 begins next step simulation.

Because the analysis and solution of power-line network and earth cord network is similarly, so the present invention only provides the analysis and solution method of power-line network.The present invention is equally applicable to the analysis and solution of earth cord network.

This method is at CPU 450M, simulation test run on the Sun Solaris V880 work station of internal memory 2G, and all codes utilize the C language compilation, and compiler is GNU gcc 2.95.1 version.

The present invention is satisfying under the prerequisite of precision, not only fast but also utilize internal memory little, is applicable to the more test of monster chip.

Claims (2)

1. based on the method for the ic power network transients analysis and solution of equivalent electric circuit, it contains the step that power line/network of wires is carried out transient analysis based on dc analysis, it is characterized in that, it may further comprise the steps: utilize computer to contain the characteristics of a large amount of chain topological structures at the power line/earth cord network of application-specific integrated circuit (ASIC), the parameters R of the rlc circuit of link intermediate node, L, C and current source equivalence are to this both link ends node, again for the equivalent electric circuit that only constitutes by two end nodes of all links, list system of linear equations, solve this magnitude of voltage of all each end points of link of equivalent electric circuit constantly more in view of the above, obtain in view of the above again in all links by this magnitude of voltage constantly of merge node.

2. the method for the ic power network transients analysis and solution based on equivalent electric circuit according to claim 1, its characteristics are that it contains following steps successively:

The 1st step: computer reads in the message file of circuit, comprises the relational structure between the node in the file; The changing in time of the supply module unit that resistance value between the node, inductance value, inductance initial voltage and current value, capacitance, electric capacity initial voltage and current value and each node are connected utilizes the current waveform that receives that PWL represents, in computer, set up the information of circuit in view of the above, and all intermediate points of mark and joint;

The 2nd step: according to the work period of circuit and the periodicity of needs simulation, computer reads in corresponding time step h and total simulation step number M respectively;

The 3rd step: the electric capacity in the discretization ifq circuit, inductance obtain the circuit of being made up of resistance, current source:

The 3.1st step: capacitor C in the discretization circuit or resistance L, the time step of given simulation is utilized trapezoidal difference formula, and K+1 moment electric capacity disperses and turns to an equivalent resistance With an equivalent current source $\frac{2C}{h}{V}_{c,k}+I_{c,k}$ Model in parallel,

$I_{c,k+1}=\frac{2C}{h}{V}_{c,k+1}-(\frac{2C}{h}{V}_{c,k}+I_{c,k})---\left(1\right),$

V _{C, k}, I _{C, k}, V _{C, k+1}, I _{C, k+1}Represent the voltage and current on K and the K+1 moment electric capacity respectively, its direction is consistent;

The time step of given simulation is utilized trapezoidal difference formula, and K+1 moment inductance disperses and turns to an equivalent resistance With an equivalent current source $\frac{h}{2L}{V}_{L,k}+I_{L,k}$ Model in parallel,

$I_{L,k+1}=\frac{h}{2L}{V}_{L,k+1}+(\frac{h}{2L}{V}_{L,k}+I_{L,k})---\left(2\right),$

V _{L, k}, I _{L, k}, V _{L, k+1}, I _{L, k+1}Represent the voltage and current on k and the k+1 moment inductance respectively, its direction is consistent;

The 3.2nd step:, set up the discretization model of ifq circuit according to the discretization process in (3.1);

The 4th step: merge all intermediate nodes, set up the equivalent electric circuit of forming by the node that crosses:

The 4.1st step: utilize the Norton equivalent law to merge current source with the simplification circuit,

For a link that contains N+1 node, be vertex ticks 1 to N+1 from left to right, (the resistance R between 1＜i＜N) of adjacent node i and i+1 on the link _iThe series circuit of forming with K+1 moment discretization inductance is reduced to by equivalent resistance R _i ^*With equivalent current source el _{I, k+1}The parallel circuits of forming:

$R_i^{*}=2L_i/h+R_i---\left(3\right),$

${\mathrm{el}}_{i,k+1}=(\frac{h}{2L_i}{V}_{L,i,k}+E_{i,k})\&CenterDot;\frac{2L_i/h}{2L_i/h+R_i}---\left(4\right),$

R _i, L _iBe respectively resistance and inductance value between node i and node i+1;

V _{L, i, k}, E _{I, k}Be respectively K L constantly _iOn electric current and magnitude of voltage, direction by the i+1 node to the i node;

El _{I, k+1}Be behind the equivalent-simplification and R _i ^*Equivalent current source in parallel;

The 4.2nd step: the current source over the ground on the merge node i, constantly for node i, receive electric current e to modular unit at K+1 _{I, k+1}With the discretization capacitor C _iThe effect circuit that obtains is merged into by current source ec _{I, k+1}With resistance r _iThe circuit that composes in parallel:

${\mathrm{ec}}_{i,k+1}=e_{i,k+1}-(\frac{2C_i}{h}{V}_{i,k}+I_{i,k})---\left(5\right),$

$r_i=\frac{h}{2C_i}---\left(6\right)$

C _iBe respectively node i associated capacitance value over the ground; V _{I, k}, I _{I, k}Be respectively K constantly magnitude of voltage on the node i and the current value by electric capacity, direction over the ground; Ec _{I, k+1}Expression constantly self receive electric current by i node K+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (5), the sense of current over the ground;

The 4.3rd step: Y type circuit is to the equivalent transformation of pi-network:

Be two end points by three adjacent successively nodes and the Y type conversion of circuits formed of ground with form pi-network;

General, three nodes establishing the Y circuit are x, y, z, wherein node Z ground connection), intermediate node is o, the structure of Y type circuit is:

Between end points x, o: by resistance R _xWith current source I _r, compose in parallel to the x direction from o,

Between end points y, o: by resistance R _yWith current source I _y, from composing in parallel to the y direction for o,

Between end points z, o: by resistance R _zWith current source I _z, compose in parallel to the z direction from o,

The structure of the pi-network that equivalence posterior nodal point x, y and z form is:

Between node x, the y by equivalent resistance R _XyWith equivalent current source I _XyCompose in parallel, wherein:

$R_{\mathrm{xy}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_z},I_{\mathrm{xy}}=\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}---\left(7.1\right),$

Between node x, the z by equivalent resistance R _XzWith equivalent current source I _XzCompose in parallel, wherein:

$R_{\mathrm{xz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_y},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xy}}}---(7.2),$

Between node y, the z by equivalent resistance R _YzWith equivalent current source I _YzCompose in parallel, wherein:

$R_{\mathrm{yz}}=\frac{R_x{R}_y+R_x{R}_z+R_y{R}_z}{R_x},I_{\mathrm{xz}}=\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}---(7.3),$

Therefore, the size of current of inflow node x is:

$E_x=\frac{V_y-V_x}{R_{\mathrm{xy}}}-\frac{V_x}{R_{\mathrm{xz}}}+\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_x{I}_x}{R_{\mathrm{xz}}}\right)---\left(8\right),$

The size of current that flows into node y is:

$E_y=\frac{V_x-V_y}{R_{\mathrm{xy}}}-\frac{V_y}{R_{\mathrm{yz}}}+\left(\frac{R_x{I}_x-R_y{I}_y}{R_{\mathrm{xy}}}\right)-\left(\frac{R_z{I}_z-R_y{I}_y}{R_{\mathrm{yz}}}\right)---\left(9\right),$

The 4.4th step: the equivalent transformation of parallel circuits:

Parallel circuits between two nodes is done to merge the simplification conversion:

$r_{\mathrm{total}}=1/(1/r_{\mathrm{left}}+1/r_{\mathrm{right}})---\left(10\right),$

i _total＝i _left+i _right -(11)，

r _Left, r _Right, i _Left, i _Right, represent the size of two resistance and current source respectively; r _Total, i _TotalThe all-in resistance after expression merges respectively and the size in total current source;

The 4.5th step: merge intermediate node, simplify obtaining final equivalent electric circuit:

Recycle top principle and step, merge the intermediate node of every link, obtain the π type equivalent electric circuit of every link, for a link that contains N+1 node, be labeled as 1 to N+1 from left to right, final π type equivalent circuit structure is as follows:

End points 1 is between N+1: equivalent resistance R _{1, n+1} ^EquivWith equivalent current source I _{1, n+1, k+1} ^Equiv, from N+1 to 1 direction parallel connection; End points 1 is between ground: equivalent resistance R ₁ ^EquivWith equivalent current source I _{1, k+1} ^Equiv, from 1 to the place to parallel connection; End points N+1 is between ground: equivalent resistance R _N+1 ^EquivWith equivalent current source I _{N+1, k+1} ^EquivFrom N+1 to the place to parallel connection;

Circuit reduction is the equivalent electric circuit of the simplification of the node composition that only crosses the most at last;

The 5th step: the nodal voltage equation group of setting up the equivalent electric circuit that obtains by step (4.5) according to Kirchhoff's law

Thereby obtain only relevant sparse coefficient matrix G with circuit structure and resistance;

The 6th step: beginningization simulation, make step counter K=0, obtain the initial voltage value of each node by the PWL oscillogram of each node, this value should equal the initial voltage value of each node associated capacitance, thus structure

The 7th step: if K＞M, then end simulation;

Otherwise execution following steps:

The 8th step: the PWL waveform extracting K+1 step by each node constantly each node supply module unit receive electric current, calculate the K+1 current vector on equation group the right constantly

Bring the system of linear equations that obtains by step (5) into:

This step is received the PWL waveform of electric current according to the supply module unit of each node, extracts this their current value size constantly, utilizes then Merge the size that obtains equivalent current by electric capacity, inductance discretization then through equivalent transformation according to formula (1) (2) (4) (5) (7) (11), finally obtain each this equivalence constantly of node that crosses and receive electric current, constitute vector

The 9th step: with existing method solving equation group

Obtain cross the constantly magnitude of voltage vector of node of K+1

The 10th step: recover to find the solution this magnitude of voltage constantly of each intermediate node:

$E_{1,k+1}=\frac{V_{n+1,k+1}-V_{1,k+1}}{R_{1,n+1}^{\mathrm{equiv}}}+I_{1,n+1,k+1}^{\mathrm{equiv}}-I_{1,k+1}^{\mathrm{equiv}}-\frac{V_{1,k+1}}{R_1^{\mathrm{equiv}}},$

V _{1, k+1}, V _{N+1, k+1}Be the K+1 magnitude of voltage of two joints constantly, then by node i from 2 to N, obtain the K+1 magnitude of voltage constantly of these all intermediate nodes of link:

$V_{i,k+1}=V_{i-1,k+1}+R_{i-1}^{*}(E_{i-1,k+1}-{\mathrm{el}}_{i-1,k+1}),$

$E_{i,k+1}=E_{i-1,k+1}+\frac{V_{i,k+1}}{r_i}+{\mathrm{ec}}_{i,k+1},$

V _{I, k+1}Expression i node is at the K+1 voltage in step, i ∈ [1, n+1]; R _i ^*Resistance between expression i node and node i+1, $R_i^{*}=2L_i/h+R_i;$ r _iThe equivalent resistance that expression is obtained by electric capacity i discretization, r _i=h/2C _iEl _{I, k+1}The equivalent current that expression obtains after by inductance i discretization, the current value that obtains through resulting electric current discretization after the Norton equivalent conversion is tried to achieve by formula (4) again, direction by node i+1 to node i;

Ec _{I, k+1}Expression constantly self receive electric current by i node K+1 and merge by the equivalent current that the corresponding capacitance discretization obtains after total current, calculate according to formula (6), the sense of current by node i to ground;

E _{I, k+1}Expression K+1 step flows into the current value of i node, direction by node i+1 to node i;

The 11st step: the magnitude of voltage of K+1 all nodes is constantly preserved in output, puts K=K+1, forwards step (7) to, carries out next step simulation process.

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