CN203631540U

CN203631540U - Testing structure

Info

Publication number: CN203631540U
Application number: CN201320804311.4U
Authority: CN
Inventors: 王喆
Original assignee: Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Beijing Corp
Priority date: 2013-12-09
Filing date: 2013-12-09
Publication date: 2014-06-04
Anticipated expiration: 2023-12-09

Abstract

The utility model provides a testing structure used for monitoring performance stability of a semiconductor chip. The testing structure comprises multiple testing units each of which includes a PMOS, a NMOS in parallel with the PMOS and spaced apart from the PMOS, a common gate electrode formed above the PMOS and NMOS, an N-type substrate under the NMOS, and multiple through hole connecting lines on the NMOS, PMOS, and the N-type substrate. The NMOS comprises a pre-doping area with a predetermined width. The testing unit comprises the NMOS, the PMOS, and the common gate. Therefore, after the testing units are formed, whether the predetermined width of the NMOS has a certain influence on the testing structure can be detected by performing performance detection on the testing structure. Thus, it can be monitored whether the predetermined width of the NMOS has influence on the stability of the semiconductor chip.

Description

Test structure

Technical field

The utility model relates to field of semiconductor manufacture, relates in particular to a kind of mechanism for testing.

Background technology

After semiconductor chip manufacture completes, conventionally need to carry out corresponding performance test to semiconductor chip, understand the problem existing in production technology, and targetedly production technology is optimized.

In prior art, after completing, semiconductor chip manufacture there will be abnormal conditions.When semiconductor chip being carried out to built-in self-test (Built In Self Test, BIST) time, when voltage is in normal voltage during in normal range (NR) (as 1.2V time), the result that semiconductor die testing obtains is for normal, for example, when voltage is during lower than normal voltage (while being 0.9-0.8V), the result that test obtains is for there will be extremely,, semiconductor chip cannot normally carry out work under the larger scope of voltage fluctuation, also shows that the stability of semiconductor chip is not strong.

But, the problems referred to above cannot can show in acceptance test (WAT) at wafer, also cannot detect by defects detection etc. in process of production, can only carry out Performance Detection to it after semiconductor chip fabrication completes time, could find, now problem discover very lags behind, and is unfavorable for batch production.

Utility model content

The purpose of this utility model is to provide a kind of test structure, for monitoring the stability of semiconductor chip.

To achieve these goals, the utility model proposes a kind of test structure, for monitoring the stability of semiconductor chip, described test structure comprises multiple test cells, described test cell comprises PMOS, NMOS, public grid, N-type substrate and multiple through hole line, wherein, described PMOS is parallel with NMOS and keep a determining deviation, described public grid is formed on described PMOS and NMOS, described NMOS is positioned on described N-type substrate, described through hole line lays respectively at described NMOS, on PMOS and N-type substrate, described NMOS comprises a pre-doped region, described pre-doped region has preset width.

Further, the number scope of described test cell is 1～100.

Further, the preset width of the pre-doped region in each test cell is all different.

Further, the preset width of described pre-doped region is respectively S-6 σ～S+6 σ, and described S is preset width in actual production, and σ is the mean square deviation of preset width in actual production.

Further, described through hole line comprises NMOS through hole line, PMOS through hole line and N-type substrate through vias line, described NMOS through hole line is positioned on described NMOS, and described PMOS through hole line is positioned on described PMOS, and described N-type substrate through vias line is positioned on described N-type substrate.

Further, described NMOS through hole line is two, lays respectively at source electrode, the drain electrode two ends of described NMOS.

Further, described PMOS through hole line is two, lays respectively at source electrode, the drain electrode two ends of described PMOS.

Further, use metal interconnecting wires to link together the through hole line that is positioned at described NMOS and pmos source.

Further, use metal interconnecting wires to link together the through hole line that is positioned at described PMOS drain electrode.

Further, described N-type substrate through vias line is used to metal interconnecting wires downlink connection together.

Further, described test structure also comprises P type substrate, and described P type substrate surrounds described test cell.

Further, on described P type substrate, be formed with multiple through hole lines.

Further, in described test structure, being formed with dielectric layer isolates.

Further, described test cell is inverter.

Compared with prior art, the beneficial effects of the utility model are mainly reflected in: test cell comprises NMOS, PMOS and public grid, whether the pre-doping width that just can detect described NMOS by test structure being carried out to Performance Detection after test cell forms can cause certain influence to test structure, thereby whether the pre-doping width of monitoring out described NMOS has impact to semiconductor chip stability.

Accompanying drawing explanation

Fig. 1 is structural representation when NMOS is adulterated in advance in explained hereafter;

Fig. 2 is the vertical view of test structure in the utility model one embodiment;

Fig. 3 is the circuit diagram of test structure in the utility model one embodiment.

Embodiment

Below in conjunction with schematic diagram, test structure of the present utility model is described in more detail, wherein represent preferred embodiment of the present utility model, should be appreciated that those skilled in the art can revise the utility model described here, and still realize advantageous effects of the present utility model.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as to restriction of the present utility model.

For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the utility model chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.

In the following passage, with way of example, the utility model is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.

Mentioned as background technology, in prior art, after completing, semiconductor chip manufacture there will be the situation of less stable, through inventor's experiment reasoning, the reason that causes semiconductor chip less stable is when NMOS is adulterated in advance, electrons in NMOS diffuses in PMOS, causes the hole in PMOS to be reduced.

Detailed, please refer to Fig. 1, Fig. 1 is structural representation when NMOS is adulterated in advance in explained hereafter, wherein, in Semiconductor substrate 10, be formed with nmos area 21 and PMOS district 22, in the time being adulterated in advance in nmos area 21, conventionally can above described PMOS district 22, form photoresistance 30, so that described PMOS district 22 is blocked, but because technique exists certain deviation, can cause the width that described photoresistance 30 exposes to be increased to abnormal width W 2 by normal width W1, and then after causing pre-doping, the pre-width adulterating is increased to abnormal width L2 by normal width L1, , the electronics of nmos area 21 easily diffuses in PMOS district 22, reduce the number of cavities in PMOS district 22, and then cause the semiconductor core tablet stability forming to reduce.

But in prior art, but cannot monitor in time such problem, in view of this, the present embodiment has proposed a kind of test structure, for monitoring the stability of semiconductor chip, please refer to Fig. 2, described test structure comprises multiple test cells, described test cell comprises PMOS120, NMOS110, public grid 200, N-type substrate 410 and multiple through hole line, wherein, described PMOS120 is parallel with NMOS110 and keep a determining deviation, described public grid 200 is formed on described PMOS120 and NMOS110, described NMOS110 is positioned on described N-type substrate 410, described through hole line lays respectively at described NMOS110, on PMOS120 and N-type substrate 410, described NMOS110 comprises a pre-doped region, described pre-doped region has preset width S.

In the present embodiment, described test structure also comprises P type substrate 420, described P type substrate 420 surrounds described test cell, on described P type substrate 420, be also formed with multiple through hole lines, in described test structure, be formed with dielectric layer and isolate (not shown), the number scope of described test cell is 1～100, for example 5 (as Digital IDs in Fig. 2), wherein, the preset width S of the pre-doped region in each test cell is all different, for the preset width S that better the understands pre-doped region impact on semiconductor chip, therefore can select to adopt the mode of different preset width S, be how many to the maximum to understand the preset width S of pre-doped region.In the present embodiment, the preset width S of described pre-doped region is respectively S-6 σ～S+6 σ, for example between connected preset width S, differ 1 σ, the preset width S that can be defined as No. 1 test cell is S-2 σ, the preset width S of No. 2 test cells is S-1 σ, the preset width S of No. 3 test cells is the actual preset width S of being, the preset width S of No. 4 test cells is S+1 σ, the preset width S of No. 5 test cells is S+2 σ, wherein, described S is preset width in actual production, and described σ is the mean square deviation of preset width S in actual production.

In other embodiment of the present embodiment, between adjacent described preset width S, can differ 0.5 σ, add an actual described preset width S, need altogether 25 test cells.Can predict, can select the difference between different preset width S according to different needs.

In the present embodiment, described through hole line comprises NMOS through hole line, PMOS through hole line and N-type substrate through vias line, described NMOS through hole line is 2, be respectively the nmos source through hole line 340 of the source terminal that is positioned at described NMOS110 and be positioned at the NMOS drain electrode through hole line 330 of the drain electrode end of described NMOS110, described PMOS through hole line is 2, be respectively the pmos source through hole line 320 of the source terminal that is positioned at described PMOS120 and be positioned at the PMOS drain electrode through hole line 310 of the drain electrode end of described PMOS120, described N-type substrate through vias line 350 is positioned on described N-type substrate 410.

In the present embodiment, use metal interconnecting wires to link together described nmos source through hole line 340 and pmos source through hole line 320, as output Output, use metal interconnecting wires to link together described PMOS drain electrode through hole line 310, be used for connecing voltage vcc, again described N-type substrate through vias line 350 is used to metal interconnecting wires downlink connection together, and ground connection.

Please refer to Fig. 2 and Fig. 3, public grid in Fig. 2 is the Common Gate in Fig. 3, in the time that described test structure is tested, Common Gate is for connecing the test voltage of certain interval range, and Vcc is connect to high level, in the time that the test voltage of Common Gate end scans in interval, can measure the magnitude of voltage of output Output, and then can whether have the unsettled problem of performance by this test structure of the section of sentencing.If there is performance instability problem, adopt again microprobe respectively 5 test cells to be detected, find out which test cell existing problem, due to the preset width S of the corresponding pre-doped region of different test cells, so just, can show that semiconductor device has problems under the preset width S of which pre-doping, thereby can find in time technological problems, and technique is optimized accordingly.

In the present embodiment, as shown in Figure 3, described test cell is inverter.

To sum up, in the test structure providing at the utility model embodiment, test cell comprises NMOS, PMOS and public grid, whether the pre-doping width that just can detect described NMOS by test structure being carried out to Performance Detection after test cell forms can cause certain influence to test structure, thereby whether the pre-doping width of monitoring out described NMOS has impact to semiconductor chip stability.

Above are only preferred embodiment of the present utility model, the utility model is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of the technical solution of the utility model; the technical scheme that the utility model is disclosed and technology contents make any type of variations such as replacement or modification that are equal to; all belong to the content that does not depart from the technical solution of the utility model, within still belonging to protection range of the present utility model.

Claims

1. a test structure, for monitoring the stability of semiconductor chip, it is characterized in that, described test structure comprises multiple test cells, described test cell comprises PMOS, NMOS, public grid, N-type substrate and multiple through hole line, wherein, described PMOS is parallel with NMOS and keep a determining deviation, described public grid is formed on described PMOS and NMOS, described NMOS is positioned on described N-type substrate, described through hole line lays respectively at described NMOS, on PMOS and N-type substrate, described NMOS comprises a pre-doped region, described pre-doped region has preset width.

2. test structure as claimed in claim 1, is characterized in that, the number scope of described test cell is 1～100.

3. test structure as claimed in claim 2, is characterized in that, the preset width of the pre-doped region in each test cell is all different.

4. test structure as claimed in claim 2, is characterized in that, the preset width of described pre-doped region is respectively S-6 σ～S+6 σ, and described S is preset width in actual production, and σ is the mean square deviation of preset width in actual production.

5. test structure as claimed in claim 2, it is characterized in that, described through hole line comprises NMOS through hole line, PMOS through hole line and N-type substrate through vias line, described NMOS through hole line is positioned on described NMOS, described PMOS through hole line is positioned on described PMOS, and described N-type substrate through vias line is positioned on described N-type substrate.

6. test structure as claimed in claim 5, is characterized in that, described NMOS through hole line is two, lays respectively at source electrode, the drain electrode two ends of described NMOS.

7. test structure as claimed in claim 6, is characterized in that, described PMOS through hole line is two, lays respectively at source electrode, the drain electrode two ends of described PMOS.

8. test structure as claimed in claim 7, is characterized in that, uses metal interconnecting wires to link together the through hole line that is positioned at described NMOS and pmos source.

9. test structure as claimed in claim 5, is characterized in that, uses metal interconnecting wires to link together the through hole line that is positioned at described PMOS drain electrode.

10. test structure as claimed in claim 5, is characterized in that, described N-type substrate through vias line is used to metal interconnecting wires downlink connection together.

11. test structures as claimed in claim 1, is characterized in that, described test structure also comprises P type substrate, and described P type substrate surrounds described test cell.

12. test structures as claimed in claim 11, is characterized in that, on described P type substrate, are formed with multiple through hole lines.

13. test structures as claimed in claim 1, is characterized in that, be formed with dielectric layer and isolate in described test structure.

14. test structures as claimed in claim 1, is characterized in that, described test cell is inverter.