CN203644760U - Test structure - Google Patents
Test structure Download PDFInfo
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- CN203644760U CN203644760U CN201320878955.8U CN201320878955U CN203644760U CN 203644760 U CN203644760 U CN 203644760U CN 201320878955 U CN201320878955 U CN 201320878955U CN 203644760 U CN203644760 U CN 203644760U
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- independent
- public
- hole
- size
- test structure
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Abstract
The utility model provides a test structure which comprises a number of annular polysilicons, a number of independent through hole connecting wires which are formed in the annular polysilicons and a number of public through hole connecting wires. Different independent through hole connecting wires and public through hole connecting wires have different sizes. The test structure comprises the independent through hole connecting wires and public through holes, wherein the independent through hole connecting wires and the public through holes have different sizes. Due to the fact that the independent through hole connecting wires and the public through holes have different sizes, the distances from the through hole connecting wires to the annular polysilicons are different from the distances from the public through holes to the annular polysilicons, and whether the phenomenon of power leakage exists between the independent through hole connecting wires to the annular polysilicons and between the public through holes to the annular polysilicons can be monitored, wherein the independent through hole connecting wires and the public through holes have different sizes.
Description
Technical field
The utility model relates to field of semiconductor manufacture, relates in particular to a kind of test structure.
Background technology
After semiconductor chip manufacture completes, conventionally need to carry out corresponding performance test to semiconductor chip, understand the problem existing in production technology, and targetedly production technology is optimized.
In prior art, after completing, semiconductor chip manufacture there will be abnormal conditions.In the time semiconductor chip being carried out to built-in self-test (Built In Self Test, BIST), the result that semiconductor die testing obtains often there will be extremely, and test typically uses the semiconductor chip of producing with a collection of light shield extremely.
But, the problems referred to above cannot can show in acceptance test (WAT) at wafer, also cannot detect by defects detection etc. in process of production, can only carry out Performance Detection to it after semiconductor chip fabrication completes time, could find, now problem discover very lags behind, and is unfavorable for batch production.
Utility model content
Whether the purpose of this utility model is to provide a kind of test structure, can fast detecting go out semiconductor chip and exist extremely, saves detection time, increases work efficiency.
To achieve these goals, the utility model proposes a kind of test structure, described test structure comprises: multiple annular polysilicons, be formed at multiple independent through-hole lines and multiple public through hole line in annular polysilicon ring, wherein, different independent through-hole lines and public through hole line all have different size.
Further, the size CD of described independent through-hole line
t1scope is CD
1-3 σ
1~CD
1+ 3 σ
1, wherein, CD
1for the size of process stipulation independent through-hole line, σ
1for all independent through-hole connection line size CD in actual production
1mean square deviation.
Further, described independent through-hole line is according to size CD
t1arrange from small to large.
Further, the size CD of described public through hole line
t2scope is CD
2-3 σ
2~CD
2+ 3 σ
2, wherein, CD
2for the size of the public through hole line of process stipulation, σ
2for all public through hole connection line size CD in actual production
2mean square deviation.
Further, described public through hole line is according to size CD
t2arrange from small to large.
Further, the annular polysilicon in the described annular polysilicon side of being.
Further, the number of described annular polysilicon is 2~8.
Further, in described test structure, being formed with dielectric layer isolates.
Compared with prior art, the beneficial effects of the utility model are mainly reflected in: test structure comprises independent through-hole line and the public through hole of different size, because the size of independent through-hole line and public through hole is all not identical, cause independent through-hole line and public through hole also different to the spacing of annular polysilicon, thereby whether independent through-hole line and the public through hole that can monitor different size there is leaky between annular polysilicon.
Accompanying drawing explanation
Fig. 1 is the structure cutaway view of semiconductor device;
Fig. 2 is the vertical view of the test structure in the utility model embodiment mono-;
Fig. 3 is the vertical view of the test structure in the utility model embodiment bis-.
Embodiment
Below in conjunction with schematic diagram, test structure of the present utility model is described in more detail, wherein represent preferred embodiment of the present utility model, should be appreciated that those skilled in the art can revise the utility model described here, and still realize advantageous effects of the present utility model.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as to restriction of the present utility model.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the utility model chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the utility model is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
Please refer to Fig. 1, mentioned as background technology, after completing, semiconductor chip manufacture in the prior art there will be abnormal conditions, research through inventor is found, the reason that causes abnormal conditions to occur be due to be formed at polysilicon 20 in Semiconductor substrate 10 and independent through-hole line 31 and and public through hole line 32 between spacing change, simultaneously, cause spacing between them to occur to change causing occurring leaky because deviation has occurred for aiming between independent through-hole line 31 and public through hole line 32 and described polysilicon 20, thereby make the semiconductor chip forming exist abnormal.
Concrete, described independent through-hole line 31 should be positioned at two polysilicon 20 midpoint, be that described independent through-hole line 31 is fixing to the interval S 1 of described polysilicon 20, described public through hole line 32 also should be fixed near the interval S 2 of polysilicon 20, but, because technique exists deviation, make the independent through-hole line 31 of formation and the size of public through hole line 32 have certain deviation, and then cause S1 and S2 to change, even make to exist and leak electricity between described independent through-hole line 31 and public through hole line 32 and described polysilicon 20, this class problem is more remarkable along with the lasting reduction of semiconductor feature sizes.And in prior art, whether can only detect separately aiming between independent through-hole line 31 and described public through hole line 32 and described polysilicon 20 goes wrong, or whether the size that can only detect separately independent through-hole line 31 and described public through hole line 32 goes wrong, do not have a kind of test structure and can all detect problems.
In view of this, propose in the present embodiment a kind of test structure, can monitor the phenomenon that whether has electric leakage between the independent through-hole line of different size and public through hole line and polysilicon.
Embodiment mono-
Please refer to Fig. 2, the test structure proposing in the present embodiment comprises multiple annular polysilicons 40, be formed at multiple independent through-hole lines 31 and multiple public through hole line 32 in annular polysilicon ring 40, wherein, different independent through-hole lines 31 and public through hole line 32 all have different size.
In the present embodiment, the size CD of described independent through-hole line 31
t1scope is CD
1-3 σ
1~CD
1+ 3 σ
1, wherein, CD
1for the size of process stipulation independent through-hole line 31, σ
1for all independent through-hole line 31 size CD in actual production
1mean square deviation, described independent through-hole line 31 is according to size CD
t1arrange from small to large, adopt as shown in Figure 2 ascending arranged clockwise, or adopt arrangement counterclockwise.
In the present embodiment, the size CD of described public through hole line 32
t2scope is CD
2-3 σ
2~CD
2+ 3 σ
2, wherein, CD
2for the size of the public through hole line 32 of process stipulation, σ
2for all public through hole line 32 size CD in actual production
2mean square deviation, identical, described public through hole line 32 is according to size CD
t2arrange from small to large, as shown in Figure 2.
As mentioned above, due to the size CD of described independent through-hole line 31
t1difference, makes described independent through-hole line 31 also not identical to the interval S 1 of described annular polysilicon 40, the size CD of described public through hole line 32
t2difference, makes described public through hole line 32 also not identical to the interval S 2 of described annular polysilicon 40, thereby can monitor out different spacing S1 and can S2 cause leaky.
In the present embodiment, the described annular polysilicon 40 annular polysilicon compositions in the side of being, the number of described annular polysilicon 40 is 2~8, in the present embodiment, only illustrate 4, as shown in Figure 2, two annular polysilicons 40 are interior therein puts respectively 4 independent through-hole lines 31, puts respectively 3 public through hole lines 32 two other annular polysilicon 40 is interior.
Embodiment bis-
In the present embodiment, the test structure general plotting proposing is identical with embodiment mono-, difference with described annular polysilicon 40 be larger two, as shown in Figure 3, so described independent through-hole line 31 is arranged in described annular polysilicon 40 according to the ascending order of size, because described annular polysilicon 40 is larger, therefore can arranges more independent through-hole line 31, meanwhile, described public through hole line 32 can be placed on respectively four angles of described annular polysilicon 40.Because the number of described independent through-hole line 31 is more, the test structure that therefore adopts the present embodiment to propose can improve the precision of test.
Meanwhile, the test structure that the present embodiment proposes can also detect the phenomenon whether independent through-hole line 31 there will be fracture, and this is because the size range of described independent through-hole line 31 is wider.
After the test structure that uses the present embodiment to propose, there is electric leakage if find, can connect two independent metal interconnecting wires, respectively described independent through-hole line 31 and public through hole line 32 are detected, to judge that problem has appearred in which kind of through hole line, is convenient to carry out corresponding problem solution.
To sum up, in the test structure providing at the utility model embodiment, test structure comprises independent through-hole line and the public through hole of different size, because the size of independent through-hole line and public through hole is all not identical, cause independent through-hole line and public through hole also different to the spacing of annular polysilicon, thereby whether independent through-hole line and the public through hole that can monitor different size there is leaky between annular polysilicon.
Above are only preferred embodiment of the present utility model, the utility model is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of the technical solution of the utility model; the technical scheme that the utility model is disclosed and technology contents make any type of variations such as replacement or modification that are equal to; all belong to the content that does not depart from the technical solution of the utility model, within still belonging to protection range of the present utility model.
Claims (8)
1. a test structure, it is characterized in that, described test structure comprises: multiple annular polysilicons, are formed at multiple independent through-hole lines and multiple public through hole line in annular polysilicon ring, wherein, different independent through-hole lines and public through hole line all have different size.
2. test structure as claimed in claim 1, is characterized in that, the size CD of described independent through-hole line
t1scope is CD
1-3 σ
1~CD
1+ 3 σ
1, wherein, CD
1for the size of process stipulation independent through-hole line, σ
1for all independent through-hole connection line size CD in actual production
1mean square deviation.
3. test structure as claimed in claim 2, is characterized in that, described independent through-hole line is according to size CD
t1arrange from small to large.
4. test structure as claimed in claim 1, is characterized in that, the size CD of described public through hole line
t2scope is CD
2-3 σ
2~CD
2+ 3 σ
2, wherein, CD
2for the size of the public through hole line of process stipulation, σ
2for all public through hole connection line size CD in actual production
2mean square deviation.
5. test structure as claimed in claim 4, is characterized in that, described public through hole line is according to size CD
t2arrange from small to large.
6. test structure as claimed in claim 1, is characterized in that, the annular polysilicon in the described annular polysilicon side of being.
7. test structure as claimed in claim 6, is characterized in that, the number of described annular polysilicon is 2~8.
8. test structure as claimed in claim 1, is characterized in that, is formed with dielectric layer and isolates in described test structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201320878955.8U CN203644760U (en) | 2013-12-27 | 2013-12-27 | Test structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201320878955.8U CN203644760U (en) | 2013-12-27 | 2013-12-27 | Test structure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203644760U true CN203644760U (en) | 2014-06-11 |
Family
ID=50875985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201320878955.8U Expired - Fee Related CN203644760U (en) | 2013-12-27 | 2013-12-27 | Test structure |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203644760U (en) |
-
2013
- 2013-12-27 CN CN201320878955.8U patent/CN203644760U/en not_active Expired - Fee Related
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Legal Events
Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140611 Termination date: 20191227 |