CN103915361A - Method for detecting chip defects - Google Patents
Method for detecting chip defects Download PDFInfo
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- CN103915361A CN103915361A CN201410138986.9A CN201410138986A CN103915361A CN 103915361 A CN103915361 A CN 103915361A CN 201410138986 A CN201410138986 A CN 201410138986A CN 103915361 A CN103915361 A CN 103915361A
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- chip
- defect
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- layout
- detection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention provides a method for detecting chip defects. The method includes the steps that a chip layout is divided into a plurality of layout unit graphs, a wafer which is provided with a plurality of chips and is to be detected is provided, the wafer to be detected is scanned, physical unit graphs of the chips are extracted according to the layout unit graphs, and the physical unit graphs and the corresponding layout unit graphs are compared to obtain a detection result. According to the method for detecting the chip defects, the chip layout is divided into a plurality of layout unit graphs, the layout unit graphs serve as references of chip defect detection, the situation that the defects cannot be detected due to the fact that the same defect exists between the adjacent chips is avoided, and accordingly the success rate of chip defect detection is improved.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly a kind of detection method of chip defect.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, larger data storage amount and more function, and semiconductor chip is to high integration future development more.The integrated level of semiconductor chip is higher, it is complicated all the more that the process of its manufacture also becomes, advanced integrated circuit fabrication process generally all comprises a hundreds of processing step at present, therefore, one of them step goes wrong and will cause the problem of whole semiconductor chip, its performance that shows as integrated circuit fails to reach designing requirement, the serious inefficacy that also may cause whole chip.
So the problem existing find product manufacture in time in the manufacture process of integrated circuit in just seems particularly important.In order to detect in time in process of production defect, industry generally all adopts highly sensitive optical detection apparatus to detect the defect of product.
The basic process of utilizing optical detection apparatus to carry out defects detection to product is as follows: first, obtain the optical imagery of detected product by light microscope; Then, described optical imagery is transformed, become the data image being represented by the bright dull gray of difference rank; Then, the data image of adjacent chips on product is contrasted, obtain testing result.
Visible, the detection method of prior art is according to the otherness between chip adjacent in product, finds defect.But the method can not detect the chip defect on product completely in the very high product of integrated level, and its recall rate is poor.The poor reason of recall rate is, whether defect is according to there are differences and judge between adjacent chip, if adjacent chip has identical defect, owing to there is no difference between adjacent chip, so cannot detect defect.
For example, the photoresistance deformation defect often occurring in the manufacture process of integrated circuit.The reason that causes photoresistance deformation defect is that some special areas of chip there will be light reflection when photoresistance is developed, makes photoresistance figure occur part distortion, causes occurring photoresistance deformation defect in circuit structure.Please refer to Fig. 1, its for according to the ideal circuit of layout design with occur photoresistance deformation defect side circuit contrast schematic diagram.As shown in Figure 1, there is no photoresistance deformation defect B according to the ideal circuit of layout design, but can form photoresistance deformation defect B in actual production process chips, and described photoresistance deformation defect B can repeat, comprise that adjacent position repeats.Cannot detect the photoresistance deformation defect repeating adjacent position according to existing detection method.
Therefore, how to solve the low problem of existing detection method recall rate and become the current technical problem of needing solution badly.
Summary of the invention
The object of the present invention is to provide a kind of detection method of chip defect, to solve the low problem of detection method recall rate of prior art chips defect.
For solving the problems of the technologies described above, the invention provides a kind of detection method of chip defect, the detection method of described chip defect comprises:
Chip layout is divided into multiple territory unit figures;
One wafer to be measured that is prepared with multiple chips is provided;
Described wafer to be measured is scanned and is extracted respectively according to described multiple territory unit figures the physical location figure of described multiple chips;
Described physical location figure and corresponding territory unit figure are compared, to obtain testing result.
Preferably, in the detection method of described chip defect, described chip layout is divided respectively according to horizontal and vertical.
Preferably, in the detection method of described chip defect, described chip layout all carries out equidistant division horizontal and vertical.
Preferably, in the detection method of described chip defect, described chip layout at horizontal and vertical equal portions all between 10 to 100.
Preferably, in the detection method of described chip defect, provide one be prepared with the wafer to be measured of multiple chips before, after chip layout being divided into multiple territory unit figures, also comprising described multiple territory unit figures all imported to defect detection equipment.
Preferably, in the detection method of described chip defect, described defect detection equipment is optical detection apparatus.
Preferably, in the detection method of described chip defect, the detection method of described chip defect is for detection of photoresistance deformation defect.
In the detection method of chip defect provided by the invention, by the benchmark that chip layout is divided into multiple territory unit figures and detects using described territory unit figure as chip defect, avoid because detecting because thering is identical defect between adjacent chip, thereby improved the success rate that chip defect detects.
Accompanying drawing explanation
Fig. 1 be according to the ideal circuit of layout design with occur photoresistance deformation defect side circuit contrast schematic diagram;
Fig. 2 is the flow chart of the detection method of the chip defect of the embodiment of the present invention;
Fig. 3 is the structural representation that the chip layout of the embodiment of the present invention is divided into multiple territory unit figures.
Embodiment
The detection method of chip defect the present invention being proposed below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, the flow chart of the detection method of its chip defect that is the embodiment of the present invention.As shown in Figure 1, the detection method of described chip defect comprises:
Step S10: chip layout 10 is divided into multiple territory unit figures 11;
Step S11 a: wafer to be measured that is prepared with multiple chips is provided;
Step S12: the physical location figure that described wafer to be measured is scanned and extracted respectively according to described multiple territory unit figures 11 described multiple chips;
Step S13: described physical location figure and corresponding territory unit figure 11 are compared, to obtain testing result.
Concrete, before making semiconductor chip, meeting design chips domain 10 is to guarantee semiconductor chip success volume production and to obtain high yield conventionally, and described chip layout 10 is ideal structures of semiconductor chip.
First, described chip layout 10 is divided into multiple territory unit figures 11.As shown in Figure 3, respectively to the dividing of described chip layout 10, form m × n territory unit figure 11 according to laterally (directions X) and longitudinal (Y-direction), wherein m is the first-class dosis refracta of directions X, and n is the first-class dosis refracta of Y-direction.The numerical value of m and n is larger, divide thinner, divide more carefully mean that the resolution of Defect Scanning is higher.Preferably, described chip layout 10 is at the equal portions of directions X and Y-direction all between 10 to 100, and the number range that number range of m is 10～100, n is also 10～100.
Preferably, described chip layout 10 is all divided according to equidistant at directions X and Y-direction.The multiple territory unit figures 11 that form according to equidistant division, its shape and size are identical.Wherein, the spacing that described chip layout 10 is divided on directions X can be the same or different with the spacing of dividing in the Y direction, if the spacing of dividing on directions X is identical with the spacing of dividing in the Y direction, described territory unit figure 11 is square, if the spacing of dividing on directions X is different from the spacing of dividing in the Y direction, described territory unit figure 11 is rectangle.
Preferably, the distance that described directions X is divided with Y-direction is identical.For example, can be using the cell of 20 μ m × 20 μ m sizes in described chip layout 10 as a territory unit figure 11.
Described chip layout 10 generally includes a series of figure, the circuit structure of respectively corresponding each production phase, the i.e. ideal structure of each layer of circuit of semiconductor chip.The Ideal graph of each layer of circuit of semiconductor chip is all divided into multiple territory unit figures 11, after this all territory unit figures 11 carried out to digitlization conversion and import in the defects detection program of optical detection apparatus, and in described defects detection program, described territory unit figure 11 is defined as to normative reference, whether meet designing requirement with the chip structure of confirming to make.
Then, provide a wafer to be measured that is prepared with multiple chips, described wafer to be measured is selected and carries out defect test.
Then, by described optical detection apparatus, each chip of described wafer to be measured is scanned.In this process, described optical detection apparatus automatically extracts the physical structure matching on each chip according to the reference pattern of defects detection program definition, obtain corresponding physical location figure.Thus, each chip has all obtained m × n physical location figure by scanning, and described physical location figure and described territory unit figure 11 are one to one.
Preferably, adopt and there is highly sensitive optical detection apparatus described wafer to be measured is scanned.
Afterwards, described physical location figure is carried out to digitlization conversion and obtain physical location graph data, the digitized image that the different light and shade GTGs of simultaneously described physical location graphics being served as reasons represent.
Finally, described physical location figure and corresponding territory unit figure 11 are contrasted, to obtain testing result.If described physical location figure does not have difference with corresponding territory unit figure 11, think that described physical location figure is normal, there is no defect; If described physical location figure there are differences with corresponding territory unit figure 11, think that described physical location figure is abnormal, find defect.
In the detection method of the chip defect providing in the embodiment of the present invention, the various piece of chip is compared with desirable circuitous pattern respectively, therefore detects more accurate.Even if adjacent position or repetitive structure exist identical defect, also there will not be undetected.The detection method of described chip defect is applicable to the detection of photoresistance deformation defect.
To sum up, in the detection method of the chip defect providing in the embodiment of the present invention, chip layout is divided into multiple territory unit figures, when chip is carried out to defects detection take described territory unit figure as benchmark, rather than judging whether to exist defect with the otherness between adjacent chip, the accuracy therefore detecting is higher.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (7)
1. a detection method for chip defect, is characterized in that, comprising:
Chip layout is divided into multiple territory unit figures;
One wafer to be measured that is prepared with multiple chips is provided;
Described wafer to be measured is scanned and is extracted respectively according to described multiple territory unit figures the physical location figure of described multiple chips;
Described physical location figure and corresponding territory unit figure are compared, to obtain testing result.
2. the detection method of chip defect as claimed in claim 1, is characterized in that, described chip layout is divided respectively according to horizontal and vertical.
3. the detection method of chip defect as claimed in claim 2, is characterized in that, described chip layout all carries out equidistant division horizontal and vertical.
4. the detection method of chip defect as claimed in claim 3, is characterized in that, described chip layout at horizontal and vertical equal portions all between 10 to 100.
5. the detection method of chip defect as claimed in claim 1, it is characterized in that, provide one be prepared with the wafer to be measured of multiple chips before, after chip layout being divided into multiple territory unit figures, also comprising described multiple territory unit figures all imported to defect detection equipment.
6. the detection method of chip defect as claimed in claim 5, is characterized in that, described defect detection equipment is optical detection apparatus.
7. the detection method of chip defect as claimed in claim 1, is characterized in that, the detection method of described chip defect is for detection of photoresistance deformation defect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410138986.9A CN103915361A (en) | 2014-04-08 | 2014-04-08 | Method for detecting chip defects |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410138986.9A CN103915361A (en) | 2014-04-08 | 2014-04-08 | Method for detecting chip defects |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104459508A (en) * | 2014-08-13 | 2015-03-25 | 华进半导体封装先导技术研发中心有限公司 | Wafer testing system and method |
| CN108241765A (en) * | 2016-12-26 | 2018-07-03 | 杭州广立微电子有限公司 | A kind of chip transistor testing chip design method |
| CN110690136A (en) * | 2019-10-12 | 2020-01-14 | 上海华力微电子有限公司 | Defect detection method and system |
| CN110836905A (en) * | 2019-11-13 | 2020-02-25 | 上海华力集成电路制造有限公司 | Failure analysis method for automatically identifying physical defects of chip |
| CN110867391A (en) * | 2019-11-13 | 2020-03-06 | 上海华力集成电路制造有限公司 | Defect detection method in chip manufacturing process |
| CN112086373A (en) * | 2019-06-13 | 2020-12-15 | 芯恩（青岛）集成电路有限公司 | Wafer defect detection method |
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| CN1164049A (en) * | 1995-03-22 | 1997-11-05 | 现代电子产业株式会社 | Method for fabricating light exposure mask |
| US20040105578A1 (en) * | 2002-08-21 | 2004-06-03 | Hideo Tsuchiya | Pattern inspection apparatus |
| CN102789999A (en) * | 2012-08-16 | 2012-11-21 | 上海华力微电子有限公司 | Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip |
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2014
- 2014-04-08 CN CN201410138986.9A patent/CN103915361A/en active Pending
Patent Citations (3)
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| CN1164049A (en) * | 1995-03-22 | 1997-11-05 | 现代电子产业株式会社 | Method for fabricating light exposure mask |
| US20040105578A1 (en) * | 2002-08-21 | 2004-06-03 | Hideo Tsuchiya | Pattern inspection apparatus |
| CN102789999A (en) * | 2012-08-16 | 2012-11-21 | 上海华力微电子有限公司 | Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104459508A (en) * | 2014-08-13 | 2015-03-25 | 华进半导体封装先导技术研发中心有限公司 | Wafer testing system and method |
| CN104459508B (en) * | 2014-08-13 | 2018-02-27 | 华进半导体封装先导技术研发中心有限公司 | A kind of wafer test system and crystal round test approach |
| CN108241765A (en) * | 2016-12-26 | 2018-07-03 | 杭州广立微电子有限公司 | A kind of chip transistor testing chip design method |
| CN108241765B (en) * | 2016-12-26 | 2022-12-02 | 杭州广立微电子股份有限公司 | Chip design method for testing chip transistor |
| CN112086373A (en) * | 2019-06-13 | 2020-12-15 | 芯恩（青岛）集成电路有限公司 | Wafer defect detection method |
| CN110690136A (en) * | 2019-10-12 | 2020-01-14 | 上海华力微电子有限公司 | Defect detection method and system |
| CN110836905A (en) * | 2019-11-13 | 2020-02-25 | 上海华力集成电路制造有限公司 | Failure analysis method for automatically identifying physical defects of chip |
| CN110867391A (en) * | 2019-11-13 | 2020-03-06 | 上海华力集成电路制造有限公司 | Defect detection method in chip manufacturing process |
| CN110867391B (en) * | 2019-11-13 | 2022-06-14 | 上海华力集成电路制造有限公司 | Defect detection method in chip manufacturing process |
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Application publication date: 20140709 |