CN103915361A - Method for detecting chip defects - Google Patents

Method for detecting chip defects Download PDF

Info

Publication number
CN103915361A
CN103915361A CN 201410138986 CN201410138986A CN103915361A CN 103915361 A CN103915361 A CN 103915361A CN 201410138986 CN201410138986 CN 201410138986 CN 201410138986 A CN201410138986 A CN 201410138986A CN 103915361 A CN103915361 A CN 103915361A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
chip
layout
method
plurality
detecting
Prior art date
Application number
CN 201410138986
Other languages
Chinese (zh)
Inventor
何理
许向辉
郭贤权
陈超
Original Assignee
上海华力微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

The invention provides a method for detecting chip defects. The method includes the steps that a chip layout is divided into a plurality of layout unit graphs, a wafer which is provided with a plurality of chips and is to be detected is provided, the wafer to be detected is scanned, physical unit graphs of the chips are extracted according to the layout unit graphs, and the physical unit graphs and the corresponding layout unit graphs are compared to obtain a detection result. According to the method for detecting the chip defects, the chip layout is divided into a plurality of layout unit graphs, the layout unit graphs serve as references of chip defect detection, the situation that the defects cannot be detected due to the fact that the same defect exists between the adjacent chips is avoided, and accordingly the success rate of chip defect detection is improved.

Description

芯片缺陷的检测方法 The method of detecting defects in the chip

技术领域 FIELD

[0001] 本发明涉及集成电路制造技术领域,特别涉及一种芯片缺陷的检测方法。 [0001] Technical Field The present invention relates to integrated circuit fabrication and more particularly relates to a method for detecting defects in the chip.

背景技术 Background technique

[0002] 随着半导体制造技术的飞速发展,半导体器件为了达到更快的运算速度、更大的资料存储量以及更多的功能,半导体芯片向更高集成度方向发展。 [0002] With the rapid development of semiconductor manufacturing technology, a semiconductor device in order to achieve faster operating speed, greater data storage, and more functions, a semiconductor chip to a higher degree of integration directions. 半导体芯片的集成度越高,其制造的过程也变得越发复杂,目前先进的集成电路制造工艺一般都包含几百个工艺步骤,因此,其中的一个步骤出现问题就会引起整个半导体芯片的问题,其表现为集成电路的性能未能达到设计要求,严重的还可能导致整个芯片的失效。 The higher integration of the semiconductor chip, the manufacturing process also becomes more complex, advanced integrated circuit manufacturing process generally contains several hundred process steps, and therefore, problems can cause problems throughout the semiconductor chip wherein a step occurs , its performance for the performance of integrated circuits failed to meet the design requirements, can also lead to serious failure of the entire chip.

[0003] 所以,在集成电路的制造过程中及时地发现产品制造工艺中存在的问题就显得尤为重要。 [0003] Therefore, in the fabrication of integrated circuits in a timely manner to find the product manufacturing process problems it is particularly important. 为了在生产过程中及时检出缺陷,业界一般都采用高灵敏度的光学检测设备对产品的缺陷进行检测。 In order to timely detection of defects in the production process, the industry generally have high sensitivity optical detection apparatus to detect defective products.

[0004] 利用光学检测设备对产品进行缺陷检测的基本过程如下:首先,通过光学显微镜获取被检测产品的光学图像;然后,对所述光学图像进行转化,使其成为由不同亮暗灰阶表示的数据图像;接着,对产品上相邻芯片的数据图像进行对比,得到检测结果。 [0004] The use of optical detection equipment to carry out the basic defect detection procedure is as follows: Firstly, the product acquires an optical image is detected by an optical microscope; then, conversion of the optical image, it became a dark gray light represented by a different image data; Next, the image data on the product of adjacent chips are compared to obtain a detection result.

[0005] 可见,现有技术的检测方法是根据产品中相邻的芯片之间的差异性,来发现缺陷的。 [0005] seen, the prior art detection method is based on the difference between adjacent chips in the product, to find defects. 但是该方法在集成度非常高的产品中并不能将产品上的芯片缺陷完全检测出来,其检出率较差。 However, this method is very high degree of integration products can not chipping defects detected in the product completely, the detection rate is poor. 检出率较差的原因在于,缺陷是根据相邻的芯片之间是否存在差异而判断的,若相邻的芯片具有相同的缺陷,由于相邻的芯片之间没有差异,所以无法检出缺陷。 The reason is that poor detection rate, according to whether there is a defect difference between adjacent chips is determined, if the adjacent chip has the same drawbacks, since there is no difference between the adjacent chip, the defect can not be detected .

[0006] 例如,在集成电路的制造过程中经常出现的光阻变形缺陷。 [0006] For example, defects often resist deformation during the manufacturing process of integrated circuits. 引起光阻变形缺陷的原因是对光阻进行显影时芯片的一些特殊区域会出现光线反射,使得光阻图形出现部分变形,导致在电路结构中出现光阻变形缺陷。 Resist deformation causes some special defects to resist developing area of ​​the chip will reflect light, the photoresist pattern portion such that deformation occurs, resulting in deformation of the resist defects in circuit configuration. 请参考图1,其为按照版图设计的理想电路与出现光阻变形缺陷的实际电路的对照示意图。 Referring to FIG. 1, which is a defect in accordance with the actual circuit resist deformation over the circuit layout design and control schematic occur. 如图1所示,按照版图设计的理想电路是没有光阻变形缺陷B的,但是实际生产过程中芯片上会形成光阻变形缺陷B,而且所述光阻变形缺陷B会重复出现,包括相邻位置重复出现。 1, according to the circuit layout design over the no resist deformation defects of B, but formed on the actual production process B chip defects resist deformation, and the deformation of the photoresist defect B will be repeated, including phase o location repeated. 按照现有的检测方法无法检出相邻位置重复出现的光阻变形缺陷。 According to the conventional method for detecting a defect can not be detected resist deformation recurring adjacent positions.

[0007] 因此,如何解决现有的检测方法检出率低的问题成为当前亟需解决的技术问题。 [0007] Therefore, how to solve the problem of the conventional method for detecting the detection rate becomes the current technical problem to be resolved.

发明内容 SUMMARY

[0008] 本发明的目的在于提供一种芯片缺陷的检测方法,以解决现有技术中芯片缺陷的检测方法检出率低的问题。 [0008] The object of the present invention to provide a method for detecting defects of a chip, in order to solve the problems the prior art method for detecting a defect detection rate of the chip.

[0009] 为解决上述技术问题,本发明提供一种芯片缺陷的检测方法,所述芯片缺陷的检测方法包括: [0009] To solve the above problems, the present invention provides a method of detecting a defect chip, the chip defect detection method comprising:

[0010] 将芯片版图划分成多个版图单元图形; [0010] The chip layout into a plurality of cell layout pattern;

[0011] 提供一制备有多个芯片的待测晶圆; [0011] Preparation of providing a plurality of chip wafers to be tested;

[0012] 对所述待测晶圆进行扫描并根据所述多个版图单元图形分别提取所述多个芯片的物理单元图形; [0012] The test wafer and scanning the plurality of physical units respectively extracted from the plurality of graphics chip layout pattern units;

[0013] 将所述物理单元图形与相应的版图单元图形进行比对,以得到检测结果。 [0013] The physical layout of the unit cell pattern corresponding to pattern are aligned to obtain a detection result.

[0014] 优选的,在所述的芯片缺陷的检测方法中,所述芯片版图按照横向和纵向分别进行划分。 [0014] Preferably, in the method of detecting defects in a chip, the chip layout in accordance with horizontal and vertical dividing respectively.

[0015] 优选的,在所述的芯片缺陷的检测方法中,所述芯片版图在横向和纵向均进行等距尚划分。 [0015] Preferably, in the method of detecting defects in a chip, the chip layout are divided still equidistant horizontal and vertical.

[0016] 优选的,在所述的芯片缺陷的检测方法中,所述芯片版图在横向和纵向的等份均在10到100之间。 [0016] Preferably, in the method of detecting defects in a chip, the chip layout in the horizontal and vertical aliquots were between 10 and 100.

[0017] 优选的,在所述的芯片缺陷的检测方法中,在提供一制备有多个芯片的待测晶圆之前,在将芯片版图划分成多个版图单元图形之后,还包括将所述多个版图单元图形均导入缺陷检测设备。 [0017] Preferably, in the method for detecting defects in a chip before providing the preparation of a test wafer with a plurality of chips, after the chip layout pattern into a plurality of unit layout, further comprising a plurality of unit layout pattern defect detecting apparatus are introduced.

[0018] 优选的,在所述的芯片缺陷的检测方法中,所述缺陷检测设备为光学检测设备。 [0018] Preferably, in the method of detecting defects in a chip, the defect detecting apparatus of an optical detection apparatus.

[0019] 优选的,在所述的芯片缺陷的检测方法中,所述芯片缺陷的检测方法用于检测光阻变形缺陷。 [0019] Preferably, in the method of detecting defects in a chip, said chip defect detection method for detecting defects resist deformation.

[0020] 在本发明提供的芯片缺陷的检测方法中,通过将芯片版图划分成多个版图单元图形并以所述版图单元图形作为芯片缺陷检测的基准,避免因相邻的芯片之间因具有相同的缺陷而无法检出,从而提高了芯片缺陷检测的成功率。 [0020] In the detection method of the present invention to provide a defect chip, the chip layout by the layout into a plurality of unit figures and to the reference chip layout pattern as a means of detecting a defect, to avoid having adjacent chip by the same can not be detected defects, thereby improving the success rate of the wafer defect detection.

附图说明 BRIEF DESCRIPTION

[0021] 图1是按照版图设计的理想电路与出现光阻变形缺陷的实际电路的对照示意图; [0021] FIG. 1 is a schematic diagram of a control circuit the actual resist deformation over the defect in accordance with a circuit layout design occur;

[0022] 图2是本发明实施例的芯片缺陷的检测方法的流程图; [0022] FIG 2 is a flowchart of a method of detecting defects in the chip of the present embodiment of the invention;

[0023] 图3是本发明实施例的芯片版图划分成多个版图单元图形的结构示意图。 [0023] FIG. 3 is a schematic structural diagram of a chip layout Example layout into a plurality of unit figures embodiment of the present invention.

具体实施方式 detailed description

[0024] 以下结合附图和具体实施例对本发明提出的芯片缺陷的检测方法作进一步详细说明。 [0024] The following specific examples in conjunction with the accompanying drawings and described in further detail of the detection method of the present invention proposed chip defect. 根据下面说明和权利要求书,本发明的优点和特征将更清楚。 The following description and the appended claims, features and advantages of the present invention will be apparent. 需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。 It should be noted that the drawings are used in a very simplified form and are using a non-precise proportion, only to facilitate, assist clarity purpose of illustrating an embodiment of the present invention.

[0025] 请参考图2,其为本发明实施例的芯片缺陷的检测方法的流程图。 [0025] Please refer to FIG 2, a flowchart of a method of detecting defects in a chip which is an embodiment of the present invention. 如图1所示,所述芯片缺陷的检测方法包括: As shown, the method for detecting a defective chip comprising:

[0026] 步骤SlO:将芯片版图10划分成多个版图单元图形11 ; [0026] Step SlO: the chip layout 10 into a plurality of unit layout pattern 11;

[0027] 步骤Sll:提供一制备有多个芯片的待测晶圆; [0027] Step Sll: preparing a plurality of chips providing a wafer to be tested;

[0028] 步骤S12:对所述待测晶圆进行扫描并根据所述多个版图单元图形11分别提取所述多个芯片的物理单元图形; [0028] Step S12: the test wafer and scanning unit according to the plurality of layout patterns 11 respectively extracts the plurality of physical units graphics chip;

[0029] 步骤S13:将所述物理单元图形与相应的版图单元图形11进行比对,以得到检测结果。 [0029] Step S13: The unit of the physical layout pattern corresponding to the pattern element 11 are aligned to obtain a detection result.

[0030] 具体的,在制作半导体芯片之前通常会设计芯片版图10以保证半导体芯片成功量产并得到高的良率,所述芯片版图10是半导体芯片的理想结构。 [0030] Specifically, before the production of the semiconductor chip 10 is usually designed chip layout of the semiconductor chip to ensure successful production and high yield, the chip layout structure 10 is over the semiconductor chip.

[0031] 首先,将所述芯片版图10划分成多个版图单元图形11。 [0031] First, the layout of the chip 10 into a plurality of pattern units 11 layout. 如图3所示,按照横向(X方向)和纵向(Y方向)分别对所述芯片版图10的进行划分,形成mXn个版图单元图形11,其中m是X方向上等分数量,η是Y方向上等分数量。 3, in accordance with the horizontal direction (X direction) and longitudinal direction (Y direction) of each divided layout of the chip 10 is formed mXn a layout pattern unit 11, where m is the number of aliquots of the X-direction, Y is [eta] number aliquot direction. m和η的数值越大,划分越细,划分越细意味着缺陷扫描的分辨率越高。 The larger the value of m and η divided finer, the finer division of defects means the higher resolution scan. 优选的,所述芯片版图10在X方向和Y方向的等份均在10到100之间,即m的数值范围为10〜100,η的数值范围也为10〜100。 Preferably, the chip layout 10 aliquots were in the X-direction and Y-direction between 10 and 100, i.e., the numerical range of 10~100 m, η numerical range also is 10~100.

[0032] 优选的,所述芯片版图10在X方向和Y方向均按照等距离进行划分。 [0032] Preferably, in accordance with the chip layout 10 are equidistantly divided in X and Y directions. 按照等距离划分形成的多个版图单元图形11,其形状和尺寸完全相同。 In accordance with a plurality of equidistantly divided layout pattern units 11 formed on its shape and dimensions are identical. 其中,所述芯片版图10在X方向上划分的间距与在Y方向上划分的间距可以相同也可以不同,若在X方向上划分的间距与在Y方向上划分的间距相同,则所述版图单元图形11为正方形,若在X方向上划分的间距与在Y方向上划分的间距不同,则所述版图单元图形11为长方形。 Wherein the chip layout 10 divided in the X direction and the pitch in the Y direction may be the same partition or different pitch, if divided in the X direction and the pitch in the Y direction in the same pitch division, then the layout square unit pattern 11, when divided in the X direction and the pitch in the Y direction different from the pitch of division is the unit layout pattern 11 is rectangular.

[0033] 优选的,所述X方向和Y方向划分的距离相同。 [0033] Preferably, the same as the X and Y directions from the division. 例如,可将所述芯片版图10中20 μ mX 20 μ m大小的单元格作为一个版图单元图形11。 For example, the chip layout 10 may be 20 μ mX cell size 20 μ m as a pattern layout unit 11.

[0034] 所述芯片版图10通常包括一系列的图形,分别对应各个生产阶段的电路结构,即半导体芯片各层电路的理想结构。 [0034] The chip 10 typically includes a series of layout pattern, the circuit configuration of the respective corresponding stages of production, i.e. the layers over the structure of the semiconductor chip circuit. 半导体芯片各层电路的理想图形均被分成多个版图单元图形11,此后将所有的版图单元图形11进行数字化转化并导入光学检测设备的缺陷检测程序中,并在所述缺陷检测程序将所述版图单元图形11定义为参考标准,以确认制成的芯片结构是否符合设计要求。 Over the circuit pattern of the semiconductor chip layers are each divided into a plurality of cell layout pattern 11, after all of the pattern layout unit 11 digitizes and introduced into the defect detection program converted optical detection apparatus and the defect detection program in the cell layout pattern 11 is defined as the reference standard, to confirm whether the structure made of chip design requirements.

[0035] 接着,提供一制备有多个芯片的待测晶圆,所述待测晶圆被选取进行缺陷测试。 [0035] Next, there is provided a wafer to be tested was prepared with a plurality of chips, the test wafer is selected for defect testing.

[0036] 然后,通过所述光学检测设备对所述待测晶圆的每个芯片进行扫描。 [0036] Then, the chip is scanned for each test wafer through said optical detection apparatus. 在此过程中,所述光学检测设备根据缺陷检测程序定义的参考图形在每个芯片上自动提取与之匹配的物理结构,获取相应的物理单元图形。 In this process, the reference pattern defined by the optical detection apparatus according to the defect detection program automatically extract matching the physical structure on each chip, to obtain the corresponding physical cell pattern. 由此,每个芯片通过扫描均获取了mXn个物理单元图形,所述物理单元图形与所述版图单元图形11是一一对应的。 Thus, each chip were acquired by scanning a pattern mXn physical units, the physical unit pattern and the pattern layout unit 11 is one to one.

[0037] 优选的,采用具有高灵敏度的光学检测设备对所述待测晶圆进行扫描。 [0037] Preferably, the use of optical detection equipment with high sensitivity to the tested wafer scan.

[0038] 之后,将所述物理单元图形进行数字化转化得到物理单元图形数据,同时将所述物理单元图形转化为由不同明暗灰阶表示的数字化图像。 After [0038], the physical unit of digital graphic pattern data converted to physical units, the physical unit while the graphic image is converted by the digital representation of different gray shading.

[0039] 最后,将所述物理单元图形与相应的版图单元图形11进行对比,以得到检测结果。 [0039] Finally, the physical layout of the unit cell pattern corresponding to pattern 11 are compared to obtain a detection result. 若所述物理单元图形与相应的版图单元图形11没有差异,则认为所述物理单元图形正常,没有缺陷;若所述物理单元图形与相应的版图单元图形11存在差异,则认为所述物理单元图形异常,发现缺陷。 If the physical layout of the unit cell pattern corresponding to the pattern 11 is no difference, the physical unit pattern is considered normal, and no defects; if the physical layout of the unit cell pattern corresponding to pattern 11 differ, it is considered the physical unit graphic anomalies, found defects.

[0040] 在本发明实施例提供的芯片缺陷的检测方法中,芯片的各个部分分别与理想的电路图形进行比对,因此检测更精确。 [0040] In the method for detecting defects in a chip according to an embodiment of the present invention, the various parts of the chip are aligned with, respectively, over the circuit pattern, and therefore more accurate detection. 即使相邻位置或重复结构存在相同的缺陷,也不会出现漏检。 Or even if there is a position adjacent to the same repeating structural defect does not occur undetected. 所述芯片缺陷的检测方法适用于光阻变形缺陷的检测。 The method of detecting a defect of the chip is adapted to detect defects in resist deformation.

[0041] 综上,在本发明实施例提供的芯片缺陷的检测方法中,将芯片版图划分成多个版图单元图形,对芯片进行缺陷检测时以所述版图单元图形为基准,而不是以相邻的芯片之间的差异性来判断是否存在缺陷,因此检测的精确度更高。 When [0041] In summary, the method for detecting defects in a chip according to an embodiment of the present invention, the chip layout pattern into a plurality of unit layout, the chip layout defect detection unit to the reference pattern, rather than phase the difference between adjacent chips to determine whether there is a defect, and therefore greater accuracy of detection.

[0042] 上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。 [0042] The above description is a description of the preferred embodiments of the present invention, and are not in any limiting the scope of the present invention, the art of the present invention of ordinary skill in the art to make according to the above disclosure of any change, modification, all fall within the scope of the claims .

Claims (7)

  1. 1.一种芯片缺陷的检测方法,其特征在于,包括: 将芯片版图划分成多个版图单元图形; 提供一制备有多个芯片的待测晶圆; 对所述待测晶圆进行扫描并根据所述多个版图单元图形分别提取所述多个芯片的物理单元图形; 将所述物理单元图形与相应的版图单元图形进行比对,以得到检测结果。 1. A method for detecting defects of a chip, characterized by comprising: a chip layout pattern into a plurality of cell layout; preparing a plurality of chips providing a wafer to be tested; the test wafer scan and It was extracted from the plurality of layout pattern of the plurality of unit cells physical graphics chip; means the physical layout pattern corresponding to the pattern units are aligned to obtain a detection result.
  2. 2.如权利要求1所述的芯片缺陷的检测方法,其特征在于,所述芯片版图按照横向和纵向分别进行划分。 2. The method of detecting defects according to claim 1 chip, wherein the chip layout in accordance with horizontal and vertical dividing respectively.
  3. 3.如权利要求2所述的芯片缺陷的检测方法,其特征在于,所述芯片版图在横向和纵向均进行等距离划分。 3. The method of detecting defects chip according to claim 2, wherein said chip layout are performed equidistantly divided in horizontal and vertical.
  4. 4.如权利要求3所述的芯片缺陷的检测方法,其特征在于,所述芯片版图在横向和纵向的等份均在10到100之间。 4. The detecting method according to claim 3 defective chip, wherein the chip layout in the horizontal and vertical aliquots were between 10 and 100.
  5. 5.如权利要求1所述的芯片缺陷的检测方法,其特征在于,在提供一制备有多个芯片的待测晶圆之前,在将芯片版图划分成多个版图单元图形之后,还包括将所述多个版图单元图形均导入缺陷检测设备。 5. The method of detecting defects according to claim 1 chip, characterized in that, prior to providing the preparation of a wafer with a plurality of test chips, after the chip layout pattern into a plurality of unit layout, further comprising the plurality of unit layout pattern defect detecting apparatus are introduced.
  6. 6.如权利要求5所述的芯片缺陷的检测方法,其特征在于,所述缺陷检测设备为光学检测设备。 6. The method of detecting defect of the chip as claimed in claim, wherein the defect detecting apparatus of an optical detection apparatus.
  7. 7.如权利要求1所述的芯片缺陷的检测方法,其特征在于,所述芯片缺陷的检测方法用于检测光阻变形缺陷。 7. A method for detecting defects according to claim 1 chip, wherein said chip defect detection method for detecting defects resist deformation.
CN 201410138986 2014-04-08 2014-04-08 Method for detecting chip defects CN103915361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201410138986 CN103915361A (en) 2014-04-08 2014-04-08 Method for detecting chip defects

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201410138986 CN103915361A (en) 2014-04-08 2014-04-08 Method for detecting chip defects

Publications (1)

Publication Number Publication Date
CN103915361A true true CN103915361A (en) 2014-07-09

Family

ID=51040956

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201410138986 CN103915361A (en) 2014-04-08 2014-04-08 Method for detecting chip defects

Country Status (1)

Country Link
CN (1) CN103915361A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104459508A (en) * 2014-08-13 2015-03-25 华进半导体封装先导技术研发中心有限公司 Wafer testing system and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1164049A (en) * 1995-03-22 1997-11-05 现代电子产业株式会社 Method for fabricating light exposure mask
US20040105578A1 (en) * 2002-08-21 2004-06-03 Hideo Tsuchiya Pattern inspection apparatus
CN102789999A (en) * 2012-08-16 2012-11-21 上海华力微电子有限公司 Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1164049A (en) * 1995-03-22 1997-11-05 现代电子产业株式会社 Method for fabricating light exposure mask
US20040105578A1 (en) * 2002-08-21 2004-06-03 Hideo Tsuchiya Pattern inspection apparatus
CN102789999A (en) * 2012-08-16 2012-11-21 上海华力微电子有限公司 Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104459508A (en) * 2014-08-13 2015-03-25 华进半导体封装先导技术研发中心有限公司 Wafer testing system and method
CN104459508B (en) * 2014-08-13 2018-02-27 华进半导体封装先导技术研发中心有限公司 A wafer test systems and wafer test method

Similar Documents

Publication Publication Date Title
US7676077B2 (en) Methods and systems for utilizing design data in combination with inspection data
US6185707B1 (en) IC test software system for mapping logical functional test data of logic integrated circuits to physical representation
US20090024967A1 (en) Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer
US20090055783A1 (en) Computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects
US20070052963A1 (en) Grouping systematic defects with feedback from electrical inspection
US7101722B1 (en) In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development
US20060269120A1 (en) Design-based method for grouping systematic defects in lithography pattern writing system
US20070133860A1 (en) Methods and systems for binning defects detected on a specimen
US20110170091A1 (en) Inspection guided overlay metrology
US7752584B2 (en) Method for verifying mask pattern of semiconductor device
US20130064442A1 (en) Determining Design Coordinates for Wafer Defects
US7904845B2 (en) Determining locations on a wafer to be reviewed during defect review
US20120308112A1 (en) Extraction of systematic defects
US8112241B2 (en) Methods and systems for generating an inspection process for a wafer
US20090257645A1 (en) Methods and systems for determining a defect criticality index for defects on wafers
JP2009516832A (en) Method and system for using design data in combination with the inspection data
US20080016481A1 (en) System and method for detecting a defect
US7711514B2 (en) Computer-implemented methods, carrier media, and systems for generating a metrology sampling plan
JP2004077390A (en) The pattern inspection apparatus
US4774461A (en) System for inspecting exposure pattern data of semiconductor integrated circuit device
US20140282334A1 (en) Method and Apparatus for Extracting Systematic Defects
CN101295659A (en) Method for detecting defect of semiconductor device
CN1877292A (en) Defect detection method
US6005966A (en) Method and apparatus for multi-stream detection of high density metalization layers of multilayer structures having low contrast
JP2005236094A (en) Method for manufacturing semiconductor device, method and system for failure analysis

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
RJ01