CN104993469A - Fool-proof protection circuit - Google Patents
Fool-proof protection circuit Download PDFInfo
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- CN104993469A CN104993469A CN201510398111.7A CN201510398111A CN104993469A CN 104993469 A CN104993469 A CN 104993469A CN 201510398111 A CN201510398111 A CN 201510398111A CN 104993469 A CN104993469 A CN 104993469A
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Abstract
The application relates to a protection circuit and particularly discloses a fool-proof protection circuit comprising a control pin, a first control circuit, a second control circuit, a switching circuit, and a power supply. The switching circuit is a power switch. The first control circuit contains two input terminals and one output terminal; when the two input terminals of the first control circuit input high-level signals, the output terminal outputs a low-level signal; and when the two input terminals of the first control circuit input a high-level signal and a low-level signal respectively, the output terminal outputs a high-level signal. The control pin is connected with a fixed metal probe of a test clamp and one input terminal of the first control circuit. The second control circuit receives a low-level signal outputted by the first control circuit, the switching circuit is disconnected; and otherwise, the switching circuit is connected. Compared with the prior art, the fool-proof protection circuit enables a test-free product like a chip to be prevented from being burned conveniently when being placed wrongly.
Description
Technical field
Application relates to chip detection technology, the protective circuit particularly in chip detection.
Background technology
The symmetric design of the similar square or rectangular of the many employings of current chip, integrated circuit modules, this design cannot from the first placement of foot of Direct Recognition chip profile or integrated circuit modules.The package surface being typically employed in product is identified by printing tag, but this method need carefully check product surface silk-screen, also needs to use magnifying glass for the less device of encapsulation.
This makes troubles with regard to giving the back end test producing line.Product for a certain production test fixture, can be put into fixture by usual product line, connects peripheral circuit test by fixture.For pin distribution than the product of comparatively dense, very accurate metal probe is normally adopted to be connected with product.Because product design adopts symmetric design, surperficial silk-screen is not easily checked again, so can be put back by product due to the carelessness of operating personnel in a lot of situation.And power supply is connected to product by metal probe, and power supply is a direct power supply, therefore, if mistake is placed in module direction, so because the pin distribution of product is not symmetric design, so power supply will be connected on other pins, easily burn product.
It is anti-mostly protective circuit more is at present to prevent power supply from connecing.Fool proof protection major part for chip or integrated circuit modules product is the design for product design.
Summary of the invention
The object of application is to provide a kind of fool proof protective circuit, is burnt when product (as the chip) mistake making it possible to avoid easily testing is placed.
For solving the problems of the technologies described above, application provides a kind of fool proof protective circuit, comprises: control pin, first control circuit, second control circuit, switching circuit and power supply; Wherein, described switching circuit is mains switch; Described first control circuit comprises two inputs and an output; Described output outputs signal to described second control circuit according to the signal that two inputs input; During the two equal input high level signal of input of described first control circuit, described output output low level signal; During an input input high level signal, another input input low level signal of described first control circuit, described output exports high level signal; Described control pin is all connected with an input of a fixing metal probe of test fixture, described first control circuit; The output of described first control circuit is connected with the input of described second control circuit; The output of described second control circuit is connected with the first port of described switching circuit; Second port, the 3rd port of described switching circuit are connected with the positive and negative electrode of described power supply respectively; Described second control circuit disconnects described switching circuit when receiving the low level signal of described first control circuit output; Described second control circuit receive described first control circuit export high level signal time conducting described in switching circuit.
Application execution mode in terms of existing technologies, when test chip is correctly placed, a fixing metal probe of test fixture is connected with the ground pin of test chip, simultaneously, this fixing metal probe is connected with control pin, like this, with the input input low level signal controlling the first control circuit that pin is connected, another input input high level signal, the output of first control circuit exports high level signal to second control circuit.Only have the signal of input second control circuit when being high level signal, second control circuit just conducting output low level signal to switching circuit.Switching circuit is ability conducting, i.e. the turn-on power switch when input low level signal only, and power turn-on, can test chip.When test chip mistake is placed, above-mentioned fixing metal probe is not connected with the ground pin of test chip, the equal input high level signal of two inputs of first control circuit, and like this, the output output low level signal of first control circuit is to second control circuit.When the signal of input second control circuit is low level signal, second control circuit ends, and its output is high level, and namely the first port of switching circuit is high level.When first port of switching circuit is high level, switching circuit disconnects, i.e. disconnecting power switch, and power supply is disconnected, and makes it possible to avoid the chip tested to be burnt.
In addition, also delay circuit is comprised.Delay circuit is used for preventing power supply spike.
In addition, delay circuit also comprises the first resistance, for the protection of first control circuit.
In addition, second control circuit comprises the 3rd resistance, for the protection of second control circuit.
In addition, switching circuit also comprises the 4th resistance, for the protection of switching circuit.
In addition, also comprise load, for the protection of power supply.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fool proof protective circuit according to application first execution mode;
Fig. 2 is the implementation schematic diagram correctly placed according to the test chip in application first execution mode;
Fig. 3 is the implementation schematic diagram placed according to the test chip mistake in application first execution mode;
Fig. 4 is the structural representation of the fool proof protective circuit according to application second execution mode.
Embodiment
For making the object of application, technical scheme and advantage clearly, be explained in detail below in conjunction with each execution mode of accompanying drawing to application.But, persons of ordinary skill in the art may appreciate that in each execution mode of application, proposing many ins and outs to make reader understand the application better.But, even without these ins and outs with based on the many variations of following execution mode and amendment, each claim of the application technical scheme required for protection also can be realized.
First execution mode of application relates to a kind of fool proof protective circuit, as shown in Figure 1, comprises and controls pin, first control circuit, delay circuit, second control circuit, switching circuit, load and power supply.
Wherein, switching circuit is mains switch.
Specifically, first control circuit comprises two inputs and an output, the signal output signal that output inputs according to two inputs.Wherein, during the two equal input high level signal of input of first control circuit, output output low level signal; During an input input high level signal, another input input low level signal of first control circuit, output exports high level signal.
Control pin to be connected with a fixing metal probe (not shown) of test fixture; An input of first control circuit is connected with control pin, and another input is connected with other function pin of test chip (this input input high level signal), and the output of first control circuit is connected with the input of delay circuit; The output of delay circuit is connected with the input of second control circuit; The output of second control circuit is connected with the first port of switching circuit; Second port of switching circuit is connected with the positive pole of power supply, and the 3rd port is connected with one end of load; The other end of load is connected with the negative pole of power supply.Wherein, load is for the protection of power supply.
Second control circuit is by the control to switching circuit, and when the signal that first control circuit exports is low level signal, disconnecting power switch, cuts off the electricity supply; When the signal that first control circuit exports is high level signal, turn-on power switch, power turn-on.
Below for product to be measured for chip, be specifically described.In the present embodiment, test chip ground pin is drawn as control pin.
When test chip is correctly placed, the control pin of this test chip is connected with test fixture fixing metal probe, and this fixing metal probe is connected with the control pin of fool proof protective circuit, and specific implementation as shown in Figure 2.1 is the metal probe on test fixture; 2 be metal probe connect test chip 4 on control pin, this control pin is the ground pin of test chip.When test chip placement direction is correct, the 1 ground pin being connected to test chip; 3 is on test chip and the pin of 2 pin symmetric positions.
Now, with the input input low level signal controlling the first control circuit that pin is connected, another input input high level signal, the output of first control circuit exports high level signal to delay circuit.
Delay circuit exports second control circuit to by after the high level signal time delay of reception, to avoid the power supply spike produced because of the shake of test products.
Conducting when second control circuit receives high level signal, and output low level signal is to switching circuit.
Conducting, i.e. power switch conducts, then power turn-on during switching circuit reception low level signal, can test products.
But, when test chip mistake is placed, the control pin of test chip is not connected with the fixing metal probe of above-mentioned test fixture, because this fixing metal probe is connected with control pin, not the ground pin of test chip with what control that pin is connected, but other function pin of test chip, specific implementation is as shown in Figure 3.When test chip direction puts back, metal probe 1 touches pin 3, and this pin 3 is not ground pin.
In this case, the equal input high level signal of two inputs of first control circuit, the output output low level signal of first control circuit is to delay circuit.
Delay circuit exports second control circuit to by after the low level signal time delay of reception.
Second control circuit ends when receiving low level signal.
During second control circuit cut-off, the first port in switching circuit is high level, and the second port is also high level, switching circuit ends, then switching circuit disconnects, i.e. disconnecting power switch, then power supply is cut off, and the product making it possible to avoid testing is burnt because mistake is placed.
In the present embodiment, control pin to be connected, when test products is correctly placed with a fixing metal probe of test fixture, this fixing metal probe is connected with the ground pin of test products, controlling pin is fixing low level, and power switch conducts can test products; When test products mistake is placed, this fixing metal probe is not connected with the ground pin of test products, and controlling pin is not low level, and mains switch disconnects, and avoids test products to be burnt.Like this, just can the fixed position of test products draw ground pin, with fixing metal probe with the use of, make it possible to avoid test products to be burnt easily, simple to operate, easily realize.
Second execution mode of the present invention relates to a kind of fool proof protective circuit.Second execution mode is the further refinement of the first execution mode.In this second embodiment, the concrete structure of fool proof protective circuit as shown in Figure 4.
In the present embodiment, first control circuit is NAND gate circuit.Output output low level signal during two inputs of NAND gate equal input high level signal; During an input input low level signal, another input input high level signal of NAND gate, output exports high level signal.
Delay circuit comprises the first resistance and electric capacity; One end of first resistance is connected with the output of first control circuit, and the other end is connected with the input of second control circuit; Electric capacity one end is connected with the input of second control circuit, other end ground connection.Wherein, the first resistance is for the protection of first control circuit.
Second control circuit comprises NPN type triode, the second resistance and the 3rd resistance; NPN type triode comprises base stage, emitter and collector electrode, and base stage is the input of second control circuit, grounded emitter, the output of current collection very second control circuit; One end of second resistance is connected with the base stage of NPN type triode, and the other end is connected with the emitter of NPN type triode; One end of 3rd resistance R3 is connected with the output of delay circuit, and the other end is connected with the base stage of NPN type triode.Wherein, the second resistance is for setting up bias voltage intrinsic between base stage and emitter when NPN type triode works.3rd resistance is for the protection of second control circuit.
Switching circuit comprises P-MOS pipe and the 4th resistance; P-MOS pipe comprises grid, source electrode and drain electrode; Grid is the first port of switching circuit, and source electrode is the second port of switching circuit, drains as the 3rd port of switching circuit; 4th resistance one end is connected with grid, and the other end is connected with source electrode.
When the grid of P-MOS pipe is low level, source electrode is high level, the conducting of P-MOS pipe, then switching circuit conducting fool proof protective circuit, can test products; But when the grid of P-MOS pipe, source electrode are high level, P-MOS pipe ends, then switching circuit turns off fool proof protective circuit, makes to avoid test products to be burnt.Wherein, the 4th resistance is for the protection of switching circuit, and bias voltage intrinsic between grid and source electrode when producing the work of P-MOS pipe.
Claims (3)
1. a fool proof protective circuit, is characterized in that, comprises: control pin, first control circuit, second control circuit, switching circuit and power supply; Wherein, described switching circuit is mains switch; Described first control circuit comprises two inputs and an output; Described output outputs signal to described second control circuit according to the signal that two inputs input; During the two equal input high level signal of input of described first control circuit, described output output low level signal; During an input input high level signal, another input input low level signal of described first control circuit, described output exports high level signal; Described control pin is all connected with an input of a fixing metal probe of test fixture, described first control circuit; The output of described first control circuit is connected with the input of described second control circuit; The output of described second control circuit is connected with the first port of described switching circuit; Second port, the 3rd port of described switching circuit are connected with the positive and negative electrode of described power supply respectively; Described second control circuit disconnects described switching circuit when receiving the low level signal of described first control circuit output; Described second control circuit receive described first control circuit export high level signal time conducting described in switching circuit.
2. fool proof protective circuit according to claim 1, is characterized in that, also comprise delay circuit; Described delay circuit is all connected with described first control circuit, described second control circuit; The input of described delay circuit receives the signal of described first control circuit output; The output of described delay circuit exports time delayed signal to described second control circuit.
3. fool proof protective circuit according to claim 1, is characterized in that, described first control circuit is NAND gate circuit; Described not circuit comprises two inputs and an output; The input of described first control circuit is the input of described NAND gate circuit; The output of described first control circuit is the output of described NAND gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510398111.7A CN104993469A (en) | 2015-06-30 | 2015-06-30 | Fool-proof protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510398111.7A CN104993469A (en) | 2015-06-30 | 2015-06-30 | Fool-proof protection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104993469A true CN104993469A (en) | 2015-10-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510398111.7A Pending CN104993469A (en) | 2015-06-30 | 2015-06-30 | Fool-proof protection circuit |
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| CN (1) | CN104993469A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955189A (en) * | 2016-06-29 | 2016-09-21 | 歌尔股份有限公司 | Foolproof protection module and automated machine platform |
| CN108169663A (en) * | 2017-12-28 | 2018-06-15 | 湖南国科微电子股份有限公司 | A kind of pcb board with fool proof debugging interface |
| CN109412134A (en) * | 2018-12-18 | 2019-03-01 | 惠科股份有限公司 | Fool-proof circuit, connector and display device |
| CN110471320A (en) * | 2019-09-23 | 2019-11-19 | 重庆工商大学 | Robot emergency stop control circuit |
| CN112462166A (en) * | 2020-11-04 | 2021-03-09 | 龙尚科技（上海）有限公司 | Fool-proof detection circuit and clamp |
-
2015
- 2015-06-30 CN CN201510398111.7A patent/CN104993469A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955189A (en) * | 2016-06-29 | 2016-09-21 | 歌尔股份有限公司 | Foolproof protection module and automated machine platform |
| CN105955189B (en) * | 2016-06-29 | 2018-10-12 | 歌尔股份有限公司 | Fool proof protection module and automated machine |
| CN108169663A (en) * | 2017-12-28 | 2018-06-15 | 湖南国科微电子股份有限公司 | A kind of pcb board with fool proof debugging interface |
| CN109412134A (en) * | 2018-12-18 | 2019-03-01 | 惠科股份有限公司 | Fool-proof circuit, connector and display device |
| CN110471320A (en) * | 2019-09-23 | 2019-11-19 | 重庆工商大学 | Robot emergency stop control circuit |
| CN112462166A (en) * | 2020-11-04 | 2021-03-09 | 龙尚科技（上海）有限公司 | Fool-proof detection circuit and clamp |
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| C06 | Publication | ||
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151021 |
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| WD01 | Invention patent application deemed withdrawn after publication |