CN103336239A

CN103336239A - A wafer testing method

Info

Publication number: CN103336239A
Application number: CN2013102179736A
Authority: CN
Inventors: 王善屹; 王磊
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-06-03
Filing date: 2013-06-03
Publication date: 2013-10-02
Anticipated expiration: 2033-06-03
Also published as: CN103336239B

Abstract

The invention provides a wafer testing method. The wafer testing method carries out a test on a to-be-tested wafer respectively along two directions which are mutually perpendicular. When the wafer test is influenced by factors of the test itself, test results in different directions can present obvious distinguishable distributions, so that whether yield rate distributions are influenced by factors of the test itself can be identified directly according to the test results, and the production efficiency is substantially raised.

Description

The method of wafer sort

Technical field

The present invention relates to integrated circuit and make the field, particularly relate to a kind of method of wafer sort.

Background technology

(Chip Probing is after the wafer manufacturing is finished CP), and each chip on the wafer is carried out the test of electrical ability and circuit function in wafer sort.Chip testing (die sort) or wafer electrical measurement (wafer sort) are also named in wafer sort.

Wafer sort is for following purpose, at first, can identify qualified chip before wafer is delivered to encapsulation factory, and underproof chip does not carry out follow-up encapsulation process, saves cost.In addition, can carry out characteristic evaluation to the electrical parameter of devices/circuits, the slip-stick artist controls the quality level of technology by the distribution of these monitoring parameters.

When test, wafer is fixed on the chuck of pull of vacuum, and probe contacts with each weld pad of chip simultaneously.Tester is imported measured device with curtage by probe, tests this chip then for the response of this input signal, obtains unit for electrical property parameters.Quantity, order and the type of test are controlled by computer program.The existing order that chip on the wafer is tested is along a certain direction, the chip on the wafer to be tested one by one.As shown in Figure 1, be the existing synoptic diagram that chip on the wafer is tested, wherein the grid that surrounds of dotted line is represented the chip on the wafer, fills the grid of shade and represents to be labeled chip bad or that electrical property is not good.In the actual production, wafer often is formed with breach (notch) 101 and is used for the position of coarse alignment wafer, in the present example, breach 101 is towards the right side behind the wafer process coarse alignment to be tested, probe is from testing (for example path that marks for solid line Fig. 1) to chip line by line one by one in the horizontal direction, and the position on wafer is noted with the form of wafer figure on computers with qualified chip and defective products then.

In general, wafer production be by product category by a batch production, for example, same box wafer, through complete same production run and technological parameter, the chip yield on it also is similar distribution.Yet, sometimes Ce Shi result can not reflect the distribution of chip bad on the wafer really, owing to reasons such as board calibration or test setting, the chip of some zone on measurement direction that test result can show as on this batch wafer all is marked as bad or unit for electrical property parameters not good (as dash area among Fig. 1).Therefore, the slip-stick artist can not tell in the face of such test result the time that there is defective really in these chips or because the problem that test causes, can only or confirm by other means by test again, so just increase the process time, in addition serious reduction production efficiency.

Summary of the invention

The invention provides a kind of method of wafer sort, can't directly tell bad test result with the solution prior art is because the certain defectiveness of chip or because the problem that test causes.

For solving the problems of the technologies described above, the invention provides a kind of method of wafer sort, the chip on the wafer to be tested one by one, the method for described wafer sort is treated test wafer respectively in two orthogonal directions and is tested.

Optionally, wafer to be tested is the multi-disc wafer of same batch like products, and described multi-disc wafer is divided into two groups, and the direction of testing of two groups of wafers is vertical mutually.

Optionally, the wafer of odd number sheet in the described multi-disc wafer is tested at first direction; Even number wafer in the described multi-disc wafer is tested in the second direction vertical with first direction.

Optionally, wafer to be tested is single-wafer, and described single-wafer is divided into a plurality of zones, and the direction that adjacent areas is tested is vertical mutually.

Optionally, orthogonal two strings are divided into four zones with wafer on the wafer, and the direction that two adjacent zones are tested is vertical mutually.

Optionally, orthogonal two diameters are divided into four zones with wafer on the wafer, defining these four zones in the direction of the clock is first area, second area, the 3rd zone, the 4th zone, wherein first area and the 3rd zone are tested at first direction, and second area and the 4th zone are tested in second direction.

Optionally, the direction of the diameter at definition notched wafer and place, the wafer center of circle is first direction, and the direction vertical with first direction is second direction in the definition wafer plane.

Compared with prior art, the method for wafer sort provided by the invention has the following advantages:

The method of described wafer sort is tested at orthogonal both direction wafer to be tested, when if wafer sort is subjected to influencing of the factor of test own, test result on the different directions can present tangible difference and distribute, can directly tell this by test result like this and measure the influence that whether is subjected to the factor of test own, the chip of mark is bad owing to the factor affecting of test itself thereby can effectively differentiate, also just reduced the situation that needs test again or by other means test result is confirmed, further, can also determine the concrete interval of the wafer of the factor affecting of tested person own by test result, improve efficient greatly.

Description of drawings

Fig. 1 is the existing synoptic diagram that chip on the wafer is tested;

The synoptic diagram of the crystal round test approach that Fig. 2 A to Fig. 2 B provides for the embodiment of the invention one;

The synoptic diagram of the crystal round test approach that Fig. 3 provides for the embodiment of the invention two.

Embodiment

Core concept of the present invention is, a kind of method of wafer sort is provided, the method of this wafer sort is tested respectively along two orthogonal directions wafer to be tested, when wafer sort is subjected to influencing of the factor of test own, test result on the different directions can present tangible difference and distribute, like this, whether the yield that can directly tell test result from test result distributes is subjected to the influence of the factor of test own, has improved production efficiency greatly.

Be described in more detail below in conjunction with the method for synoptic diagram to wafer sort of the present invention, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.

In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.

Embodiment one

Wafer to be tested be for batch the multi-disc wafer of like products, for example be the box wafer (25) in the production of standard, described multi-disc wafer is divided into two groups, the direction of testing of these two groups of wafers is vertical mutually.If there is the influence of the factor of test own, on the wafer that different directions is tested, can present tangible difference so, directly tell the problem whether this time test exists test itself with this.

Preferably, be divided into two groups by odd number sheet and even number sheet, the wafer of odd number sheet is tested at first direction; Even number wafer in the described multi-disc wafer is tested in the second direction vertical with first direction.More excellent, with reference to Fig. 2 A to Fig. 2 B, the direction (horizontal direction among the figure) of the diameter at definition notched wafer and place, the wafer center of circle is first direction, the direction (in figure vertical direction) vertical with first direction is second direction in the definition wafer plane.That is to say, the 1st wafer of this batch is carried out one by one line by line test (shown in Fig. 2 A) to chip in the horizontal direction, the 2nd wafer in the vertical direction carries out one by one test (shown in Fig. 2 B) by row to chip, and the 3rd wafer is carried out one by one line by line test to chip in the horizontal direction ... the rest may be inferred.

If test result is the spaced apart of rule by the odd even sheet number of wafer, for example all showing as in the horizontal direction on the odd number sheet, the subregion chip is marked as bad or unit for electrical property parameters not good (dash area among Fig. 2 A), on the even number wafer, all show as in the vertical direction subregion chip and be marked as bad or unit for electrical property parameters not good (dash area among Fig. 2 B), or corresponding region and chipless is labeled as bad in the horizontal direction or unit for electrical property parameters is not good on the even number sheet.Then can judge the factor affecting that this time test is subjected to test itself, the problem of setting as detection calibration or parameter etc.Further, phenomenon spaced apart certain wafer from this batch wafer that is rule as if the odd even sheet number by wafer begins to occur or finish, and gets final product the concrete interval of the wafer of the concrete factor affecting of definite tested person own.

If the rule that odd number sheet or even number sheet are not pressed in the distribution of test result defective region on this batch wafer, and though for example odd number sheet or even number sheet all the chip in the zone be labeled as badly in the horizontal direction, then can get rid of is because the influence of test factor.

Embodiment two

In the present embodiment, wafer to be tested is single-wafer, zones of different on this this wafer is treated test wafer respectively in two orthogonal directions test, can distribute whether to be subjected to the influence of test problem by the yield that test result picks out test result.

Concrete, wafer is divided into four zones by orthogonal two strings on it with wafer in the present embodiment, and the direction that two adjacent zones are tested is vertical mutually.More excellent, utilize that orthogonal two diameters are divided into four zones with wafer on the wafer, in the present embodiment, choose wherein that a diameter is the diameter through notched wafer, as shown in Figure 3.Defining these four zones in the direction of the clock is first area 311, second area 312, the 3rd zone 313, the 4th zone 314; The direction of the diameter at definition notched wafer and place, the wafer center of circle is first direction, the direction vertical with first direction is second direction in the definition wafer plane, wherein first area 311 and the 3rd zone 313 are tested at first direction, and second area 312 and the 4th zone 314 are tested in second direction.Identical with the principle among the embodiment one, if the yield in these four zones distributes along with the interior variation that rule occurs in the different zone of not coexisting of measurement direction, bad chip distribution along first direction for example appears in first area 311 and the 3rd zone 313, bad chip distribution along second direction appears in second area 312 and the 4th zone 314, as shown in Figure 3, can conclude that then this test exists the chip that causes owing to the reason of test own to be marked as bad factor; If the yield in these four zones distributes not with the different generation of measurement direction significant change, for example, the first area occurs along the distribution of the bad chip of first direction, the bad chip of second area still is to distribute along first direction, can judge that then the chip that is not owing to the reason of test own causes is marked as bad.

In another embodiment of the present invention, the method for testing to single-wafer among the embodiment two is attached among the embodiment one, every wafer is all carried out as the test mode among the embodiment two, and make the direction of measurement of same area of adjacent wafers vertical mutually, equally can to batch the multi-disc wafer test.

In sum, the invention provides a kind of method of wafer sort, this method is tested wafer to be tested on orthogonal both direction, the chip of mark is bad owing to the factor affecting of test itself thereby can effectively differentiate, and on test result, directly tell the influence whether test result is subjected to the factor of test own, also just having reduced needs test again or by the situation that other means are confirmed test result, has improved efficient greatly.

Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims

1. the method for a wafer sort is tested one by one to the chip on the wafer, it is characterized in that, the method for described wafer sort is treated test wafer respectively in two orthogonal directions and tested.

2. the method for wafer sort as claimed in claim 1 is characterized in that, described wafer to be tested is the multi-disc wafer of same batch like products, and described multi-disc wafer is divided into two groups, and the direction of testing of two groups of wafers is vertical mutually.

3. the method for wafer sort as claimed in claim 2 is characterized in that, the wafer of odd number sheet in the described multi-disc wafer is tested at first direction; Even number wafer in the described multi-disc wafer is tested in the second direction vertical with first direction.

4. the method for wafer sort as claimed in claim 1 is characterized in that, described wafer to be tested is single-wafer, and described single-wafer is divided into a plurality of zones, and the direction that adjacent areas is tested is vertical mutually.

5. the method for wafer sort as claimed in claim 4 is characterized in that, orthogonal two strings are divided into four zones with wafer on the wafer, and the direction that two adjacent zones are tested is vertical mutually.

6. the method for wafer sort as claimed in claim 5, it is characterized in that, orthogonal two diameters are divided into four zones with wafer on the wafer, defining these four zones in the direction of the clock is first area, second area, the 3rd zone, the 4th zone, wherein first area and the 3rd zone are tested at first direction, and second area and the 4th zone are tested in second direction.

7. as the method for claim 3 or 6 described wafer sorts, it is characterized in that the direction of the diameter at definition notched wafer and place, the wafer center of circle is first direction, the direction vertical with first direction is second direction in the definition wafer plane.