CN109633209A - Test sample and preparation method thereof - Google Patents
Test sample and preparation method thereof Download PDFInfo
- Publication number
- CN109633209A CN109633209A CN201910099456.0A CN201910099456A CN109633209A CN 109633209 A CN109633209 A CN 109633209A CN 201910099456 A CN201910099456 A CN 201910099456A CN 109633209 A CN109633209 A CN 109633209A
- Authority
- CN
- China
- Prior art keywords
- sample
- wafer
- test
- target area
- test sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01Q—SCANNING-PROBE TECHNIQUES OR APPARATUS; APPLICATIONS OF SCANNING-PROBE TECHNIQUES, e.g. SCANNING PROBE MICROSCOPY [SPM]
- G01Q30/00—Auxiliary means serving to assist or improve the scanning probe techniques or apparatus, e.g. display or data processing devices
- G01Q30/20—Sample handling devices or methods
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
- Radiology & Medical Imaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
The present invention relates to a kind of test samples and preparation method thereof, the preparation method of the test sample includes: to provide a sample comprising target area, the sample is ground by semiconductor samples to be measured, with single-wafer thickness, the thickness direction of the section to be measured of the target area perpendicular to the sample；Wafer is accompanied in two sides side wall adherency on the thickness direction of the sample, and the surface for accompanying wafer is flushed with the surface of the sample；It accompanies wafer and the sample surfaces integrally to grind to described, until expose the section to be measured of the target area, sample after grinding and wafer is accompanied integrally to be used as test sample.The above method can be improved the accuracy of test sample.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of test sample and preparation method thereof.
Background technique
After atomic force microscope (SAFM) is by invention, it is widely used in the sections such as physics, chemistry, biology and material
Field, and the Scanning capacitance microscope (SCM) derived is also referred to as exploitation, manufacture and examines one kind of semiconductor devices very
Important and necessary means, especially for the inspection of the example injection technology of semiconductor devices.
When atomic force microscope (SCM) work is under contact mode, Scanning capacitance microscope (SCM) use can be used as,
Add a low-frequency ac electric field between conductive afm tip and semiconductor samples, the free carrier in sample is periodically inhaled by needle point
Draw or repel, the capacitor that needle point is constituted with semiconductor samples also changes therewith, this capacitance variations utilizes hyperfrequency resonant capacitor
Sensor obtains to measure, and test result can characterize the doping characteristic on scanned surface.Due in test process, afm tip
It is directly contacted with the surface of sample, it is therefore, whether particularly significant comprising target area in the scanned region of sample.
Test sample passes through artificial grind away and prepares at present, by diamond sand paper grinding semiconductor device to destination layer, so
Cloth polishing and section is cleaned with polishing again afterwards.The sand particle size of diamond sand paper most thin at present is 0.1 μm or so, works as target area
Size in μm rank, basic in grinding control there is no problem, can accurately expose target area section；But once
Target area size is less than 1 μm, especially in 200nm or less, it is easy to generate grinding；Diamond sand paper crystalline substance can not accurately be ground
It is milled to destination layer, or can only probabilistic be ground to destination layer.Also, polishing cleaning is carried out using polishing cloth subsequent
When, although can only grind away very thin one layer, for the target area of size originally very little, also easily lead to target
Region, which is crossed, grinds.
Therefore, in the prior art, larger using target area size limitation of the artificial grind away preparation for sample, it can prepare
Sample scope it is smaller.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of test samples and preparation method thereof, improve test sample
The accuracy of preparation.
Technical solution of the present invention provides a kind of preparation method of test sample, comprising: providing one includes target area
Sample, the sample are ground by semiconductor samples to be measured, have single-wafer thickness, the section to be measured of the target area
Perpendicular to the thickness direction of the sample；Wafer is accompanied in two sides side wall adherency on the thickness direction of the sample, described to accompany
The surface of wafer is flushed with the surface of the sample；Wafer and the sample surfaces is accompanied integrally to grind to described, directly
To the section to be measured for exposing the target area, sample after grinding and wafer is accompanied integrally to be used as test sample.
Optionally, the sample is cuboid.
Optionally, described to accompany wafer identical as the sidewall shape and size that the sample is pasted.
Optionally, wafer and sample surfaces are accompanied integrally to grind to described using polishing cloth.
Optionally, in process of lapping, polishing fluid is sprayed in lapped face.
Optionally, in three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μ for the target area
m。
Optionally, further includes: by the bottom surface of the sample be fixed on a fixed wafer and then the sample thickness
Wafer is accompanied in two sides side wall adherency on degree direction.
Optionally, it is fixed between the sample and the fixed wafer by conducting resinl.
Optionally, described that wafer bottom is accompanied to be fixed on the fixed crystal column surface.
Optionally, described that wafer is accompanied to be adhered to the sample side wall by a glue-line, the thickness of the glue-line is less than etc.
In 1 μm.
Optionally, the distance between the sample surfaces and the section to be measured are more than or equal to 1 μm.
Optionally, the distance between side wall on the target area and thickness direction of the sample is more than or equal to 1 μm.
Technical solution of the present invention provides a kind of test sample, comprising: one includes the sample of target area, the sample
Test surfaces perpendicular to the sample thickness direction and expose the section to be measured of the target area；It is pasted on the sample
Two sides side wall on thickness direction accompanies wafer, described that platelet circular surfaces and the test surfaces of the sample is accompanied to flush and thick
Degree is consistent, respectively less than the thickness of monolithic bare silicon wafer.
Optionally, the junction of the test surfaces for accompanying wafer and the sample has continuous grinding marks.
Optionally, in three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μ for the target area
m。
It optionally, further include fixed wafer, the fixed crystal column surface is fixed in the bottom surface of the sample.
Optionally, it is fixed between the sample bottom surface and the fixed crystal column surface by conducting resinl.
Optionally, described that wafer bottom is accompanied to be fixed on the fixed crystal column surface.
Optionally, described that wafer is accompanied to be adhered to the sample side wall by a glue-line, the thickness of the glue-line is less than etc.
In 1 μm.
Optionally, the distance between side wall on the target area and thickness direction of the sample is more than or equal to 1 μm.
Test sample preparation method of the invention can accurately prepare the test sample with small size target area, avoid
Grinding was caused to section to be measured, improves the success rate of test sample production, and reduce and test specimens are prepared by lapping mode
To the limitation of target area size when product.
Detailed description of the invention
Fig. 1 to Fig. 6 B is the structural schematic diagram of the preparation process of the test sample of the embodiment of the invention.
Specific embodiment
The specific embodiment of test sample provided by the invention and preparation method thereof is done specifically with reference to the accompanying drawing
It is bright.
Fig. 1 to Fig. 6 B is please referred to, is the structural representation of the preparation process of the test sample of the embodiment of the invention
Figure.
Referring to FIG. 1, providing a sample to be tested 100 comprising target area.
Doped region and/semiconductor devices etc. are formed in the sample to be tested 100.The sample to be tested 100 may include
Dielectric layer, semiconductor layer, metal layer etc..The sample to be tested 100 can be to be formed with the bare chip of semiconductor devices or half
Structure in conductor device forming process can be the cuboid determined from wafer.When needs are in the sample to be tested 100
A certain region when being tested, need through abrasive article region exposure to be tested.
In the specific embodiment, it is formed with semiconductor devices 102 in the sample to be tested 100, needs partly to lead to described
Target area 103 in body device 102 is tested.The test can be the doping concentration of detection target area 103, capacitor
The electrical property features such as value.
As the integrated level of integrated circuit improves, the size reduction of semiconductor devices 102, target area 103 to be detected
As a part of semiconductor devices 102, size is also further reduced, and how accurately to expose the section to be measured of target area,
It is the key that setup test sample.
In a specific embodiment of the invention, for the length in three-dimensional system of coordinate, at least on a coordinate direction
Degree is less than or equal to 1 μm of sample to be tested 100, can not accurately expose the section to be measured of target area by directly grinding.At this
In specific embodiment, the target area 103 is a cuboid, at least one size is small in length, width and height
In or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.Certainly, for mesh
In the case that size on three directions in mark region 103 is all larger than 1 μm, the test sample system in the specific embodiment of the invention
Preparation Method is equally applicable.
Fig. 2A and 2B are please referred to, wherein Fig. 2 B is the diagrammatic cross-section of the secant AA ' along Fig. 2A.
The sample to be tested 100 (please referring to Fig. 1) is ground, prefabricated sample 200, the target area 103 are formed
In the prefabricated sample 200, and the thickness h of the prefabricated sample 200 and monolithic bare silicon wafer consistency of thickness, the target area
The section to be measured 1031 in domain 103 perpendicular to the prefabricated sample 200 thickness direction, on prefabricated 200 thickness direction of sample
Surface be prefabricated sample 200 side wall.
Specifically, according to the domain structure of the semiconductor devices in the sample to be tested 100, it can be determined that go out target area
Approximate location locating for 103.According to approximate location of the target area 103 in sample to be tested 100, to the sample to be tested
100 are ground.When target area 103 and the sample to be tested surface are larger, the sand paper of larger particles partial size can be used
It is quickly ground, to improve grinding efficiency.Observe target area 103 close to test sample by modes such as Electronic Speculum, microscopes
Stop grinding when 100 surface of product.Multiple surfaces of sample to be tested 100 can be ground around the target area 103, most
End form is equal to the prefabricated sample 200 of monolithic bare silicon wafer thickness at thickness.Preferably, the prefabricated sample 200 is cuboid；Or
Prefabricated sample 200 described in person at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described two opposite
Vertical sidewall between.The prefabricated sample 200 also has the top surface 201 and bottom surface 202 parallel with the section 1031 to be measured.
In order to avoid grinding was caused in the section to be measured 1031 to target area 103, need to the section 1031 to be measured
The distance between prefabricated 200 surface of sample is controlled.In a specific embodiment of the invention, the prefabricated sample 200
Surface, including multiple side walls and top surface 201 and bottom surface 202, the distance between described section 1031 to be measured is more than or equal to 1
μm.It in the specific embodiment, can be controlled by process of lapping, so that the target area 103 is located at prefabricated thickness of sample
Near medium position on direction.In other specific embodiments, can also suitably reduce the section to be measured 1031 with it is prefabricated
The top surface 201 the distance between parallel with the section 1031 to be measured in sample 200, it is described to be measured to reduce subsequent grinding exposure
The time in section 1031.
Referring to FIG. 3, semiconductor bottom plate 300 is fixed in the bottom surface 202 (please referring to Fig. 2 B) of the prefabricated sample 200
Surface.
The semiconductor bottom plate 300 can be for by the wafer cut, the size of the semiconductor bottom plate 300 be much larger than institute
The size for stating prefabricated print 200, as the loading plate of prefabricated print 200, convenient for subsequently through the mobile institute of mechanical or hand-held
It states prefabricated sample 200 or the prefabricated sample 200 is handled.
In a specific embodiment of the invention, pass through conduction between the prefabricated sample 200 and the semiconductor bottom plate 300
Glue is fixed.In some embodiments, the conducting resinl can be the viscoloid doped with metal, such as elargol, make
Obtaining has good electric conductivity between the prefabricated sample 200 and the semiconductor bottom plate 300, so as to partly be led by described
Body bottom plate 300 applies voltage to the prefabricated print 200.
The semiconductor bottom plate can be adhered to after the 202 surface coating colloid of bottom surface of the prefabricated sample 200
300 surfaces, then solidified by modes such as heating.
Referring to FIG. 4, wafer 400 is accompanied in the two sides side wall stickup in the prefabricated sample 200, it is described to accompany wafer 400
Thickness and prefabricated 200 consistency of thickness of sample, the surface on the surface for accompanying wafer 400 and the prefabricated sample 200
It flushes.
It is described accompany wafer 400 can for bare silicon wafer cut after part wafer, it may have the thickness of monolithic bare silicon wafer.?
In a specific embodiment of the invention, it is identical material with the semiconductor bottom plate 300, is monocrystalline silicon wafer crystal.In the tool
It is described to accompany wafer 400 for cuboid in body embodiment, accompany wafer 400 and the prefabricated sample 200 to paste with described
Sidewall shape it is identical with size.It is described that wafer 400 is accompanied laterally to be pasted on the vertical side of 200 any two of prefabricated sample
On wall, the target area is between described two vertical side walls.
200 side wall of prefabricated sample and described accompany are fixed between wafer 400 by glue-line.The glue-line can be AB
The glue-lines such as glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee 200 side wall of prefabricated sample and institute
It states to accompany and be fitted closely between wafer 400, the thickness of the glue-line is less than or equal to 1 μm.
It is described that 400 bottom of wafer is accompanied also to be secured to 300 surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 and the prefabricated print 200 avoids described accompanying wafer 400 with the prefabricated print 200 rear
In continuous process of lapping, it is detached from.Also, during accompanying wafer 400 described in the stickup, with the semiconductor bottom plate 300
As loading plate, height fall can be generated between wafer 400 and the top surface 201 of the prefabricated print 200 to avoid described accompany,
Reduce the difficulty that wafer 400 is accompanied described in pasting.The size for accompanying wafer 400 is less than the ruler of the semiconductor bottom plate 300
It is very little, it is fully located on the semiconductor bottom plate 300, so that the semiconductor bottom plate 300 is capable of providing preferable supporting effect.
In other specific embodiments, the semiconductor bottom plate 300 can not also be provided, is forming the prefabricated sample
After 200, directly the prefabricated print 200 side wall paste described in accompany wafer 400.
Referring to FIG. 5, accompanying wafer 400 to be polishing to semiconductor bottom plate 300 (please referring to Fig. 4) edge to flush by described.
It can be ground by diamond sand paper or by blade dicing methods, the uncovered area of removal semiconductor bottom plate 300
Domain so that polishing after semiconductor bottom plate 300 ', accompany wafer 400 and 200 edge of prefabricated print to flush.Polishing can be passed through
It is described to accompany wafer 400 and semiconductor bottom plate 300, so that described accompany wafer 400, prefabricated print 200 and semiconductor bottom plate
A 300 generally cuboids or other regular figures, convenient for being held or being moved in subsequent polishing and test process.
If in other specific embodiments, not providing the semiconductor bottom plate 300, wafer 400 can be accompanied by selection
Shape and size so that described accompany wafer 400 and the generally cuboid of prefabricated print 200 or other regular figures.
Fig. 6 A and 6B are please referred to, accompanies (the please referring to Fig. 5) surface of wafer 400 and the prefabricated sample 200 (please join for described
Examine Fig. 5) plane is ground as a whole for top surface 201 (please referring to Fig. 5), until exposing the target area 103
Section to be measured 1031；Prefabricated sample 200 ' after grinding accompanies wafer 400 ' and semiconductor bottom plate 300 ' whole as surveying
Test agent 600.Fig. 6 B is the partial enlargement diagram of 1031 region of section to be measured.
In the lesser situation of 103 size of target area, when being, for example, less than 1 μm, piece is accompanied to described using polishing cloth
(the please referring to Fig. 5) surface of wafer 400 and the top surface 201 (please referring to Fig. 5) of prefabricated sample 200 (please referring to Fig. 5) are ground.By
It is larger in the grinding precision of polishing cloth, grinding can be effectively avoided, control grinding depth can be stopped at accurately described to be measured
1031 position of section.But since polishing cloth is easily-deformable, ground flat and around have difference in height when, be easy grinding
The problem of horizontal edge generates fillet, leads to section missing to be measured and lapped face out-of-flatness.In specific implementation of the invention
In mode, the top surface 201 of the prefabricated print is ground as a whole with the surface for accompanying wafer 400, and the two it
Between there's almost no difference in height, it is thus possible to improve the flatness of lapped face, avoids in process of lapping in section 1031 to be measured
Edge leads to the problem of fillet, keeps the integrality in section 1031 to be measured.
During being ground using polishing cloth, 400 surface of wafer and the pre- sample preparation can also be accompanied described
Polishing fluid is sprayed on the surface of product 200, to improve grinding effect.While grinding by polishing cloth, also by polishing cloth pair
It is cleaned on the surface of test sample 600.
The forming method of above-mentioned test sample can accurately prepare the test sample with small size target area, avoid pair
Grinding was caused in section to be measured, improved the success rate of test sample production, and reduce and prepare test sample by lapping mode
When limitation to target area size.
A specific embodiment of the invention also provides a kind of test sample formed using the above method.
Fig. 6 A and 6B are please referred to, Fig. 6 B is partial enlargement diagram.
The test sample 600 includes a prefabricated sample 200 ' comprising target area 103, the prefabricated 200 ' sample of sample
The top surface 201 of product is used as test surfaces, perpendicular to the thickness direction of the prefabricated sample 200 ', and exposes the target area
103 section to be measured 1031.
The prefabricated sample 200 ' can be a part of sample to be tested, and the sample to be tested includes body layer, the body layer
Inside it is formed with doped region and/semiconductor devices etc..The sample to be tested can also be including dielectric layer etc..The sample to be tested can be with
Bare chip to be formed with semiconductor devices or the structure in semiconductor devices forming process, can determine from wafer
Cuboid.The distance between the target area 103 of the prefabricated sample 200 ' and the side wall on thickness direction are more than or equal to 1 μm,
It avoids passing through when obtaining prefabricated sample 200 ' by the modes such as grinding or cutting to the sample to be tested, causes target area 103
Missing.
The test sample 600 further includes that the two sides side wall that is pasted on the 200 ' thickness direction of prefabricated sample accompanies piece
Wafer 400 ', it is described that 400 ' surface of wafer and the test surfaces of the prefabricated sample 200 ' is accompanied to flush, and consistency of thickness, it is small
In the thickness of monolithic bare silicon wafer.
It is described to accompany the test surfaces of wafer 400 ' and the prefabricated sample 200 ' by integral grinding, so that described accompany piece
The junction of the test surfaces of wafer 400 ' and the prefabricated sample 200 ' has continuous grinding marks.
In three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μm for the target area 103.?
In the specific embodiment, the target area 103 is a cuboid, at least one size in length, width and height
Less than or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.
The section to be measured 1031 of the target area 103 perpendicular to the prefabricated sample 200 ' thickness direction, it is described pre-
Surface on 200 ' thickness direction of sample preparation product is the side wall of prefabricated sample 200 '.Preferably, the prefabricated sample 200 ' is rectangular
The bodily form；Or the prefabricated sample 200 ' at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described
Between two opposite vertical sidewalls.
In this specific embodiment, described to accompany wafer 400 ' for cuboid, wafer 400 ' and institute are accompanied with described
It is identical with size to state the sidewall shape that prefabricated sample 200 ' is pasted.It is described that wafer 400 ' is accompanied laterally to be pasted on the prefabricated sample
On the vertical side wall of 200 ' any two, the target area 103 is between described two vertical side walls.
200 ' the side wall of prefabricated sample and described accompany are fixed between wafer 400 ' by glue-line.The glue-line can be
The glue-lines such as AB glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee the 200 ' side wall of prefabricated sample with
Described accompany fits closely between wafer 400 ', and the thickness of the glue-line is less than or equal to 1 μm.
In some embodiments, the prefabricated sample 200 ' and wafer 400 ' is accompanied integrally to can be used as test specimens
Product.
In the specific embodiment, the test sample 600 further includes semiconductor bottom plate 300 ', and semiconductor bottom plate 300 can
Think by the wafer that cuts and/or polish, the semiconductor bottom plate 300 ' as accompanied described in fixed and carrying wafer 400 ' and
The fixation wafer of prefabricated sample 200 '.
300 ' the surface of semiconductor bottom plate is fixed in the bottom surface of the 200 ' sample of prefabricated sample.In some specific implementations
In mode, fixed between the prefabricated sample 200 ' and the semiconductor bottom plate 300 ' by conducting resinl.In some specific implementations
In mode, the conducting resinl can be the viscoloid doped with metal, such as elargol, so that the prefabricated sample 200 ' and institute
Stating has good electric conductivity between semiconductor bottom plate 300 ', so as to by the semiconductor bottom plate 300 ' to described prefabricated
Print 200 ' applies voltage.
It is described that 400 ' bottom of wafer is accompanied also to be secured to the 300 ' surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 ' and the prefabricated print 200 ' avoids described accompanying wafer 400 ' and the prefabricated print 200 '
It is detached from.
The edge for accompanying wafer 400 ', prefabricated sample 200 ' and semiconductor bottom plate 300 ' flushes.Some specific
In embodiment, it is described accompany wafer 400 ', prefabricated print 200 ' and semiconductor bottom plate 300 ' a generally cuboid or
Other regular figures, convenient for being held or being moved during follow-up test.
The specific embodiment of the present invention also provides a kind of semiconductor structure test method.
Test sample 600 described in above-mentioned specific embodiment is formed using above-mentioned test sample preparation method first
(please referring to Fig. 6 A and 6B)；Using scanning capacitance capacitance microscopy, the section to be measured 1031 of the test sample 600 is surveyed
Examination, obtains the electrical parameter and/or physical characteristic information of the target area 103.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The accuracy of electrical testing can be improved, especially have to the accuracy for the electrical testing for needing direct contact measured section larger
Raising.
The semiconductor test can be the electrical testings such as capacity measurement, contact resistance test, or doping concentration
Test, the test of the physical features such as lattice pattern test.
In a specific embodiment, the semiconductor test is capacity measurement, will during carrying out capacity measurement
The test probe of the Scanning capacitance microscope is contacted with the section 1031 to be measured and is moved in a manner of rank scanning, together
When between the test probe and the test sample 600 plus a low-frequency ac electric field.
Voltage can be applied to the prefabricated sample 200 ' by the semiconductor bottom plate 300 ', so that the testing section
1031 are electrically connected to test voltage end.
It, can also be directly to the prefabricated sample when test sample only includes accompanying wafer 400 ' and prefabricated sample 200 '
200 ' apply voltage.
During the test probe scanning, is measured by hyperfrequency capacitance sensor and obtain capacitance and acquisition
The capacitance profile figure of target area 103.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The accuracy of electrical testing can be improved.
A specific embodiment of the invention also provides a kind of semiconductor test system.
The semiconductor test system includes tester table and test sample；Wherein test sample please refer to Fig. 6 A and
6B, Fig. 6 B are partial enlargement diagram.
The test sample 600 includes a prefabricated sample 200 ' comprising target area 103, the prefabricated 200 ' sample of sample
The top surface 201 of product is used as test surfaces, perpendicular to the thickness direction of the prefabricated sample 200 ', and exposes the target area
103 section to be measured 1031.
The prefabricated sample 200 ' can be a part of sample to be tested, and the sample to be tested includes body layer, the body layer
Inside it is formed with doped region and/semiconductor devices etc..The sample to be tested can also be including dielectric layer etc..The sample to be tested can be with
Bare chip to be formed with semiconductor devices or the structure in semiconductor devices forming process, can determine from wafer
Cuboid.The distance between the target area 103 of the prefabricated sample 200 ' and the side wall on thickness direction are more than or equal to 1 μm,
It avoids passing through when obtaining prefabricated sample 200 ' by the modes such as grinding or cutting to the sample to be tested, causes target area 103
Missing.
The test sample 600 further includes that the two sides side wall that is pasted on the 200 ' thickness direction of prefabricated sample accompanies piece
Wafer 400 ', it is described that 400 ' surface of wafer and the test surfaces of the prefabricated sample 200 ' is accompanied to flush, and consistency of thickness, it is small
In the thickness of monolithic bare silicon wafer.
It is described to accompany the test surfaces of wafer 400 ' and the prefabricated sample 200 ' by integral grinding, so that described accompany piece
The junction of the test surfaces of wafer 400 ' and the prefabricated sample 200 ' has continuous grinding marks.
In three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μm for the target area 103.?
In the specific embodiment, the target area 103 is a cuboid, at least one size in length, width and height
Less than or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.
The section to be measured 1031 of the target area 103 perpendicular to the prefabricated sample 200 ' thickness direction, it is described pre-
Surface on 200 ' thickness direction of sample preparation product is the side wall of prefabricated sample 200 '.Preferably, the prefabricated sample 200 ' is rectangular
The bodily form；Or the prefabricated sample 200 ' at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described
Between two opposite vertical sidewalls.
In this specific embodiment, described to accompany wafer 400 ' for cuboid, wafer 400 ' and institute are accompanied with described
It is identical with size to state the sidewall shape that prefabricated sample 200 ' is pasted.It is described that wafer 400 ' is accompanied laterally to be pasted on the prefabricated sample
On the vertical side wall of 200 ' any two, the target area 103 is between described two vertical side walls.
200 ' the side wall of prefabricated sample and described accompany are fixed between wafer 400 ' by glue-line.The glue-line can be
The glue-lines such as AB glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee the 200 ' side wall of prefabricated sample with
Described accompany fits closely between wafer 400 ', and the thickness of the glue-line is less than or equal to 1 μm.
In some embodiments, the prefabricated sample 200 ' and wafer 400 ' is accompanied integrally to can be used as test specimens
Product.
In the specific embodiment, the test sample 600 further includes semiconductor bottom plate 300 ', and semiconductor bottom plate 300 can
Think by the wafer that cuts and/or polish, the semiconductor bottom plate 300 ' as accompanied described in fixed and carrying wafer 400 ' and
The fixation wafer of prefabricated sample 200 '.
300 ' the surface of semiconductor bottom plate is fixed in the bottom surface of the 200 ' sample of prefabricated sample.In some specific implementations
In mode, fixed between the prefabricated sample 200 ' and the semiconductor bottom plate 300 ' by conducting resinl.In some specific implementations
In mode, the conducting resinl can be the viscoloid doped with metal, such as elargol, so that the prefabricated sample 200 ' and institute
Stating has good electric conductivity between semiconductor bottom plate 300 ', so as to by the semiconductor bottom plate 300 ' to described prefabricated
Print 200 ' applies voltage.
It is described that 400 ' bottom of wafer is accompanied also to be secured to the 300 ' surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 ' and the prefabricated print 200 ' avoids described accompanying wafer 400 ' and the prefabricated print 200 '
It is detached from.
The edge for accompanying wafer 400 ', prefabricated sample 200 ' and semiconductor bottom plate 300 ' flushes.Some specific
In embodiment, it is described accompany wafer 400 ', prefabricated print 200 ' and semiconductor bottom plate 300 ' a generally cuboid or
Other regular figures, convenient for being held or being moved during follow-up test.
In a specific embodiment, the semiconductor test system is capacitor, contact resistance or other electrical parameters
Test macro, the semiconductor test system can also for doping concentration, lattice structure test etc. physical features test macro.
For capacitor test system, the tester table includes Scanning capacitance microscope.The Scanning capacitance microscope packet
Include a test probe.During carrying out capacity measurement, the test probe of the Scanning capacitance microscope is used for and test sample
600 section to be measured 1031 is directly contacted and is moved in a manner of rank scanning, while Scanning capacitance microscope is also used to
Add a low-frequency ac electric field between the test probe and the test sample 600.The semiconductor bottom plate 300 ' can be passed through
Voltage is applied to the prefabricated sample 200 ', so that the testing section 1031 is electrically connected to test voltage end.Work as test sample
It only include that voltage directly can also be applied to the prefabricated sample 200 ' when accompanying wafer 400 ' and prefabricated sample 200 '.It is described
Capacitor test system further includes a hyperfrequency capacitance sensor, for measuring acquisition capacitance and obtaining target area 103
Capacitance profile figure.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The test result accuracy of the semiconductor test system can be improved.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (20)
1. a kind of preparation method of test sample characterized by comprising
A sample comprising target area is provided, the sample is ground by semiconductor samples to be measured, has single-wafer thick
Degree, the thickness direction of the section to be measured of the target area perpendicular to the sample；
Wafer, the surface for accompanying wafer and the sample are accompanied in two sides side wall adherency on the thickness direction of the sample
Surface flush；
Wafer and the sample surfaces is accompanied integrally to grind to described, until exposing to be measured section of the target area
Face, sample after grinding and accompanies wafer to be integrally used as test sample.
2. the preparation method of test sample according to claim 1, which is characterized in that the sample is cuboid.
3. the preparation method of test sample according to claim 1, which is characterized in that described to accompany wafer and the sample
The sidewall shape of stickup is identical with size.
4. the preparation method of test sample according to claim 1, which is characterized in that accompany platelet to described using polishing cloth
Round and sample surfaces are integrally ground.
5. the preparation method of test sample according to claim 4, which is characterized in that in process of lapping, in lapped face
Spray polishing fluid.
6. the preparation method of test sample according to claim 1, which is characterized in that the target area is in three-dimensional coordinate
In system, the size at least one coordinate direction is less than or equal to 1 μm.
7. the preparation method of test sample according to claim 1, which is characterized in that further include: by the bottom of the sample
Wafer is accompanied in the two sides side wall adherency that face is fixed on a fixed wafer and then on the thickness direction of the sample.
8. the preparation method of test sample according to claim 7, which is characterized in that the sample and the fixed wafer
Between fixed by conducting resinl.
9. the preparation method of test sample according to claim 7, which is characterized in that described that wafer bottom is accompanied to be fixed on
The fixed crystal column surface.
10. the preparation method of test sample according to claim 9, which is characterized in that described that wafer is accompanied to pass through a glue
Layer is adhered to the sample side wall, and the thickness of the glue-line is less than or equal to 1 μm.
11. the preparation method of test sample according to claim 1, which is characterized in that the sample surfaces and it is described to
It surveys the distance between section and is more than or equal to 1 μm.
12. the preparation method of test sample according to claim 1, which is characterized in that the target area of the sample with
The distance between side wall on thickness direction is more than or equal to 1 μm.
13. a kind of test sample characterized by comprising
One includes the sample of target area, the test surfaces of the sample perpendicular to the sample thickness direction and expose institute
State the section to be measured of target area；
The two sides side wall being pasted on the thickness of sample direction accompanies wafer, platelet circular surfaces and the sample of accompanying
Test surfaces flush, and consistency of thickness, respectively less than the thickness of monolithic bare silicon wafer.
14. test sample according to claim 13, which is characterized in that the test table for accompanying wafer Yu the sample
The junction in face has continuous grinding marks.
15. test sample according to claim 13, which is characterized in that the target area in three-dimensional system of coordinate, until
Size on a few coordinate direction is less than or equal to 1 μm.
16. test sample according to claim 13, which is characterized in that further include fixed wafer, the bottom surface of the sample
It is fixed on the fixed crystal column surface.
17. test sample according to claim 16, which is characterized in that the sample bottom surface and the fixed crystal column surface
Between fixed by conducting resinl.
18. test sample according to claim 16, which is characterized in that described that wafer bottom is accompanied to be fixed on the fixation
Crystal column surface.
19. test sample according to claim 18, which is characterized in that described that wafer is accompanied to be adhered to institute by a glue-line
Sample side wall is stated, the thickness of the glue-line is less than or equal to 1 μm.
20. test sample according to claim 13, which is characterized in that on the target area and thickness direction of the sample
The distance between side wall be more than or equal to 1 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910099456.0A CN109633209A (en) | 2019-01-31 | 2019-01-31 | Test sample and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910099456.0A CN109633209A (en) | 2019-01-31 | 2019-01-31 | Test sample and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109633209A true CN109633209A (en) | 2019-04-16 |
Family
ID=66064658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910099456.0A Pending CN109633209A (en) | 2019-01-31 | 2019-01-31 | Test sample and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109633209A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111257071A (en) * | 2020-01-17 | 2020-06-09 | 胜科纳米（苏州）有限公司 | Preparation method of sample for dynamic secondary ion mass spectrometer and prepared sample |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005300502A (en) * | 2004-04-16 | 2005-10-27 | Hitachi High-Technologies Corp | Method for preparing analytical sample |
| CN102023108A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing transmission electron microscope sample |
| CN103336239A (en) * | 2013-06-03 | 2013-10-02 | 上海宏力半导体制造有限公司 | A wafer testing method |
| CN103528869A (en) * | 2013-10-28 | 2014-01-22 | 北京大学 | Manufacturing method for sample suitable for observation of unconventional oil and gas by ten-thousand-time scanning electron microscope |
| CN103698170A (en) * | 2012-09-27 | 2014-04-02 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of TEM sample |
| CN104037076A (en) * | 2014-06-23 | 2014-09-10 | 昆山永续智财技术服务有限公司 | Reverse technology preparation method for grinding sample of chip |
| CN105004588A (en) * | 2015-07-10 | 2015-10-28 | 首钢总公司 | Alloy-galvanized layer scanning electron microscope sectioned sample precision making method |
| CN107702962A (en) * | 2017-11-21 | 2018-02-16 | 长江存储科技有限责任公司 | Preparation method for the sample of Scanning capacitance microscope and the sample using this method preparation |
| CN108803264A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The determination method of multiple alignment marks being centrally placed with photoetching position on wafer |
-
2019
- 2019-01-31 CN CN201910099456.0A patent/CN109633209A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005300502A (en) * | 2004-04-16 | 2005-10-27 | Hitachi High-Technologies Corp | Method for preparing analytical sample |
| CN102023108A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing transmission electron microscope sample |
| CN103698170A (en) * | 2012-09-27 | 2014-04-02 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of TEM sample |
| CN103336239A (en) * | 2013-06-03 | 2013-10-02 | 上海宏力半导体制造有限公司 | A wafer testing method |
| CN103528869A (en) * | 2013-10-28 | 2014-01-22 | 北京大学 | Manufacturing method for sample suitable for observation of unconventional oil and gas by ten-thousand-time scanning electron microscope |
| CN104037076A (en) * | 2014-06-23 | 2014-09-10 | 昆山永续智财技术服务有限公司 | Reverse technology preparation method for grinding sample of chip |
| CN105004588A (en) * | 2015-07-10 | 2015-10-28 | 首钢总公司 | Alloy-galvanized layer scanning electron microscope sectioned sample precision making method |
| CN107702962A (en) * | 2017-11-21 | 2018-02-16 | 长江存储科技有限责任公司 | Preparation method for the sample of Scanning capacitance microscope and the sample using this method preparation |
| CN108803264A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The determination method of multiple alignment marks being centrally placed with photoetching position on wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111257071A (en) * | 2020-01-17 | 2020-06-09 | 胜科纳米（苏州）有限公司 | Preparation method of sample for dynamic secondary ion mass spectrometer and prepared sample |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109870336A (en) | Semiconductor test system and its test method | |
| US6809533B1 (en) | Quantitative imaging of dielectric permittivity and tunability | |
| US11293940B2 (en) | Scanning sensor having a spin defect | |
| US20060152232A1 (en) | Method and apparatus for inspection of high frequency and microwave hybrid circuits and printed circuit boards | |
| US6201401B1 (en) | Method for measuring the electrical potential in a semiconductor element | |
| Sonnenfeld et al. | Semiconductor topography in aqueous environments: Tunneling microscopy of chemomechanically polished (001) GaAs | |
| US6091248A (en) | Method for measuring the electrical potential in a semiconductor element | |
| CN102654516B (en) | Displacement detecting mechanism and use the sweep type probe microscope of this displacement detecting mechanism | |
| CN108802431A (en) | A kind of detection method of the scanning probe microscopy with magnetic-electric signal detecting function | |
| CN100543448C (en) | Scanning tunnel microscope and scanning microelectrode coupling measuring system and measuring technique thereof | |
| Airaksinen | Silicon wafer and thin film measurements | |
| US9157935B2 (en) | Apparatus and method for endpoint detection during electronic sample preparation | |
| CN107014663A (en) | Suitable for the sample method for making sample of mineralogy parameter automatic measurement system | |
| CN109633209A (en) | Test sample and preparation method thereof | |
| RU2466381C2 (en) | System and method of detecting local mechanical stress in integrated devices | |
| CN109443295B (en) | Method for testing roughness of Al metallization layer on surface of automobile-grade IGBT chip | |
| US11112427B2 (en) | Method and tip substrate for scanning probe microscopy | |
| EP1212625A1 (en) | Quantitative imaging of dielectric permittivity and tunability | |
| JP2017034025A (en) | Processing damage evaluation method of semiconductor wafer | |
| Michalas et al. | Scanning microwave microscopy for nanoscale characterization of semiconductors: De-embedding reflection contact mode measurements | |
| CN112414876B (en) | Method for rapidly detecting depth of damaged layer of substrate material | |
| TWI311328B (en) | Electron microscopy , methods to determine the contact point and the contact of the probe | |
| Yee et al. | Application of atomic force microscopy in IC/discrete failure analysis | |
| Polovodov et al. | Building a near-field scanning millimeter-wave microscope integrated in a scanning electron microscope | |
| RU2415444C2 (en) | Method to increase validity of results of analysing solid body surface by atomic power microscopy |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190416 |