CN104037076A - Reverse technology preparation method for grinding sample of chip - Google Patents
Reverse technology preparation method for grinding sample of chip Download PDFInfo
- Publication number
- CN104037076A CN104037076A CN201410292930.9A CN201410292930A CN104037076A CN 104037076 A CN104037076 A CN 104037076A CN 201410292930 A CN201410292930 A CN 201410292930A CN 104037076 A CN104037076 A CN 104037076A
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- CN
- China
- Prior art keywords
- chip
- sheet
- ground
- accompanying
- grinding
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
Abstract
The invention discloses a reverse technology preparation method for a grinding sample of a chip. The reverse technology preparation method for the grinding sample of the chip includes: firstly, enabling a surface of the chip, to be ground, to face down, and placing the chip on a flat surface; then respectively placing rectangular accompanying pieces all around the chip and aligning each rectangular accompanying piece with each edge of the chip; dripping adhesive capable of solidifying onto the chip and the accompanying pieces; finally placing a fixing jig on the chip and the accompanying pieces, and placing the chip and the accompanying pieces in static mode until solidification is finished. According to the reverse technology preparation method for the grinding sample of the chip, a coplanar effect can be achieved during the grinding process regardless of height differences of the accompanying pieces due to the fact that the sample is prepared by placing the surfaces of the chip and the accompanying pieces downward and locating the surfaces of the chip and the accompanying pieces in the same plane, and due to the fact that the edges of the chip to be ground are at the same height as the accompanying pieces, the edges and the center of the chip to be ground bear commensurate pressure, grinding speed of the edges of the chip is commensurate with grinding speed of the center of the chip, and grinding flatness of the chip is excellent, and furthermore due to the fact that a unilateral alignment arrangement method is adopted among the rectangular accompanying pieces and the chip, the rectangular accompanying pieces can adapt to random rectangular chips, a seamless butt joint is generated, and the reverse technology preparation method for the grinding sample of the chip prevents an gap from being generated between the chip and each accompanying piece.
Description
Technical field
The invention belongs to chip manufacture technology field, relate in particular to a kind of ground sample preparation method of chip reverse process.
Background technology
In integrated circuit fabrication process; reverse process is to understand self circuit and the most effective approach of competitor's circuit; and then as the important method of circuit studies and improved circuit; in traditional die reverse process, grind as going one of effective way of layer, but during traditional grinding chip; because chip edge is not protected; when grinding, to bear pressure larger at edge, often causes chip edge overgrinding, and form the uneven situation of chip.
Summary of the invention
The object of the present invention is to provide a kind of ground sample preparation method of chip reverse process; while being intended to solve chip grinding; because chip edge is not protected, when grinding, to bear pressure larger at edge, often causes chip edge overgrinding; and the uneven problem of formation chip; and optimize the arrangement mode of accompanying sheet and chip, and can make any rectangle accompany sheet, can adapt to any rectangular dies; form slitless connection, avoid chip and accompany between sheet have space to produce.
The present invention is achieved in that a kind of ground sample preparation method of chip reverse process, first, is positioned over a flat surfaces by chip surface to be ground down; Again the sheet of accompanying of rectangle is positioned over respectively to aliging of chip all around and with chip is monolateral; Curable adhesive agent dripped in chip again and accompany on sheet; After finally putting that fixed jig is standing and solidifying, complete.
Further, described chip is that it is shaped as rectangle according to the formed Gui sheet of semiconductor technology.
Further, the described sheet of accompanying is that the rectangle corresponding with chip form to be ground accompanied sheet, and thickness is regardless of, and material can be the material of resistance to grinding, as pottery or metal, but take Gui sheet as best.
Further, described rectangle is accompanied sheet, and it adopts the monolateral aligning method aliging with chip, can make any rectangle accompany sheet, can adapt to any rectangular dies, forms slitless connection, and avoiding chip and accompanying between sheet has space to produce.
Further, described curable adhesive agent and fixed jig, as fixing chip to be ground and accompany sheet to use.
Further, the sample after having prepared, it accompanies sheet and chip surface to be ground for having plane surface altogether.
effect gathers
The ground sample preparation method of chip reverse process of the present invention, due to chip with accompany sheet surface under same plane, to prepare sample all down, no matter accompany sheet difference in height, all can when grinding, reach coplanar effect; Due to chip edge to be ground with accompany sheet with high, grinding Shi Yu chip center, to bear pressure suitable, grinding rate is suitable, makes chip grind flatness better; Described rectangle is accompanied sheet, and it adopts the monolateral aligning method aliging with chip, can make any rectangle accompany sheet, can adapt to any rectangular dies, forms slitless connection, and avoiding chip and accompanying between sheet has space to produce.
Accompanying drawing explanation
Fig. 1 is normal chip and the chip sides enlarged drawing that the embodiment of the present invention provides;
Fig. 2 is the traditional die that provides of the embodiment of the present invention while grinding, and chip bears grinding pad pressure schematic diagram;
Fig. 3 is the traditional die that provides of the embodiment of the present invention while grinding, and chip bears grinding pad pressure and causes chip edge overgrinding schematic diagram;
Fig. 4 is the sample preparation flow chart that the embodiment of the present invention provides;
Fig. 5 be the embodiment of the present invention provide when grinding, chip uniform stressed schematic diagram;
In figure: 1, chip; 2, fixed jig; 3, grinding pad; 4, accompany sheet; 4-1, first accompanies sheet; 4-2, second accompanies sheet; 4-3, escort services' sheet; 4-4, the 4th accompanies sheet; 5, curable adhesive agent.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Fig. 1 is normal chip and chip sides enlarged drawing; Chip 1 bottom surface is that integrated circuit technology forms multilayer circuit figure; Fig. 2 is traditional die while grinding, and chip bears grinding pad pressure schematic diagram, 2 fixed jigs that are carries chips, and 3 grinding pads that use for process of lapping, in figure, display chip edge is subject to the situation of the more pressure of grinding pad; When Fig. 3 is traditional die grinding, chip bears grinding pad pressure and causes chip edge overgrinding schematic diagram.
As shown in Figure 4, the present invention is achieved in that first by chip 1 surface to be ground down, is positioned over a flat surfaces, as glass; By first of rectangle, accompany sheet 4-1 again, second accompanies sheet 4-2, escort services' sheet 4-3, and the 4th accompanies sheet 4-4 to be positioned over respectively aliging of chip 1 all around and with chip 1 is monolateral; Again by 5 of curable adhesive agents in chip 1 and accompany on sheet 4; After finally putting that fixed jig 2 is standing and solidifying, complete.
Further, described chip 1 is that it is shaped as rectangle according to the formed Gui sheet of semiconductor technology.
Further, the described sheet 4 of accompanying is that the rectangle corresponding with chip 1 shape to be ground accompanied sheet, and thickness is regardless of, and material can be the material of resistance to grinding, as pottery or metal, but take Gui sheet as best.
Further, described rectangle is accompanied sheet 4, and it adopts the monolateral aligning method aliging with chip 1, can make any rectangle accompany sheet 4, can adapt to any rectangular dies 1, forms slitless connection, avoids chip 1 and accompanies 4 of sheets to have space to produce.
Further, described curable adhesive agent 5 and fixed jig 2, as fixing chip 1 to be ground and accompany sheet 4 use.
Further, the sample after having prepared, it accompanies sheet 4 and chip to be ground 1 surface is to have plane surface altogether, avoids chip edge to be ground because pressure is inhomogeneous, to cause the overground problem of chip edge.
Fig. 5 is the present invention when grinding, chip uniform stressed schematic diagram; Sample after having prepared, it accompanies sheet 4 and chip to be ground 1 surface is to have plane surface altogether, can avoid chip edge because pressure is inhomogeneous, to cause the overground problem of chip edge during grinding.
The ground sample preparation method of chip reverse process of the present invention, due to chip 1 with accompany sheet 4 surfaces under same plane, to prepare sample all down, no matter accompany sheet 4 differences in height, all can when grinding, reach coplanar effect; Due to chip to be ground 1 edge with accompany sheet 4 with high, when grinding, to bear pressure suitable with chip 1 center, grinding rate is suitable, makes chip 1 grinding flatness better; Described rectangle is accompanied sheet 4, and it adopts the monolateral aligning method aliging with chip 1, can make any rectangle accompany sheet 4, can adapt to any rectangular dies 1, forms slitless connection, avoids chip 1 and accompanies 4 of sheets to have space to produce.
Although above-mentioned, by reference to the accompanying drawings the specific embodiment of the present invention is described; but be not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various modifications that performing creative labour can make or distortion still within protection scope of the present invention.
Claims (6)
1. a ground sample preparation method for chip reverse process, is characterized in that, first the ground sample preparation method of described chip reverse process, is positioned over a flat surfaces by chip surface to be ground down; Again the sheet of accompanying of rectangle is positioned over respectively to aliging of chip all around and with chip is monolateral; Curable adhesive agent dripped in chip again and accompany on sheet; After finally putting that fixed jig is standing and solidifying, complete.
2. the ground sample preparation method of chip reverse process as claimed in claim 1, is characterized in that, described chip is that it is shaped as rectangle according to the formed Gui sheet of semiconductor technology.
3. the ground sample preparation method of chip reverse process as claimed in claim 1, is characterized in that, the described sheet of accompanying is that the rectangle corresponding with chip form to be ground accompanied sheet, thickness is regardless of, material can be the material of resistance to grinding, as pottery or metal, but take Gui sheet as best.
4. the ground sample preparation method of chip reverse process as claimed in claim 1, it is characterized in that, described rectangle is accompanied sheet, it adopts the monolateral aligning method aliging with chip, can make any rectangle accompany sheet, can adapt to any rectangular dies, form slitless connection, avoid chip and accompany between sheet have space to produce.
5. the ground sample preparation method of chip reverse process as claimed in claim 1, is characterized in that, described curable adhesive agent and fixed jig, as fixing chip to be ground and accompany sheet to use.
6. the ground sample preparation method of chip reverse process as claimed in claim 1, is characterized in that, the sample after having prepared, and it accompanies sheet and chip surface to be ground for having plane surface altogether.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410292930.9A CN104037076A (en) | 2014-06-23 | 2014-06-23 | Reverse technology preparation method for grinding sample of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410292930.9A CN104037076A (en) | 2014-06-23 | 2014-06-23 | Reverse technology preparation method for grinding sample of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104037076A true CN104037076A (en) | 2014-09-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410292930.9A Pending CN104037076A (en) | 2014-06-23 | 2014-06-23 | Reverse technology preparation method for grinding sample of chip |
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| CN (1) | CN104037076A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633209A (en) * | 2019-01-31 | 2019-04-16 | 长江存储科技有限责任公司 | Test sample and preparation method thereof |
| CN109870336A (en) * | 2019-01-31 | 2019-06-11 | 长江存储科技有限责任公司 | Semiconductor test system and its test method |
| CN114750018A (en) * | 2022-06-13 | 2022-07-15 | 合肥晶合集成电路股份有限公司 | Chip layer removing device and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH097986A (en) * | 1995-06-14 | 1997-01-10 | Mitsubishi Materials Shilicon Corp | Semiconductor wafer grinding method and apparatus |
| CN1883881A (en) * | 2006-05-26 | 2006-12-27 | 中国科学院上海技术物理研究所 | Surface polishing method for protective side edge of group II-VI semiconductor material |
| US20090117832A1 (en) * | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Wafer polishing method |
| CN201519904U (en) * | 2009-11-17 | 2010-07-07 | 宜硕科技(上海)有限公司 | Chip stripping device |
| CN102398313A (en) * | 2010-09-14 | 2012-04-04 | 株式会社迪思科 | Optical device wafer processing method |
| TW201320171A (en) * | 2011-11-14 | 2013-05-16 | Rexchip Electronics Corp | Processing method for the planarization of a semiconductor device |
-
2014
- 2014-06-23 CN CN201410292930.9A patent/CN104037076A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH097986A (en) * | 1995-06-14 | 1997-01-10 | Mitsubishi Materials Shilicon Corp | Semiconductor wafer grinding method and apparatus |
| CN1883881A (en) * | 2006-05-26 | 2006-12-27 | 中国科学院上海技术物理研究所 | Surface polishing method for protective side edge of group II-VI semiconductor material |
| US20090117832A1 (en) * | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Wafer polishing method |
| CN201519904U (en) * | 2009-11-17 | 2010-07-07 | 宜硕科技(上海)有限公司 | Chip stripping device |
| CN102398313A (en) * | 2010-09-14 | 2012-04-04 | 株式会社迪思科 | Optical device wafer processing method |
| TW201320171A (en) * | 2011-11-14 | 2013-05-16 | Rexchip Electronics Corp | Processing method for the planarization of a semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633209A (en) * | 2019-01-31 | 2019-04-16 | 长江存储科技有限责任公司 | Test sample and preparation method thereof |
| CN109870336A (en) * | 2019-01-31 | 2019-06-11 | 长江存储科技有限责任公司 | Semiconductor test system and its test method |
| CN114750018A (en) * | 2022-06-13 | 2022-07-15 | 合肥晶合集成电路股份有限公司 | Chip layer removing device and method |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140910 |
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| RJ01 | Rejection of invention patent application after publication |