CN109870336A - Semiconductor test system and its test method - Google Patents
Semiconductor test system and its test method Download PDFInfo
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- CN109870336A CN109870336A CN201910100813.0A CN201910100813A CN109870336A CN 109870336 A CN109870336 A CN 109870336A CN 201910100813 A CN201910100813 A CN 201910100813A CN 109870336 A CN109870336 A CN 109870336A
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Abstract
The present invention relates to a kind of semiconductor test system and its test methods, provide a sample to be tested, and the sample to be tested includes target area to be tested；The sample to be tested is ground, forms prefabricated sample, the thickness and single-wafer consistency of thickness of the prefabricated sample, the thickness direction of the section to be measured of the target area perpendicular to the prefabricated sample；Wafer is accompanied in the two sides side wall stickup of the prefabricated sample, the surface for accompanying wafer is flushed with the surface of the prefabricated sample；It accompanies the surface of platelet circular surfaces and the prefabricated sample by described plane is ground as a whole, until exposing the section to be measured of the target area；The section to be measured is tested, the electrical property and/or object features information of the target area are obtained.Above-mentioned semiconductor test system and its test method can be improved the accuracy of semiconductor test results.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor test system and its test methods.
Background technique
After atomic force microscope (SAFM) is by invention, it is widely used in the sections such as physics, chemistry, biology and material
Field, and the Scanning capacitance microscope (SCM) derived is also referred to as exploitation, manufacture and examines one kind of semiconductor devices very
Important and necessary means, especially for the inspection of the example injection technology of semiconductor devices.
When atomic force microscope (SCM) work is under contact mode, Scanning capacitance microscope (SCM) use can be used as,
Add a low-frequency ac electric field between conductive afm tip and semiconductor samples, the free carrier in sample is periodically inhaled by needle point
Draw or repel, the capacitor that needle point is constituted with semiconductor samples also changes therewith, this capacitance variations utilizes hyperfrequency resonant capacitor
Sensor obtains to measure, and test result can characterize the doping characteristic on scanned surface.Due in test process, afm tip
It is directly contacted with the surface of sample, it is therefore, whether particularly significant comprising target area in the scanned region of sample.
Test sample passes through artificial grind away and prepares at present, by diamond sand paper grinding semiconductor device to destination layer, so
Cloth polishing and section is cleaned with polishing again afterwards.The sand particle size of diamond sand paper most thin at present is 0.1 μm or so, works as target area
Size in μm rank, basic in grinding control there is no problem, can accurately expose target area section；But once
Target area size is less than 1 μm, especially in 200nm or less, it is easy to generate grinding；Diamond sand paper crystalline substance can not accurately be ground
It is milled to destination layer, or can only probabilistic be ground to destination layer.Also, polishing cleaning is carried out using polishing cloth subsequent
When, although can only grind away very thin one layer, for the target area of size originally very little, also easily lead to target
Region, which is crossed, grinds.
Therefore, in the prior art, larger using target area size limitation of the artificial grind away preparation for sample, it can prepare
Sample scope it is smaller, cause the test scope of semiconductor test limited, and test structure accuracy and need further to mention
It is high.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of semiconductor test system and its test methods, improve and survey
The test result accuracy of test system.
Technical solution of the present invention provides a kind of semiconductor test method, comprising: a sample to be tested is provided, it is described to test sample
Product include target area to be tested；The sample to be tested is ground, prefabricated sample is formed, the target area is located at institute
It states in prefabricated sample, and the thickness of the prefabricated sample and single-wafer consistency of thickness, the section to be measured of the target area is hung down
It is directly the side wall of prefabricated sample in the surface on the thickness direction of the prefabricated sample, the prefabricated thickness of sample direction；Institute
Wafer is accompanied in the two sides side wall stickup for stating prefabricated sample, and the thickness for accompanying wafer is consistent with the prefabricated thickness of sample, institute
It states and the surface of wafer and the surface of the prefabricated sample is accompanied to flush；By the table for accompanying platelet circular surfaces and the prefabricated sample
Plane is ground as a whole in face, until exposing the section to be measured of the target area；By accompanying after the grinding
Wafer and prefabricated sample are integrally used as test sample, test the section to be measured, obtain the electricity of the target area
Property and/or physical characteristic information.
Optionally, the semiconductor test is capacity measurement.
Optionally, during the capacity measurement, by the test probe of the Scanning capacitance microscope with it is described to be measured
Section is contacted and is moved in a manner of rank scanning, while adding a low frequency between the test probe and the test sample
AC field.
Optionally, platelet circular surfaces and the surface of the prefabricated sample are accompanied to grind to described using polishing cloth.
Optionally, further includes: before wafer is accompanied in the side wall stickup of the prefabricated sample, by the bottom of the prefabricated sample
Semiconductor backplate surface is fixed in face.
Optionally, it is fixed between the prefabricated sample and the semiconductor bottom plate by conducting resinl.
Optionally, described that wafer bottom is accompanied also to be secured to the semiconductor backplate surface.
Optionally, the prefabricated sample side wall and described accompany are fixed between wafer by glue-line, the thickness of the glue-line
Less than or equal to 1 μm.
Optionally, further includes: accompany platelet circular surfaces and the surface of the prefabricated sample to grind as a whole for described
Before, it accompanies wafer to be polishing to semiconductor bottom edge to flush by described.
Optionally, described to accompany wafer and semiconductor bottom plate for identical material.
Optionally, in three-dimensional system of coordinate, the length at least on a coordinate direction is less than or equal to 1 for the target area
μm。
Optionally, the distance between the prefabricated sample surfaces and the section to be measured are more than or equal to 1 μm；The target area
The distance between side wall of domain and the prefabricated sample is more than or equal to 1 μm.
Technical solution of the present invention also provides a kind of semiconductor test system, comprising: test sample and tester table；It is described
Sample to be tested includes: a prefabricated sample comprising target area, and the test surfaces of the prefabricated sample are perpendicular to the pre- sample preparation
The thickness direction of product and the section to be measured for exposing the target area；It is pasted on the two sides on the prefabricated thickness of sample direction
Side wall accompanies wafer, described that platelet circular surfaces and the test surfaces of the prefabricated sample is accompanied to flush, and consistency of thickness, respectively less than
The thickness of monolithic bare silicon wafer；The tester table obtains the mesh for testing the section to be measured of the test sample
Mark the electrical property and/or physical characteristic information in region.
Optionally, the tester table includes Scanning capacitance microscope, the probe of the Scanning capacitance microscope be used for
The section to be measured contact, and being moved in a manner of rank scanning, at the same the test probe and the test sample it
Between plus a low-frequency ac electric field.
Optionally, the tester table further include: hyperfrequency capacitance sensor, for measuring the capacitor for obtaining target area
Value.
Optionally, the junction of the test surfaces for accompanying wafer and the prefabricated sample has continuous grinding marks
Mark.
Optionally, in three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μ for the target area
m。
Optionally, the test sample further includes semiconductor bottom plate, and the bottom surface of the prefabricated sample, which is fixed on, described partly leads
Body backplate surface；It is described that wafer bottom is accompanied to be fixed on the semiconductor backplate surface.
Optionally, it is fixed between the prefabricated sample bottom surface and the semiconductor backplate surface by conducting resinl.
Optionally, described that wafer is accompanied to be adhered to the prefabricated sample side wall by a glue-line, the thickness of the glue-line is small
In equal to 1 μm.
Optionally, the target area is more than or equal to the distance between the side wall on the thickness direction of the prefabricated sample
1μm。
Semiconductor test system and test method of the invention passes through to the test sample for being prepared with complete section to be measured
It is tested, the test sample includes complete target area, so as to improve the test of the semiconductor test system
As a result accuracy.
Detailed description of the invention
Fig. 1 to Fig. 6 B is the structural schematic diagram of the preparation process of the test sample of the embodiment of the invention.
Specific embodiment
With reference to the accompanying drawing to test sample provided by the invention and preparation method thereof, semiconductor test system and its test
The specific embodiment of method elaborates.
Fig. 1 to Fig. 6 B is please referred to, is the structural representation of the preparation process of the test sample of the embodiment of the invention
Figure.
Referring to FIG. 1, providing a sample to be tested 100 comprising target area.
Doped region and/semiconductor devices etc. are formed in the sample to be tested 100.The sample to be tested 100 may include
Dielectric layer, semiconductor layer, metal layer etc..The sample to be tested 100 can be to be formed with the bare chip of semiconductor devices or half
Structure in conductor device forming process can be the cuboid determined from wafer.When needs are in the sample to be tested 100
A certain region when being tested, need through abrasive article region exposure to be tested.
In the specific embodiment, it is formed with semiconductor devices 102 in the sample to be tested 100, needs partly to lead to described
Target area 103 in body device 102 is tested.The test can be the doping concentration of detection target area 103, capacitor
The electrical property features such as value.
As the integrated level of integrated circuit improves, the size reduction of semiconductor devices 102, target area 103 to be detected
As a part of semiconductor devices 102, size is also further reduced, and how accurately to expose the section to be measured of target area,
It is the key that setup test sample.
In a specific embodiment of the invention, for the length in three-dimensional system of coordinate, at least on a coordinate direction
Degree is less than or equal to 1 μm of sample to be tested 100, can not accurately expose the section to be measured of target area by directly grinding.At this
In specific embodiment, the target area 103 is a cuboid, at least one size is small in length, width and height
In or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.Certainly, for mesh
In the case that size on three directions in mark region 103 is all larger than 1 μm, the test sample system in the specific embodiment of the invention
Preparation Method is equally applicable.
Fig. 2A and 2B are please referred to, wherein Fig. 2 B is the diagrammatic cross-section of the secant AA ' along Fig. 2A.
The sample to be tested 100 (please referring to Fig. 1) is ground, prefabricated sample 200, the target area 103 are formed
In the prefabricated sample 200, and the thickness h of the prefabricated sample 200 and monolithic bare silicon wafer consistency of thickness, the target area
The section to be measured 1031 in domain 103 perpendicular to the prefabricated sample 200 thickness direction, on prefabricated 200 thickness direction of sample
Surface be prefabricated sample 200 side wall.
Specifically, according to the domain structure of the semiconductor devices in the sample to be tested 100, it can be determined that go out target area
Approximate location locating for 103.According to approximate location of the target area 103 in sample to be tested 100, to the sample to be tested
100 are ground.When target area 103 and the sample to be tested surface are larger, the sand paper of larger particles partial size can be used
It is quickly ground, to improve grinding efficiency.Observe target area 103 close to test sample by modes such as Electronic Speculum, microscopes
Stop grinding when 100 surface of product.Multiple surfaces of sample to be tested 100 can be ground around the target area 103, most
End form is equal to the prefabricated sample 200 of monolithic bare silicon wafer thickness at thickness.Preferably, the prefabricated sample 200 is cuboid；Or
Prefabricated sample 200 described in person at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described two opposite
Vertical sidewall between.The prefabricated sample 200 also has the top surface 201 and bottom surface 202 parallel with the section 1031 to be measured.
In order to avoid grinding was caused in the section to be measured 1031 to target area 103, need to the section 1031 to be measured
The distance between prefabricated 200 surface of sample is controlled.In a specific embodiment of the invention, the prefabricated sample 200
Surface, including multiple side walls and top surface 201 and bottom surface 202, the distance between described section 1031 to be measured is more than or equal to 1
μm.It in the specific embodiment, can be controlled by process of lapping, so that the target area 103 is located at prefabricated thickness of sample
Near medium position on direction.In other specific embodiments, can also suitably reduce the section to be measured 1031 with it is prefabricated
The top surface 201 the distance between parallel with the section 1031 to be measured in sample 200, it is described to be measured to reduce subsequent grinding exposure
The time in section 1031.
Referring to FIG. 3, semiconductor bottom plate 300 is fixed in the bottom surface 202 (please referring to Fig. 2 B) of the prefabricated sample 200
Surface.
The semiconductor bottom plate 300 can be for by the wafer cut, the size of the semiconductor bottom plate 300 be much larger than institute
The size for stating prefabricated print 200, as the loading plate of prefabricated print 200, convenient for subsequently through the mobile institute of mechanical or hand-held
It states prefabricated sample 200 or the prefabricated sample 200 is handled.
In a specific embodiment of the invention, pass through conduction between the prefabricated sample 200 and the semiconductor bottom plate 300
Glue is fixed.In some embodiments, the conducting resinl can be the viscoloid doped with metal, such as elargol, make
Obtaining has good electric conductivity between the prefabricated sample 200 and the semiconductor bottom plate 300, so as to partly be led by described
Body bottom plate 300 applies voltage to the prefabricated print 200.
The semiconductor bottom plate can be adhered to after the 202 surface coating colloid of bottom surface of the prefabricated sample 200
300 surfaces, then solidified by modes such as heating.
Referring to FIG. 4, wafer 400 is accompanied in the two sides side wall stickup in the prefabricated sample 200, it is described to accompany wafer 400
Thickness and prefabricated 200 consistency of thickness of sample, the surface on the surface for accompanying wafer 400 and the prefabricated sample 200
It flushes.
It is described accompany wafer 400 can for bare silicon wafer cut after part wafer, it may have the thickness of monolithic bare silicon wafer.?
In a specific embodiment of the invention, it is identical material with the semiconductor bottom plate 300, is monocrystalline silicon wafer crystal.In the tool
It is described to accompany wafer 400 for cuboid in body embodiment, accompany wafer 400 and the prefabricated sample 200 to paste with described
Sidewall shape it is identical with size.It is described that wafer 400 is accompanied laterally to be pasted on the vertical side of 200 any two of prefabricated sample
On wall, the target area is between described two vertical side walls.
200 side wall of prefabricated sample and described accompany are fixed between wafer 400 by glue-line.The glue-line can be AB
The glue-lines such as glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee 200 side wall of prefabricated sample and institute
It states to accompany and be fitted closely between wafer 400, the thickness of the glue-line is less than or equal to 1 μm.
It is described that 400 bottom of wafer is accompanied also to be secured to 300 surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 and the prefabricated print 200 avoids described accompanying wafer 400 with the prefabricated print 200 rear
In continuous process of lapping, it is detached from.Also, during accompanying wafer 400 described in the stickup, with the semiconductor bottom plate 300
As loading plate, height fall can be generated between wafer 400 and the top surface 201 of the prefabricated print 200 to avoid described accompany,
Reduce the difficulty that wafer 400 is accompanied described in pasting.The size for accompanying wafer 400 is less than the ruler of the semiconductor bottom plate 300
It is very little, it is fully located on the semiconductor bottom plate 300, so that the semiconductor bottom plate 300 is capable of providing preferable supporting effect.
In other specific embodiments, the semiconductor bottom plate 300 can not also be provided, is forming the prefabricated sample
After 200, directly the prefabricated print 200 side wall paste described in accompany wafer 400.
Referring to FIG. 5, accompanying wafer 400 to be polishing to semiconductor bottom plate 300 (please referring to Fig. 4) edge to flush by described.
It can be ground by diamond sand paper or by blade dicing methods, the uncovered area of removal semiconductor bottom plate 300
Domain so that polishing after semiconductor bottom plate 300 ', accompany wafer 400 and 200 edge of prefabricated print to flush.Polishing can be passed through
It is described to accompany wafer 400 and semiconductor bottom plate 300, so that described accompany wafer 400, prefabricated print 200 and semiconductor bottom plate
A 300 generally cuboids or other regular figures, convenient for being held or being moved in subsequent polishing and test process.
If in other specific embodiments, not providing the semiconductor bottom plate 300, wafer 400 can be accompanied by selection
Shape and size so that described accompany wafer 400 and the generally cuboid of prefabricated print 200 or other regular figures.
Fig. 6 A and 6B are please referred to, accompanies (the please referring to Fig. 5) surface of wafer 400 and the prefabricated sample 200 (please join for described
Examine Fig. 5) plane is ground as a whole for top surface 201 (please referring to Fig. 5), until exposing the target area 103
Section to be measured 1031；Prefabricated sample 200 ' after grinding accompanies wafer 400 ' and semiconductor bottom plate 300 ' whole as surveying
Test agent 600.Fig. 6 B is the partial enlargement diagram of 1031 region of section to be measured.
In the lesser situation of 103 size of target area, when being, for example, less than 1 μm, piece is accompanied to described using polishing cloth
(the please referring to Fig. 5) surface of wafer 400 and the top surface 201 (please referring to Fig. 5) of prefabricated sample 200 (please referring to Fig. 5) are ground.By
It is larger in the grinding precision of polishing cloth, grinding can be effectively avoided, control grinding depth can be stopped at accurately described to be measured
1031 position of section.But since polishing cloth is easily-deformable, ground flat and around have difference in height when, be easy grinding
The problem of horizontal edge generates fillet, leads to section missing to be measured and lapped face out-of-flatness.In specific implementation of the invention
In mode, the top surface 201 of the prefabricated print is ground as a whole with the surface for accompanying wafer 400, and the two it
Between there's almost no difference in height, it is thus possible to improve the flatness of lapped face, avoids in process of lapping in section 1031 to be measured
Edge leads to the problem of fillet, keeps the integrality in section 1031 to be measured.
During being ground using polishing cloth, 400 surface of wafer and the pre- sample preparation can also be accompanied described
Polishing fluid is sprayed on the surface of product 200, to improve grinding effect.While grinding by polishing cloth, also by polishing cloth pair
It is cleaned on the surface of test sample 600.
The forming method of above-mentioned test sample can accurately prepare the test sample with small size target area, avoid pair
Grinding was caused in section to be measured, improved the success rate of test sample production, and reduce and prepare test sample by lapping mode
When limitation to target area size.
A specific embodiment of the invention also provides a kind of test sample formed using the above method.
Fig. 6 A and 6B are please referred to, Fig. 6 B is partial enlargement diagram.
The test sample 600 includes a prefabricated sample 200 ' comprising target area 103, the prefabricated 200 ' sample of sample
The top surface 201 of product is used as test surfaces, perpendicular to the thickness direction of the prefabricated sample 200 ', and exposes the target area
103 section to be measured 1031.
The prefabricated sample 200 ' can be a part of sample to be tested, and the sample to be tested includes body layer, the body layer
Inside it is formed with doped region and/semiconductor devices etc..The sample to be tested can also be including dielectric layer etc..The sample to be tested can be with
Bare chip to be formed with semiconductor devices or the structure in semiconductor devices forming process, can determine from wafer
Cuboid.The distance between the target area 103 of the prefabricated sample 200 ' and the side wall on thickness direction are more than or equal to 1 μm,
It avoids passing through when obtaining prefabricated sample 200 ' by the modes such as grinding or cutting to the sample to be tested, causes target area 103
Missing.
The test sample 600 further includes that the two sides side wall that is pasted on the 200 ' thickness direction of prefabricated sample accompanies piece
Wafer 400 ', it is described that 400 ' surface of wafer and the test surfaces of the prefabricated sample 200 ' is accompanied to flush, and consistency of thickness, it is small
In the thickness of monolithic bare silicon wafer.
It is described to accompany the test surfaces of wafer 400 ' and the prefabricated sample 200 ' by integral grinding, so that described accompany piece
The junction of the test surfaces of wafer 400 ' and the prefabricated sample 200 ' has continuous grinding marks.
In three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μm for the target area 103.?
In the specific embodiment, the target area 103 is a cuboid, at least one size in length, width and height
Less than or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.
The section to be measured 1031 of the target area 103 perpendicular to the prefabricated sample 200 ' thickness direction, it is described pre-
Surface on 200 ' thickness direction of sample preparation product is the side wall of prefabricated sample 200 '.Preferably, the prefabricated sample 200 ' is rectangular
The bodily form；Or the prefabricated sample 200 ' at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described
Between two opposite vertical sidewalls.
In this specific embodiment, described to accompany wafer 400 ' for cuboid, wafer 400 ' and institute are accompanied with described
It is identical with size to state the sidewall shape that prefabricated sample 200 ' is pasted.It is described that wafer 400 ' is accompanied laterally to be pasted on the prefabricated sample
On the vertical side wall of 200 ' any two, the target area 103 is between described two vertical side walls.
200 ' the side wall of prefabricated sample and described accompany are fixed between wafer 400 ' by glue-line.The glue-line can be
The glue-lines such as AB glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee the 200 ' side wall of prefabricated sample with
Described accompany fits closely between wafer 400 ', and the thickness of the glue-line is less than or equal to 1 μm.
In some embodiments, the prefabricated sample 200 ' and wafer 400 ' is accompanied integrally to can be used as test specimens
Product.
In the specific embodiment, the test sample 600 further includes semiconductor bottom plate 300 ', and semiconductor bottom plate 300 can
Think by the wafer that cuts and/or polish, the semiconductor bottom plate 300 ' as accompanied described in fixed and carrying wafer 400 ' and
The fixation wafer of prefabricated sample 200 '.
300 ' the surface of semiconductor bottom plate is fixed in the bottom surface of the 200 ' sample of prefabricated sample.In some specific implementations
In mode, fixed between the prefabricated sample 200 ' and the semiconductor bottom plate 300 ' by conducting resinl.In some specific implementations
In mode, the conducting resinl can be the viscoloid doped with metal, such as elargol, so that the prefabricated sample 200 ' and institute
Stating has good electric conductivity between semiconductor bottom plate 300 ', so as to by the semiconductor bottom plate 300 ' to described prefabricated
Print 200 ' applies voltage.
It is described that 400 ' bottom of wafer is accompanied also to be secured to the 300 ' surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 ' and the prefabricated print 200 ' avoids described accompanying wafer 400 ' and the prefabricated print 200 '
It is detached from.
The edge for accompanying wafer 400 ', prefabricated sample 200 ' and semiconductor bottom plate 300 ' flushes.Some specific
In embodiment, it is described accompany wafer 400 ', prefabricated print 200 ' and semiconductor bottom plate 300 ' a generally cuboid or
Other regular figures, convenient for being held or being moved during follow-up test.
The specific embodiment of the present invention also provides a kind of electric test method.
Test sample 600 described in above-mentioned specific embodiment is formed using above-mentioned test sample preparation method first
(please referring to Fig. 6 A and 6B)；Using scanning capacitance capacitance microscopy, electricity is carried out to the section to be measured 1031 of the test sample 600
Property test, obtain the electrical parameter information of the target area 103.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The accuracy of electrical testing can be improved, especially have to the accuracy for the electrical testing for needing direct contact measured section larger
Raising.
In a specific embodiment, the electrical testing is capacity measurement.It is described in other specific embodiments
Electrical testing can also be contact resistance test, doping concentration test etc..
During carrying out capacity measurement, by the test probe of the Scanning capacitance microscope and the section 1031 to be measured
It contacts and is moved in a manner of rank scanning, while adding a low frequency between the test probe and the test sample 600
AC field.
Voltage can be applied to the prefabricated sample 200 ' by the semiconductor bottom plate 300 ', so that the testing section
1031 are electrically connected to test voltage end.
It, can also be directly to the prefabricated sample when test sample only includes accompanying wafer 400 ' and prefabricated sample 200 '
200 ' apply voltage.
During the test probe scanning, is measured by hyperfrequency capacitance sensor and obtain capacitance and acquisition
The capacitance profile figure of target area 103.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The accuracy of electrical testing can be improved.
A specific embodiment of the invention also provides a kind of electrical testing system.
The electrical testing system includes tester table and test sample；Wherein test sample please refers to Fig. 6 A and 6B,
Fig. 6 B is partial enlargement diagram.
The test sample 600 includes a prefabricated sample 200 ' comprising target area 103, the prefabricated 200 ' sample of sample
The top surface 201 of product is used as test surfaces, perpendicular to the thickness direction of the prefabricated sample 200 ', and exposes the target area
103 section to be measured 1031.
The prefabricated sample 200 ' can be a part of sample to be tested, be formed in the sample to be tested doped region and/
Semiconductor devices etc., the sample to be tested can also be including dielectric layers etc..The sample to be tested can be to be formed with semiconductor device
The bare chip of part or the structure in semiconductor devices forming process can be the cuboid determined from wafer.It is described prefabricated
The distance between side wall on the target area 103 of sample 200 ' and thickness direction is more than or equal to 1 μm, avoid passing through to it is described to
When sample obtains prefabricated sample 200 ' by the modes such as grinding or cutting, target area 103 is caused to lack.
The test sample 600 further includes that the two sides side wall that is pasted on the 200 ' thickness direction of prefabricated sample accompanies piece
Wafer 400 ', it is described that 400 ' surface of wafer and the test surfaces of the prefabricated sample 200 ' is accompanied to flush, and consistency of thickness, it is small
In the thickness of monolithic bare silicon wafer.
It is described to accompany the test surfaces of wafer 400 ' and the prefabricated sample 200 ' by integral grinding, so that described accompany piece
The junction of the test surfaces of wafer 400 ' and the prefabricated sample 200 ' has continuous grinding marks.
In three-dimensional system of coordinate, the size at least one coordinate direction is less than or equal to 1 μm for the target area 103.?
In the specific embodiment, the target area 103 is a cuboid, at least one size in length, width and height
Less than or equal to 1 μm.In other specific embodiments, the target area 103 can also be other shapes.
The section to be measured 1031 of the target area 103 perpendicular to the prefabricated sample 200 ' thickness direction, it is described pre-
Surface on 200 ' thickness direction of sample preparation product is the side wall of prefabricated sample 200 '.Preferably, the prefabricated sample 200 ' is rectangular
The bodily form；Or the prefabricated sample 200 ' at least has there are two opposite vertical sidewall, and the target area 103 be located at it is described
Between two opposite vertical sidewalls.
In this specific embodiment, described to accompany wafer 400 ' for cuboid, wafer 400 ' and institute are accompanied with described
It is identical with size to state the sidewall shape that prefabricated sample 200 ' is pasted.It is described that wafer 400 ' is accompanied laterally to be pasted on the prefabricated sample
On the vertical side wall of 200 ' any two, the target area 103 is between described two vertical side walls.
200 ' the side wall of prefabricated sample and described accompany are fixed between wafer 400 ' by glue-line.The glue-line can be
The glue-lines such as AB glue, epoxy resin can may be insulating cement for conducting resinl.In order to guarantee the 200 ' side wall of prefabricated sample with
Described accompany fits closely between wafer 400 ', and the thickness of the glue-line is less than or equal to 1 μm.
In some embodiments, the prefabricated sample 200 ' and wafer 400 ' is accompanied integrally to can be used as test specimens
Product.
In the specific embodiment, the test sample 600 further includes semiconductor bottom plate 300 ', and semiconductor bottom plate 300 can
Think by the wafer that cuts and/or polish, the semiconductor bottom plate 300 ' as accompanied described in fixed and carrying wafer 400 ' and
The fixation wafer of prefabricated sample 200 '.
300 ' the surface of semiconductor bottom plate is fixed in the bottom surface of the 200 ' sample of prefabricated sample.In some specific implementations
In mode, fixed between the prefabricated sample 200 ' and the semiconductor bottom plate 300 ' by conducting resinl.In some specific implementations
In mode, the conducting resinl can be the viscoloid doped with metal, such as elargol, so that the prefabricated sample 200 ' and institute
Stating has good electric conductivity between semiconductor bottom plate 300 ', so as to by the semiconductor bottom plate 300 ' to described prefabricated
Print 200 ' applies voltage.
It is described that 400 ' bottom of wafer is accompanied also to be secured to the 300 ' surface of semiconductor bottom plate, to accompany wafer described in stabilization
Stickup reliability between 400 ' and the prefabricated print 200 ' avoids described accompanying wafer 400 ' and the prefabricated print 200 '
It is detached from.
The edge for accompanying wafer 400 ', prefabricated sample 200 ' and semiconductor bottom plate 300 ' flushes.Some specific
In embodiment, it is described accompany wafer 400 ', prefabricated print 200 ' and semiconductor bottom plate 300 ' a generally cuboid or
Other regular figures, convenient for being held or being moved during follow-up test.
In a specific embodiment, the electrical testing system is capacitor test system, the electrical property test machine
Including Scanning capacitance microscope.The Scanning capacitance microscope includes a test probe.It is described during carrying out capacity measurement
The test probe of Scanning capacitance microscope with the section to be measured 1031 of test sample 600 for directly contacting and with rank scanning side
Formula is moved, while Scanning capacitance microscope is also used between the test probe and the test sample 600 plus one is low
Frequency AC field.
Voltage can be applied to the prefabricated sample 200 ' by the semiconductor bottom plate 300 ', so that the testing section
1031 are electrically connected to test voltage end.
It, can also be directly to the prefabricated sample when test sample only includes accompanying wafer 400 ' and prefabricated sample 200 '
200 ' apply voltage.
The electrical testing system further includes a hyperfrequency capacitance sensor, obtains capacitance and acquisition mesh for measuring
Mark the capacitance profile figure in region 103.
It include complete target area 103 since the test sample 600 has complete section 1031 to be measured, thus
The accuracy of the electrical testing of the electrical testing system can be improved.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (20)
1. a kind of semiconductor test method characterized by comprising
A sample to be tested is provided, the sample to be tested includes target area to be tested；
The sample to be tested is ground, prefabricated sample is formed, the target area is located in the prefabricated sample, and described
The thickness of prefabricated sample and single-wafer consistency of thickness, the thickness of the section to be measured of the target area perpendicular to the prefabricated sample
Direction is spent, the surface on the prefabricated thickness of sample direction is the side wall of prefabricated sample；
Wafer, the thickness for accompanying wafer and the prefabricated thickness of sample are accompanied in the two sides side wall stickup of the prefabricated sample
Unanimously, the surface for accompanying wafer is flushed with the surface of the prefabricated sample；
It accompanies the surface of platelet circular surfaces and the prefabricated sample by described plane is ground as a whole, until exposing
The section to be measured of the target area；
Wafer and prefabricated sample will be accompanied integrally to be used as test sample after the grinding, the section to be measured tested,
Obtain the electrical property and/or physical characteristic information of the target area.
2. semiconductor test method according to claim 1, which is characterized in that the semiconductor test is capacity measurement.
3. semiconductor test method according to claim 2, which is characterized in that during the capacity measurement, by institute
The test probe for stating Scanning capacitance microscope is contacted with the section to be measured and is moved in a manner of rank scanning, while in institute
It states and adds a low-frequency ac electric field between test probe and the test sample.
4. semiconductor test method according to claim 1, which is characterized in that accompany wafer table to described using polishing cloth
Face and the surface of the prefabricated sample are ground.
5. semiconductor test method according to claim 1, which is characterized in that further include: in the side of the prefabricated sample
Before wafer is accompanied in wall stickup, semiconductor backplate surface is fixed in the bottom surface of the prefabricated sample.
6. semiconductor test method according to claim 5, which is characterized in that the prefabricated sample and the semiconductor bottom
It is fixed between plate by conducting resinl, it is described that wafer bottom is accompanied also to be secured to the semiconductor backplate surface.
7. semiconductor test method according to claim 1, which is characterized in that the prefabricated sample side wall accompanies piece with described
It is fixed between wafer by glue-line, the thickness of the glue-line is less than or equal to 1 μm.
8. semiconductor test method according to claim 6, which is characterized in that further include: platelet circular surfaces are accompanied by described
Before being ground as a whole with the surface of the prefabricated sample, wafer is accompanied to be polishing to semiconductor bottom edge by described
It flushes.
9. semiconductor test method according to claim 6, which is characterized in that described to accompany wafer and semiconductor bottom plate is
Identical material.
10. semiconductor test method according to claim 1, which is characterized in that the target area is in three-dimensional system of coordinate
In, the length at least on a coordinate direction is less than or equal to 1 μm.
11. semiconductor test method according to claim 1, which is characterized in that the prefabricated sample surfaces and it is described to
It surveys the distance between section and is more than or equal to 1 μm；The distance between side wall of the target area and the prefabricated sample is greater than etc.
In 1 μm.
12. a kind of semiconductor test system characterized by comprising
Test sample and tester table；
The test sample includes: a prefabricated sample comprising target area, and the test surfaces of the prefabricated sample are perpendicular to institute
It states the thickness direction of prefabricated sample and exposes the section to be measured of the target area；
The two sides side wall being pasted on the prefabricated thickness of sample direction accompanies wafer, it is described accompany platelet circular surfaces with it is described pre-
The test surfaces of sample preparation product flush, and consistency of thickness, respectively less than the thickness of monolithic bare silicon wafer；
The tester table obtains the electrical property of the target area for testing the section to be measured of the test sample
And/or physical characteristic information.
13. semiconductor test system according to claim 12, which is characterized in that the tester table includes scanning capacitance
Microscope, the probe of the Scanning capacitance microscope are moved in a manner of rank scanning for contacting with the section to be measured
It is dynamic, while adding a low-frequency ac electric field between the test probe and the test sample.
14. semiconductor test system according to claim 12, which is characterized in that the tester table further include: superelevation
Frequency capacitance sensor, for measuring the capacitance for obtaining target area.
15. semiconductor test system according to claim 12, which is characterized in that described to accompany wafer and the pre- sample preparation
The junction of the test surfaces of product has continuous grinding marks.
16. semiconductor test system according to claim 12, which is characterized in that the target area is in three-dimensional system of coordinate
In, the size at least one coordinate direction is less than or equal to 1 μm.
17. semiconductor test system according to claim 12, which is characterized in that the test sample further includes semiconductor
The semiconductor backplate surface is fixed in bottom plate, the bottom surface of the prefabricated sample；It is described that wafer bottom is accompanied to be fixed on described half
Conductor substrate surface.
18. semiconductor test system according to claim 17, which is characterized in that the prefabricated sample bottom surface and described half
Conductor substrate is fixed between surface by conducting resinl.
19. semiconductor test system according to claim 12, which is characterized in that described to accompany wafer viscous by a glue-line
The prefabricated sample side wall is invested, the thickness of the glue-line is less than or equal to 1 μm.
20. semiconductor test system according to claim 12, which is characterized in that the target area and the pre- sample preparation
The distance between side wall on the thickness direction of product is more than or equal to 1 μm.
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| CN201910100813.0A CN109870336A (en) | 2019-01-31 | 2019-01-31 | Semiconductor test system and its test method |
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Application publication date: 20190611 |