JP2007208046A - Test method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test method for a semiconductor device which can shorten the test time efficiently. <P>SOLUTION: The test method includes a process (step S 13) to select a tested chip in a reference region on a wafer positioned to surround a test chip; a process (step S 14) to compile test items and their number of the selected tested chips identified to be failure, and to rearrange the sequence of the test items so that the test item with many failures may come first; and a process (step S 15) to carry out the test of the test chips in the order of rearranged test item sequence. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for testing a semiconductor device.

  A test for determining whether or not a semiconductor device (referred to as a chip from a morphological side) is performed on a wafer tends to increase the number of test items due to the multi-functionalization of the semiconductor device. In particular, in an analog semiconductor device, it is necessary to perform a test in which the input level is changed even in a similar test, and therefore the number of test items may reach several hundred or more.

  The wafer test is started from a predetermined position on the wafer for each chip, and the test is often performed in the order of arrangement on the wafer. In each chip, the test is performed in the order set from the first test item to the several hundredth test item, for example. When a defect is found in the test item, it is determined as a defective product. In the pass / fail judgment, since no further measurement is required, the prober and tester move to the next chip to be tested. In the next chip, the test is repeated in the order set from the first test item. For this reason, an increase in the number of test items in an analog semiconductor device or the like leads to an increase in wafer test time and deteriorates the wafer test throughput.

  Therefore, in the pass / fail judgment test, the first chip No. 1 to 10 are all tested in the order of the test items described in the test program. 11 to 20 are chip numbers. Based on the test results 1 to 10, the test items are rearranged in the order of the test items having the largest number of defects, and then the test items are rearranged every 10 chips in the same manner, and the test items are always sorted for the immediately preceding 10 chips. A method is disclosed in which the next test is performed in order from the one with the largest number of defects in the test results (see, for example, Patent Document 1).

In the disclosed test method, since the order of the frequency of defective test items occurring on 10 chips that are close to the measurement time is reflected in the measurement of the test chip, it happens that the distribution of failure causes that is the same as the distribution of the previous 10 chips. When the test pieces overlap, it is possible to shorten the time to reach the defective test item, that is, the test time when testing the test chip. However, since the chips are formed in the planar spread of the wafer, the distribution of the 10 chips immediately before being referenced is often different from the distribution of the cause of failure, and the test time is not so large as expected. There is a problem.
JP-A-9-181134

  The present invention provides a method for testing a semiconductor device that can efficiently reduce the test time.

  A method for testing a semiconductor device according to an aspect of the present invention includes a step of selecting a tested chip in a reference region on a wafer at a position surrounding a test chip, and a test in which the selected tested chip is defective. A step of counting the items and the number thereof, rearranging the order of the test items so that the test item having a large number of defects comes first, and a step of performing the test of the test chip in the order of the rearranged test items; It is characterized by having.

  According to another aspect of the present invention, there is provided a test method for a semiconductor device, the step of preparing a wafer having a pattern formed by dividing into a plurality of shots, and the test chip and the wafer at the same position in the shot. The step of selecting the above tested chip, the test items that have become defective in the selected tested chip, and the number of the test items are totaled, and the order of the test items is set so that the test item with the highest number of defects is at the top. The rearrangement step and the test of the test chip are performed in the order of the rearranged test items.

  ADVANTAGE OF THE INVENTION According to this invention, the test method of the semiconductor device which can shorten test time efficiently can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component.

  First, when performing the wafer test process, as shown in FIG. 1, coordinates indicating the position of the chip 5 are given in order to distinguish each of the chips 5 arranged two-dimensionally on the wafer 1. For example, “1” is given in the row direction of the vertical axis, starting from a substantial wafer edge, and hereinafter, the number is incremented by 1 for each vertical pitch parallel to the sides of the rectangular chip. Similarly, in the row direction of the horizontal axis parallel to the sides of the rectangular chip, “1” is given starting from the substantial wafer edge, and the number is incremented by 1 for each horizontal pitch of the chip. The chip 5 indicated by the leading end of the lead-out line (wavy line) has a row number “4” and a column number “7”, and can be displayed with coordinates (4, 7), for example.

  Since the wafer is generally circular, four corners of a rectangle displayed in rows and columns, for example, (1,1), (1,16), (16,1), (16,16) ) Etc., there is no chip, and the chip present in the peripheral part of the wafer has a large difference in manufacturing conditions compared to the chip in the central part, or a complete chip shape cannot be secured. Therefore, it is excluded in the wafer test process. That is, the circle shown in FIG. 1 is inside the outer periphery of the actual wafer 1, and 164 chips 5 worth testing are distributed in this circle, for example.

  Next, the wafer test process is performed by a test apparatus 100 schematically shown in FIG. As shown in FIG. 2, in the semiconductor device testing apparatus 100, a tester 101 and a prober 102 are connected to a tester server 104, and the tester 101 and the tester server 104 are connected to a setting unit 106. A wafer is placed at a predetermined position of the prober 102, the position of the test chip is brought out by the moving mechanism, and the probe is brought into contact with the electrode of the test chip. In this contact state, a power test and a test signal are supplied from the tester to perform a wafer test. Usually, there are many test items, and in determining whether a chip is good or bad, when a defect is found in the test item, the test chip is determined to be a defective chip, and the next test, for example, is performed on the adjacent test chip.

  The wafer test result is sent to the tester server 104, and the pass / fail test item number and the like are stored together with the coordinates of the test chip. The setting unit 106 includes a computer including an input / output device and a storage device. The setting unit 106 sets a reference area distributed around the test chip, sets a reference to a equivalent chip at a position equivalent to the test chip, Applications that have settings, analysis / display of test results, wafer / lot quality check, and other functions are installed.

  3A and 3B are diagrams schematically showing the pass / fail test items for each chip in correspondence with the chip distribution on the wafer through the wafer test process for pass / fail determination. Note that when all the test chips are measured, even if a plurality of test items are defective, in the pass / fail judgment test, the test item in which the defect first appears is shown as a defect test item for the test chip.

  As shown in FIG. 3A, the wafer 2 has many good chips 11, while the defective chips 12 distributed almost randomly on the wafer 2 and the wafer 1 indicated by relatively small coordinates. The defective chips 13 are intensively distributed in the upper left. For example, dust in the wafer manufacturing process often shows a random distribution of defects, and it is known that defects caused by chemical processes or equipment conditions may show a distribution of defects spread over a certain area. Yes.

  As shown in FIG. 3B, the wafer 3 has regularity in which many good chips 21 are present and defective chips 22 are distributed with a constant interval in the row direction and the column direction. This regularity corresponds to the shot of the stepper used in the pattern transfer process, as will be described later.

  A test method for a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a flowchart schematically showing a test method for a semiconductor device. FIG. 5 is a diagram schematically showing a reference region for a test chip in a semiconductor device testing method.

  As shown in FIG. 4, a reference area for determining the order of test items on the test chip is set (step S11). There is a cause for the failure of the chip in the test, and the range of the cause may be only one test chip, but may be the same for a plurality of chips. Although the range of the range is various, since the chips are two-dimensionally arranged on the wafer, it is common to think that defects caused by the cause also have a two-dimensional expansion. is there. Therefore, the reference area is a chip that is in contact with or in contact with the side or corner of the test chip with the test chip at the center (referred to as “singly surrounding”), and the chip before the test. A region excluding, ie, a region composed of tested chips. The coordinates of the chips to be tested at the beginning and end of the wafer can be stored in the test apparatus 100 in advance.

  Next, as shown in FIG. 5, the first chip to be tested is located at (2, 6), for example. However, since it is clear that there is no data to be referred to by this test chip, the initially set test is performed. Tests are performed in the order of items (step S12). When a defect is found, subsequent test items are skipped.

  The process proceeds to the next test chip, and a tested chip in the reference area of this test chip is selected (step S13).

  The selection of the tested chip within the reference area will be described. As shown in FIG. 5, at a certain point in time when the wafer test is in progress, the reference area 31 is a chip that surrounds the test chip 6 at the center and surrounds the periphery of the test chip 6, and excludes the pre-test chip. Therefore, if the test chip 6 is (4, 7), the reference area 31 has chips (3, 6), (3, 7), (3, 8), (4, 6). Is included. The wafer test sequence proceeds from the (2,6) chip at the end of the wafer to the peripheral portion of the wafer 2 along the same row, and the peripheral portion is oriented in the direction of the arrow shown in the figure. Instead, the process proceeds along the next line, and similarly, the test is performed in the direction of increasing the line number. When the test chip is inside the wafer 2, four chips can be selected as the reference region 31. However, the test chip is located at the periphery of the wafer 2, for example, (3, 13). In some cases, there may be no tested chip in the reference area 31. In addition, p, f3, and f9 written in each chip position in FIG. 5 respectively indicate a pass, that is, a defect, a test item number “3” defect, and a test item number “9” defect.

  Next, the test items and the number of chips determined to be defective among the tested chips in the reference area are totaled, arranged in order of the test items with the largest number, and a new test with this test item order at the top. Item order is created (step S14). For example, in the case shown in FIG. 5, the new test item order is such that the test item number “9” having three defects is first, followed by the test item number “3” having one defect. The test items are initially set in the order excluding 2 items. For example, when there is no tested chip in the reference area 31 as in (3, 13), the order of the test items adopted in the previous test chip and the chip in (2, 11) Is adopted.

  Next, the test chip is tested according to the new test item order, and when a defect occurs, the subsequent test items are skipped and the process proceeds to the next chip test (step S15).

  Next, whether or not the test of the last test chip has been completed is confirmed by the coordinates of the previously input chip (step S16). If all the chips in the wafer have not been tested, the process returns to step S13, and the process proceeds to the next test chip, for example, the test of (4, 8) in the case shown in FIG.

  If all the chips in the wafer have been tested, it is next checked with the wafer number inputted in advance whether the last wafer in the lot structure has been tested (step S17).

  If all the wafers in the lot have not been tested, the next test wafer is set (step S18). Then, the process returns to step S12 and the test of the test chip is started.

  On the other hand, if all the wafers in the lot have been tested, the process proceeds to the end of the wafer test (step S17).

  As described above, in this embodiment, a chip that surrounds the test chip 6 in a single layer, that is, a chip that is adjacent in plan and is in the reference region 31 excluding the chip before the test is selected. Then, the test items that have become defective in the selected tested chip and the number of the test items are totaled, the order of the test items is rearranged in the order of the test items having the highest number of defects, and placed at the top of the test items, and the test chip 6 The tests are performed in the order of the sorted test items.

  As a result, when the test chip 6 becomes defective due to the same cause as the tested chip, it is determined as defective at an early point in the order of the test items. In addition, since the reference area 31 in which the tested chips surrounding the test chip 6 are distributed has a relation that bisects the area in which the pre-test chips are distributed in a plane, the range covers a plurality of continuously distributed chips. About half of the defects due to the cause can be reflected in the order of the test items of the test chip 6 and can be determined to be defective at the beginning of the test. That is, according to the present embodiment, it is possible to shorten the test time more efficiently as compared with the wafer test based on the test item order based on the defective item of the chip measured close in time. .

  Next, a modification of the first embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram schematically showing a reference region for a test chip in a semiconductor device testing method. As shown in FIG. 6, the reference region 32 is placed in contact with or in contact with the chip that surrounds the test chip 6 and the side or corner of the chip that surrounds the test chip 6 with the test chip 6 at the center. In addition, the method is different from the measurement method of the semiconductor device according to the first embodiment in that the chip is an area excluding the chip before the test (referred to as “double surround”). Components different from the first embodiment will be described.

  The semiconductor device test method is the same as the semiconductor device test method of the first embodiment.

  The selection of the test chip in the reference area 32 will be described. As shown in FIG. 6, at a certain point in time when the wafer test is in progress, the reference region 32 is a chip that double surrounds the periphery of the test chip 6 and is composed of tested chips. If the test chip 6 is (4, 7), the reference area 32 has (2, 6), (2, 7), (2, 8), (2, 9), (3, 5), (3 , 6), (3, 7), (3, 8), (3, 9), (4, 5), and (4, 6) chips are included. When the test chip is inside the wafer 1, a maximum of 12 chips can be selected as the reference area 32.

  The test method for the semiconductor device of this modification is different from the test method of the first embodiment only in that the reference region 32 is widened, and thus has the same effect as the test method of the semiconductor device of the first embodiment. In addition, since the reference area 32 is widened, it is possible to catch defects caused by discontinuous distribution in the plane of the wafer 2 and reflect them in the order of the test items of the test chip 6. Thus, it is possible to determine that the test chip 6 is defective.

  Note that the reference region 32 of this modification is a region including a chip that surrounds the test chip 6 around the doubly, and includes a chip that surrounds the periphery of the test chip 6 in a wider area, for example, a chip that surrounds the test chip 6 An area or the like can be used as a reference area. In addition, an area composed of tested chips included in a range limited by the distance from the test chip 6 can be used as a reference area.

  A method for testing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a diagram schematically showing the quality of each chip corresponding to the chip distribution on the wafer, and repeating units corresponding to the shot areas. FIG. 8 is a flowchart schematically showing a semiconductor device testing method. FIG. 9 is a diagram schematically showing a reference chip for the test chip in the semiconductor device testing method. The present embodiment is different from the first embodiment and the modification thereof in that the test item order is created by referring to the defect test item of the equivalent chip at a position shifted by an integral multiple of the repeating unit with respect to the test chip. Below, the same code | symbol is attached | subjected to the same component as the said Example 1 or a modification, the description is abbreviate | omitted, and a different component is demonstrated.

  As shown in FIG. 7, in the tested wafer 3, the frame of the unit corresponding to the shot of the stepper used in the pattern transfer process is repeated on the pass / fail judgment chip distribution on the wafer shown in FIG. The unit 33 is displayed in an overlapping manner. The repeating units 33 are arranged so as to cover all the wafers 3 with the starting point being (1, 1). Many of the defective chips appear at specific positions of the repeating unit 33. In the pass / fail wafer test, if the size of the repeat unit 33 corresponds to the size of the shot, the arrangement of the repeat unit 33 and the shot may not exactly overlap.

  The test method of the semiconductor device according to the present embodiment is applicable to shots in the wafer manufacturing process when one wafer test in a lot having a plurality of wafers is completed and it is determined that there is a repeated defect corresponding to the shot. This method is applied to the case where it is grasped or predicted in advance that there is a cause of failure, or the case where a failure corresponding to a shot tends to occur based on past wafer test data.

  As shown in FIG. 8, in order to determine the order of the test items of the test chip, a repeat unit corresponding to a shot is set (step S21). The repetition unit is defined by the number of chips in the row and column directions, for example, 4 rows × 3 columns. Based on the repeating unit, the equivalent chip in the repeating unit (repeating unit that is in plane contact with the side or corner of the repeating unit having the test chip) that surrounds the periphery of the repeating unit having the test chip in a single layer. Then, a tested equivalent chip excluding the equivalent chip before the test is referred to. Note that the coordinates of the chips to be tested at the beginning and end of the wafer can be set in advance in the test apparatus 100.

  Next, as shown in FIG. 9, the chip to be tested first is located at (2, 6), for example. However, since it is clear that there is no data to be referred to by this test chip, the initially set test is performed. Tests are performed in the order of items (step S22). When a defect is found, subsequent test items are skipped.

  The process proceeds to the next test chip, and the equivalent chip of this test chip is selected (step S23).

  Describe the selection of tested equivalent chips. As shown in FIG. 9, at a certain point in time when the wafer test is in progress, for example, (4, 6), (4, 9) at the equivalent position with respect to the test chip 8 at coordinates (8, 9). , (4, 12), (8, 6) equivalent chips 9 are selected. These equivalent chips 9 are chips at equivalent positions in the repeating unit 33 that surrounds the repeating unit 33 having the test chip 8 in a single layer. The order of the wafer test is the same as that in the first embodiment. In addition, p and f2 written in each chip position indicate a pass, that is, good, or a failure of the test item number “2”, respectively.

  If the coordinates of the test chip shown in FIG. 9 are (a, b) and the repetition unit is (m, n), for example, if the row is being tested from left to right, (a−m, b -N), (am, b), (am, b + n), and (a, b-n), and if the row is being tested from right to left, the fourth is (a, The chip represented by b + n) is the tested equivalent chip.

  In addition, when the test chip is at or near the center of the wafer 3, four chips can be selected as equivalent chips. However, when the test chip is at the peripheral part of the wafer 3, the equivalent chip is selected. May not be available.

  Next, the test items and the number of chips determined to be defective among the tested equivalent chips are aggregated, arranged in the order of the test items with the largest number, and a new test item order with this test item order at the top is added. Create (step S24). The new test item order is, for example, in the case shown in FIG. 9, the test item number “2” having four defects comes to the top, and the test items that are initially set excluding this test item number “2” will be described below. In order. When the equivalent chip cannot be selected, the order of the test items adopted in the previous test chip is adopted.

  Next, the test chips are tested in the order of new test items, and when a defect occurs, the subsequent test items are skipped and the process proceeds to the next chip test (step S25).

  Next, whether or not the test of the last test chip has been completed is confirmed with the coordinates of the previously input chip (step S26). If all the chips in the wafer have not been tested, the process returns to step S23, and the process proceeds to the next test chip, for example, the test of (8, 10) in the case shown in FIG.

  If all the chips in the wafer have been tested, it is next checked with the wafer number input in advance whether the last wafer in the lot structure has been tested (step S27).

  If all the wafers in the lot have not been tested, the next test wafer is set (step S28). Then, the process returns to step S22, and the test of the test chip is started.

  On the other hand, if all the wafers in the lot have been tested, the process proceeds to the end of the wafer test (step S27).

  As described above, in this embodiment, the tested equivalent chip on the wafer 3 at the same position as the test chip 8 is selected, and the test items and the number of the defective equivalent chips are selected. The test items are tabulated, and the order of the test items is rearranged in the order of the test items having the highest number of defects and placed at the top of the test items, and the test of the test chip 8 is performed in the order of the rearranged test items.

  As a result, when the test chip 8 becomes defective due to the same cause as the equivalent chip, it is determined as defective at an early point in the order of the test items. That is, according to the present embodiment, since the order of the test items based on the planar regularity of the defective chip is set, the test performed simply based on the defective items of the chip measured close in time Compared with the item order, the test time can be shortened more efficiently.

  In the present embodiment, the equivalent chip in the repeating unit that surrounds the repeating unit having the test chip in a single layer with reference to the repeating unit, and the tested equivalent chip was referred to. Is a double-enclosing repeat unit (single-enclosed repeat unit and repeat unit that touches these sides or corners in a plane), or more, for example, an equivalent chip in the entire wafer and tested It is safe to refer to equivalent chips.

  As mentioned above, this invention is not limited to the said Example, In the range which does not deviate from the summary of this invention, it can change and implement variously.

  For example, in the first embodiment, the test item order based on the number of defective test items of the tested chip in the reference area surrounding the test chip is created, and in the second embodiment, the equivalent chip separated by the repeating unit with respect to the test chip. The order of the test items based on the number of defective test items is created, and both the reference area shown in the first embodiment and the equivalent chip shown in the second embodiment are selected as reference chips for the test chip, and The test item order is created based on the defect test items obtained in the first embodiment and the number thereof and the defect test items obtained in the second embodiment and the total number of the defect test items and the number thereof, and the wafer test is performed. It can be done.

  Further, in the second embodiment, for example, as an example of a test method to be performed after a test of one wafer in a lot consisting of a plurality of wafers is completed and it is separately determined that there is a repeated defect corresponding to a shot. Although shown, it is possible to add a step of determining whether or not there is a repeating unit corresponding to the shot before the step 21 of performing the test of the second embodiment, and to perform the test continuously. .

  In the second embodiment, the repeat unit of the wafer test is a repeat unit based on the shot of the stepper, but other repeat units in the wafer manufacturing process may be selected as the repeat unit of the wafer test.

The figure which shows typically the coordinate for showing the position of the chip | tip (semiconductor device) on the wafer which concerns on the Example of this invention. The block diagram which shows typically the structure of the test apparatus used for the test of the semiconductor device which concerns on the Example of this invention. The figure which shows typically the quality determination result of the chip | tip which concerns on the Example of this invention corresponding to the chip distribution on a wafer. 1 is a flowchart schematically showing a test method for a semiconductor device according to Embodiment 1 of the present invention. FIG. 3 is a diagram schematically illustrating a reference region for a test chip in the semiconductor device testing method according to the first embodiment of the invention. The figure which shows typically the reference area | region with respect to the test chip in the testing method of the semiconductor device which concerns on the modification of Example 1 of this invention. The figure which shows the quality of every chip | tip which concerns on Example 2 of this invention corresponding to the chip distribution on a wafer, and shows repeatedly the repeating unit area | region equivalent to a shot area | region. 9 is a flowchart schematically showing a semiconductor device testing method according to Embodiment 2 of the present invention. The figure which shows typically the reference chip (equivalent chip | tip) with respect to the test chip in the testing method of the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

1, 2, 3 Wafer 5 Chip 6, 8 Test chip 9 Equivalent chip 11, 21 Good chip 12, 13, 22 Bad chip 31, 32 Reference area 33 Repeat unit 100 Test device 101 Tester 102 Prober 104 Tester server 106 Setting unit

Claims (5)

Selecting a tested chip in a reference area on the wafer in a position surrounding the test chip;
Totalizing the test items and the number of defective test items of the selected tested chip, and rearranging the order of the test items so that the test items with a large number of defects are first,
A test of the test chip is performed in the order of the sorted test items;
A method for testing a semiconductor device, comprising:   The reference area is a chip including at least a chip that is in contact with a side or a corner of the test chip with the test chip as a center, and the reference area is an area made of a tested chip. 2. A test method for a semiconductor device according to 1. Preparing a wafer having a pattern formed by dividing into a plurality of shots;
Selecting a tested chip on the wafer at the same position in the shot as the test chip;
Totalizing the test items and the number of defective test items of the selected tested chip, and rearranging the order of the test items so that the test items with a large number of defects are first,
A test of the test chip is performed in the order of the sorted test items;
A method for testing a semiconductor device, comprising:   The tested chip at the equivalent position is a test at the equivalent position in the repeating unit that is in contact with a side or corner of the repeating unit having a size corresponding to the shot having the test chip therein. 4. The method of testing a semiconductor device according to claim 3, further comprising a finished chip.   5. The semiconductor according to claim 3, further comprising a step of determining that a repeating unit corresponding to the shot exists based on data of another wafer obtained before testing the wafer. 6. Equipment test method.

Images