JP2012204544A - Inspection method and inspection device for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection method and an inspection device for semiconductor device that can precisely detect characteristic defects of semiconductor devices formed on a semiconductor wafer.SOLUTION: There is provided the inspection method for semiconductor device including a first wafer inspection step, a second wafer inspection step, and a determination step. The first wafer inspection step is to inspect characteristics of a plurality of semiconductor devices formed on a semiconductor wafer using a probe card having probe needles brought into contact with the plurality of semiconductor devices at the same time. The second wafer inspection step is to re-inspect characteristics of the semiconductor devices while shifting the position of the probe card with respect to the semiconductor wafer from the position in the first wafer inspection step based upon a distribution of semiconductor devices, determined in the first inspection step to have characteristic defects, on the semiconductor wafer. The determination step is to determine characteristic defects, caused in manufacturing process carried out in units of a plurality of semiconductor devices, among the characteristic defects of the semiconductor devices based upon a result of the re-inspection in the second wafer inspection step.

Description

  FIELD Embodiments described herein relate generally to a semiconductor device inspection method and inspection apparatus.

  In recent years, a large number of semiconductor devices have been formed on a single semiconductor wafer due to miniaturization of semiconductor manufacturing processes and an increase in wafer diameter. As a result, the wafer inspection time for inspecting the characteristics of each semiconductor device formed on the semiconductor wafer tends to increase.

  In order to shorten the time for such wafer inspection, a probe card having a large number of probe needles (inspection needles) is used to simultaneously inspect the characteristics of a plurality of semiconductor devices by simultaneously contacting the probe needles with a plurality of semiconductor devices. Individual inspection has been carried out.

  In such wafer inspection, for example, contact failure of a specific probe needle occurs due to wear or dust adhesion, or a connection failure occurs in a specific connection terminal in a performance board connected to the probe card. There is a case.

JP 2010-038547 A

  The problem to be solved by the present invention is to provide an inspection method and an inspection apparatus for a semiconductor device capable of accurately detecting a characteristic defect of the semiconductor device formed on the semiconductor wafer.

  According to the embodiment, a semiconductor device inspection method including a first wafer inspection process, a two-wafer inspection process, and a determination process is provided. In the first wafer inspection step, the characteristics of the semiconductor device formed on the semiconductor wafer in a plurality of units are moved while moving the position of the probe card with which the probe needles are simultaneously brought into contact with the plurality of semiconductor devices with respect to the semiconductor wafer. inspect. In the second wafer inspection process, the position of the probe card with respect to the semiconductor wafer is determined based on the distribution of the semiconductor device on the semiconductor wafer determined to be defective in the characteristics by the first wafer inspection process. The characteristics of the semiconductor device are re-inspected by shifting from the position. The determination step determines a characteristic defect that occurs in a manufacturing process performed in units of a plurality of semiconductor devices among the characteristic defects of the semiconductor device based on a result of re-inspection in the second wafer inspection step.

Explanatory drawing of the test | inspection method concerning embodiment. The figure which shows an example of the misjudgment produced by the poor contact of a probe needle. Explanatory drawing which shows an example of the determination method with respect to the characteristic defect produced by a manufacturing process. The schematic diagram of the test | inspection apparatus concerning embodiment. The block diagram of the test | inspection management apparatus concerning embodiment. The figure which shows the relationship between the probe card concerning embodiment, and the position of a semiconductor device. The figure which shows the relationship between the probe card concerning embodiment, and the position of the semiconductor device on a semiconductor wafer. The figure which shows an example of distribution of the characteristic defect of the semiconductor device formed on a semiconductor wafer. The figure which shows the relationship between an exposure process and the position of a semiconductor device. 6 is a diagram illustrating an example of a distribution of characteristic defects in a semiconductor device. FIG. The figure which shows the example of a relationship between the characteristic defect of a semiconductor device, an exposure position, and a DUT position. 6 is a diagram illustrating an example of a distribution of characteristic defects in a semiconductor device. FIG. The figure which shows the example of a relationship between the characteristic defect of a semiconductor device, an exposure position, and a DUT position. 6 is a diagram illustrating an example of a distribution of characteristic defects in a semiconductor device. FIG. The figure which shows the example of a relationship between the characteristic defect of a semiconductor device, an exposure position, and a DUT position. 6 is a diagram illustrating an example of a distribution of characteristic defects in a semiconductor device. FIG. The figure which shows the example of a relationship between the characteristic defect of a semiconductor device, an exposure position, and a DUT position. 6 is a diagram illustrating an example of a distribution of characteristic defects in a semiconductor device. FIG. The figure which shows the example of a relationship between the characteristic defect of a semiconductor device, an exposure position, and a DUT position. The flowchart which shows the process sequence which the test | inspection apparatus concerning embodiment performs.

  Exemplary embodiments of an inspection method and an inspection apparatus for a semiconductor device according to embodiments will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below. In the following description, a semiconductor device inspection method is simply referred to as an “inspection method”, and a semiconductor device inspection device is simply referred to as an “inspection device”.

  First, the inspection method according to the embodiment will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is an explanatory diagram of an inspection method according to the embodiment, FIG. 2 is an explanatory diagram illustrating an example of erroneous determination of a characteristic failure caused by a probe needle contact failure, and FIG. 3 is a determination method for a characteristic failure caused by a manufacturing process. It is explanatory drawing which shows an example.

  The inspection method according to the embodiment performs wafer inspection for inspecting a semiconductor device formed on a semiconductor wafer using a probe card attached to a performance board.

  The probe card has many probe needles, and the probe needles can be brought into contact with a plurality of semiconductor devices under test (DUT) at the same time. Thereby, it is possible to inspect a plurality of semiconductor devices for inspecting characteristics of a plurality of semiconductor devices at the same time.

  Specifically, as shown in FIG. 1, the probe card can contact the probe needles simultaneously with a total of four semiconductor devices for two in the X direction and two in the Y direction. . Here, for convenience of explanation, the four DUT positions simultaneously contacting the probe needles of the probe card are defined as DUT positions p1 to p4.

  In the wafer inspection according to the embodiment, the characteristic inspection is performed in units of four semiconductor devices while changing the relative positions of the probe card and the semiconductor wafer, thereby inspecting the semiconductor devices one by one. Compared to the above, the wafer inspection time can be shortened.

  Note that the number of semiconductor devices that can be inspected at the same time is not limited to this, and it is sufficient that two or more semiconductor devices can be inspected simultaneously. For example, a total of 6 semiconductor devices in the X direction and 2 in the Y direction. It is good also as a probe card which can contact a probe needle with the semiconductor device simultaneously.

  In such wafer inspection, for example, a contact failure of a specific probe needle may occur, or a connection failure may occur at a specific connection terminal in a performance board connected to the probe card. When contact failure of a specific probe needle or connection failure of a specific connection terminal occurs, a semiconductor device at a specific position among semiconductor devices to be inspected at the same time may be erroneously determined as a characteristic failure.

  Such characteristic failure occurs depending on the position of the semiconductor device with respect to the probe card. For example, when the probe needle is not in good contact with the semiconductor device at the DUT position p1 in the probe card, as shown in FIG. 2A, many characteristic defects of the semiconductor device at the DUT position p1 are detected.

  In FIG. 2A, among the semiconductor devices formed on the semiconductor wafer, the probe card for the semiconductor devices of four columns (X1 to X4) in the X direction and four rows (Y1 to Y4) in the Y direction. And the position of the semiconductor device detected as a characteristic defect.

  Thus, when a characteristic defect corresponding to a specific position of the probe card is detected, the actual semiconductor device may not be a characteristic defect but may be erroneously determined.

  Accordingly, when the position of the probe card with respect to the semiconductor wafer is shifted in the X direction by one semiconductor device and reinspected, for example, the result shown in FIG. 2B is obtained. When the result shown in FIG. 2B is obtained, it can be detected that there is a problem in the inspection related to the DUT position p1 in the probe card, and the determination of the characteristic failure is an erroneous determination on the inspection side.

  However, characteristic defects of the semiconductor device formed on the semiconductor wafer may have a regular defect distribution in the semiconductor wafer due to fluctuations in the manufacturing apparatus before the inspection process.

  For example, the exposure processing performed by the exposure apparatus when forming a pattern on a semiconductor wafer uses a plurality of semiconductor devices as one exposure processing unit, and the exposure processing is performed for each of the plurality of semiconductor devices. When the exposure conditions such as the photomask shape and exposure intensity differ depending on the exposure position, the exposure results vary among the semiconductor devices exposed at the same time.

  As described above, when the exposure result varies among the semiconductor devices exposed at the same time, there may be a case where a semiconductor device having a characteristic defect is generated on the semiconductor wafer with a distribution corresponding to the exposure position. For this reason, there is a possibility that it may not be possible to accurately determine whether it is an erroneous determination on the inspection side or a characteristic defect caused by the exposure process. This is not limited to the exposure process, and may occur, for example, when a manufacturing process is performed for each of a plurality of semiconductor device units. Also, it may occur when the relationship between the DUT position and the position on the semiconductor wafer is biased, such as when the specific DUT position of the probe card tends to be biased at a specific position of the semiconductor wafer such as the outermost periphery of the semiconductor wafer. There is.

  Here, it is assumed that the exposure processing by the exposure apparatus is simultaneously performed on a total of four semiconductor devices, two in the X direction and two in the Y direction, as shown in FIG. For convenience of explanation, the positions of the four semiconductor devices exposed simultaneously are defined as exposure positions a to d.

  Then, it is assumed that the semiconductor device at the position as shown in FIG. That is, it is assumed that the characteristic failure of the semiconductor device is determined at the position X1: Y1, the position X1: Y3, the position X4: Y1, and the position X4: Y3. In this case, since there are a large number of semiconductor devices that are determined to have poor characteristics at the DUT position p1 and the DUT position p2 in the probe card, there is a possibility of erroneous determination on the inspection side.

  However, in the exposure process, the simultaneous exposure range is a range of [X1-X2: Y1-Y2], a range of [X1-X2: Y3-Y4], a range of [X3-X4: Y1-Y2], [X3- X4: Y3 to Y4], it is determined that a part of the semiconductor device at the exposure position a and the exposure position b (see FIG. 1) has a characteristic defect.

  In such a situation, as described above, it is assumed that the position of the probe card with respect to the semiconductor wafer is shifted by one semiconductor device in the X direction and the characteristics of the semiconductor device on the semiconductor wafer are re-inspected. When the result of such re-inspection is the result shown in FIG. 3B, there are a large number of semiconductor devices that are determined to have poor characteristics at the DUT position p1 and DUT position p2 even in the re-inspection.

  When the actual characteristic of the semiconductor device is just in the range where it is determined to be normal, the same semiconductor device may or may not be determined to be defective due to the inspection environment. Therefore, even if the result of the re-inspection is the result shown in FIG. 3B, the possibility of erroneous determination on the inspection side cannot be excluded.

  Therefore, in the inspection method according to the embodiment, the wafer inspection is performed again based on the distribution on the semiconductor wafer of the semiconductor device determined to have a characteristic defect. For example, when the result of the first wafer inspection is the result shown in FIG. 3A, a large number of semiconductor devices that are continuous in the X direction are determined as characteristic defects. Therefore, for example, the re-inspection is performed by shifting by one semiconductor device in the Y direction in addition to the X direction.

  For example, when the result of the re-inspection is the result shown in FIG. 3C, it can be determined that the determination of the characteristic failure is not an erroneous determination on the inspection side but is caused by the manufacturing process. On the other hand, when the result shown in FIG. 3D is obtained, it can be determined that the determination of the characteristic failure is not due to the manufacturing process but is due to an erroneous determination on the inspection side. In addition, when it is determined that the semiconductor device is continuously defective in the Y direction, the re-inspection is performed by shifting by one semiconductor device in the X direction.

  As described above, in the inspection method according to the embodiment, it is possible to accurately detect whether the regular determination of the characteristic defect is caused by the manufacturing process or the erroneous determination on the inspection side. Therefore, it is possible to accurately detect a characteristic defect of the semiconductor device formed on the semiconductor wafer.

  Hereinafter, the inspection method and the inspection apparatus according to the embodiment will be described more specifically. FIG. 4 is a schematic diagram of the inspection apparatus according to the embodiment, and FIG. 5 is a configuration diagram of the inspection management apparatus according to the embodiment.

  As shown in FIG. 4, the inspection device 10 according to the embodiment includes an inspection processing device 11 and an inspection management device 12. Here, the inspection processing apparatus 11 and the inspection management apparatus 12 are divided, but this is only an example, and the configuration of the inspection apparatus 10 is not limited to this.

  The inspection processing apparatus 11 includes a probe unit 20 and a placement unit 30. The probe unit 20 further includes a test head 21, a performance board 22, a mounting member 23, and a probe card 24.

  The test head 21 generates a power supply voltage and an electric signal to be applied to the semiconductor device formed on the semiconductor wafer W, and acquires an electric signal output from the semiconductor device in response to the electric signal. Further, the test head 21 determines the quality of the electrical characteristics of the semiconductor device based on the electrical signal acquired from the semiconductor device. In addition, you may perform the quality determination of the electrical property which the test head 21 determines on the inspection management apparatus 12 side.

  The performance board 22 exchanges signals between the test head 21 and the probe card 24. A mounting member 23 for mounting the probe card 24 is provided below the performance board 22. A recess for fitting the probe card 24 is provided below the mounting member 23, and the probe card 24 is fitted into the recess.

  The probe card 24 has a plurality of probe needles 25 that are brought into contact with a plurality of pads formed on the N semiconductor devices, and each of the N semiconductor devices formed on the semiconductor wafer W is input. An electric signal is applied from the probe needle 25 to the pad. Further, the probe card 24 further acquires a plurality of electrical signals respectively output from the output pads of the N semiconductor devices by the probe needle 25 and sends it to the performance board 22.

  The mounting unit 30 includes a stage 31 that attracts the semiconductor wafer W to the upper surface, and a moving mechanism 32 that moves the stage 31 in the X axis direction, the Y axis direction, and the Z axis direction by a plurality of motors (not shown).

  The inspection management device 12 causes the inspection processing device 11 to inspect the semiconductor device, and causes the semiconductor device to be re-inspected based on the inspection result output from the inspection processing device 11.

  As shown in FIG. 5, the inspection management apparatus 12 includes a control unit 40 and a storage unit 41. The control unit 40 further includes a first inspection processing unit 40a, a characteristic defect distribution analysis unit 40b, a second inspection condition determination unit 40c, a second inspection processing unit 40d, and a determination unit 40e.

  The storage unit 41 is a storage area for storing first inspection condition data 41a, first inspection result data 41b, characteristic defect distribution data 41c, second inspection condition data 41d, and second inspection result data 41e. Have

  The first inspection processing unit 40a reads the first inspection condition data 41a from the storage unit 41, and causes the inspection processing apparatus 11 to execute the first wafer inspection based on the first inspection condition data 41a. The first inspection condition data 41a includes information on a set of N or less semiconductor devices (hereinafter referred to as inspection groups) that are simultaneously inspected by the probe card 24.

  Here, as shown in FIG. 6, an example is described in which a probe card 24 is used in which probe needles 25 are simultaneously brought into contact with a total of six semiconductor devices, three in the X direction in the row direction and two in the Y direction. To do. FIG. 6 is a diagram showing the relationship between the probe card 24 and the position of the semiconductor device. In the following, the positions 1 to 6 shown in FIG. 6 are defined as DUT positions 1 to 6, respectively.

  The first inspection condition data 41a includes inspection group information as shown in FIG. FIG. 7 is a diagram showing the relationship between the DUT positions 1 to 6 of the probe card 24 and the position of the semiconductor device on the semiconductor wafer W. The numbers 1-6 shown in FIG. 7 correspond to the DUT positions 1-6 of the probe card 24 shown in FIG. The first inspection condition data 41a includes information on the inspection order of inspection groups. Note that the inspection order of the inspection group is the order in which the probe needles 25 of the probe card 24 contact the inspection group.

  The first inspection processing unit 40a shown in FIG. 5 causes the inspection processing apparatus 11 to inspect the semiconductor devices in the inspection group unit in the order in accordance with the contact order defined in the first inspection condition data 41a, and then on the semiconductor wafer W. The inspection processing apparatus 11 is inspected for the characteristics of all the semiconductor devices formed in the above. Then, the first inspection processing unit 40a acquires the result of the first wafer inspection from the inspection processing apparatus 11, and stores it in the storage unit 41 as the first inspection result data 41b.

  The characteristic defect distribution analysis unit 40b reads the first inspection result data 41b stored in the storage unit 41, and based on the first inspection result data 41b, the semiconductor wafer of the semiconductor device detected as a characteristic defect in the first wafer inspection A distribution on W (hereinafter referred to as a characteristic defective chip distribution) is analyzed. Then, the characteristic defect distribution analyzer 40b analyzes the characteristic defect chip distribution and determines whether the characteristic defect chip distribution is a regular distribution.

  For example, assume that semiconductor devices having poor characteristics are distributed on the semiconductor wafer W as shown in FIG. In this case, since there are a large number of characteristic defects in the semiconductor device at DUT position 1 and the semiconductor device at DUT position 4, the characteristic defect distribution analysis unit 40b shows a regular distribution of the characteristic defect chip distribution. Judge that there is. FIG. 8 is a diagram showing an example of the distribution of characteristic defects of the semiconductor device formed on the semiconductor wafer W. In FIG.

  The characteristic defect distribution analysis unit 40b stores the characteristic defect chip distribution thus analyzed in the storage unit 41 as characteristic defect distribution data 41c.

  The second inspection condition determination unit 40c reads out the characteristic defect distribution data 41c stored in the storage unit 41, and based on the characteristic defect distribution data 41c, the second inspection condition including the condition of the second wafer inspection that is a reinspection. Data 41d is generated.

  That is, in the second inspection condition determining unit 40c, when a regular characteristic defect distribution is found in the characteristic defect chip distribution, the cause of the characteristic defect chip distribution is caused by the inspection apparatus 10 including the probe card 24. Is generated as second inspection condition data 41d. On the other hand, the second inspection condition determination unit 40c does not store the second inspection condition data 41d in the storage unit 41 when no regular characteristic defect distribution is found in the characteristic defect chip distribution.

  The semiconductor device formed on the semiconductor wafer W is manufactured in units of a plurality of units in some manufacturing processes. Here, in the step of the exposure process by the exposure apparatus, as shown in FIG. 9, a total of twelve semiconductor devices, three in the X direction and four in the Y direction, are performed simultaneously. FIG. 9 is a diagram showing the relationship between the exposure process and the position of the semiconductor device. For convenience of explanation, as shown in FIG. 9, the positions of 12 semiconductor devices exposed simultaneously are defined as exposure positions a to l.

  Further, it is assumed that a set of semiconductor devices exposed simultaneously (hereinafter referred to as an exposure group) is in a state as shown in FIG. FIG. 10 is a diagram illustrating an example of a distribution of characteristic defects of a semiconductor device. The alphabets shown in FIG. 10 correspond to the exposure positions a to l of the exposure processing unit shown in FIG.

  Further, the characteristic failure of the semiconductor device shown in FIG. 10 is the same as the characteristic failure of the semiconductor device shown in FIG. That is, FIG. 8 shows the position of the semiconductor device corresponding to the positions of the DUT positions 1 to 6 of the probe card 24, and FIG. 10 shows the position of the semiconductor device corresponding to the positions of the exposure positions a to l in the simultaneous exposure process. Let it be expressed.

  FIG. 11 shows the characteristic failure with respect to the exposure positions a to l in the simultaneous exposure process and the characteristic failure with respect to the DUT positions 1 to 6 of the probe unit 20 for the semiconductor wafer W in the characteristic defect distribution state shown in FIGS. Each is a tabulated table. As shown in FIG. 11, the number of semiconductor devices at the DUT position 1 and the semiconductor device at the DUT position 4 is poor in characteristics, the semiconductor device at the exposure position a, the semiconductor device at the exposure position d, and the exposure position g. There are a large number of semiconductor devices having defective characteristics.

  Therefore, it is difficult to distinguish from the results of the first wafer inspection whether the regularly distributed characteristic defects are caused by the inspection apparatus 10 or the exposure process.

  Therefore, the second inspection condition determination unit 40c shown in FIG. 5 defines an inspection group different from the inspection group defined in the first wafer inspection. That is, the second inspection condition determination unit 40c replaces some semiconductor devices among the six semiconductor devices that simultaneously contact the probe needles 25 of the probe card 24.

  Specifically, the second inspection condition determination unit 40c defines a new inspection group by shifting the position of the probe card 24 (see FIG. 7) in the first wafer inspection. At this time, the second inspection condition determination unit 40c determines the position of the probe card 24 in the first wafer inspection based on the characteristic defect distribution data 41c in the first wafer inspection, the inspection group information, and the exposure processing unit information. It is determined whether to define a new inspection group.

  In the case of the distribution of characteristic defects shown in FIGS. 8 and 10, from the viewpoint of the DUT position of the probe card 24, there are many defects in the semiconductor devices at two DUT positions 1 and 4 that are continuous in the Y direction. Further, from the viewpoint of the exposure position in the simultaneous exposure process, there are many defects in the semiconductor devices at the three consecutive exposure positions a, d, and g in the Y direction.

  In the case of such distribution of characteristic defects, when the second wafer inspection is performed by shifting the position of the probe card 24 in the first wafer inspection to only one semiconductor device in the Y direction, the result of the second wafer inspection is For example, the result shown in FIG. 12 is obtained. FIG. 13 is a table summarizing the characteristic defects for the exposure positions a to l in the simultaneous exposure process and the characteristic defects for the DUT positions 1 to 6 of the probe card 24 in the second wafer inspection.

  As shown in FIG. 13, when the second wafer inspection is performed by shifting the position of the probe card 24 in the first wafer inspection by one semiconductor device in the Y direction, as with the first wafer inspection, the DUT position 1, The semiconductor device No. 4 has many characteristic defects, and the semiconductor devices at the exposure positions a, d, and g have many characteristic defects. Therefore, even if the second wafer inspection is performed, it is difficult to distinguish whether the characteristic defect detected in the first wafer inspection is caused by the inspection apparatus 10 or the exposure process.

  In particular, when a characteristic defect always appears at a specific DUT position, it is easy to determine that it is caused by the inspection apparatus 10 without considering the exposure position. However, as described above, the characteristic at the specific DUT position Often, defects will or may not appear. For example, the characteristic defect may or may not occur depending on the degree of wear of the probe needle 25 and the degree of dust adhesion. In addition, when the range in which the characteristic is determined as a non-defective product is narrow, it may be determined that the characteristic is poor if the contact of the probe needle 25 is poor even a little.

  For this reason, the characteristic defect distribution as shown in FIG. 8 is often shown for the first time when the results of inspecting a plurality of semiconductor wafers W are overlapped. In such a case, it is difficult to determine whether or not the characteristic defect is caused by the inspection apparatus 10.

  In many cases, the relationship between the DUT position and the exposure position is not constant. In such a case, it is difficult to determine whether or not there is a characteristic defect caused by the exposure process due to the exposure process. . In addition, when the appearance rate of characteristic defects changes depending on the conditions of the exposure process, it becomes more difficult to determine whether or not it is caused by the exposure process.

  For example, in the example shown in FIG. 10, exposure positions a to f in [Y7 to Y10: X4 to X6] correspond to DUT positions 1 to 6 (see FIG. 8), respectively, and exposure positions g to l respectively correspond to DUT. It corresponds to positions 1 to 6 (see FIG. 8). On the other hand, the exposure positions a to f in [Y3 to Y6: X4 to X6] correspond to the DUT positions 3, 1, 2, 6, 4, 5 (see FIG. 8), respectively, and the exposure positions g to l are respectively It corresponds to DUT positions 1 to 6 (see FIG. 8).

  As described above, it is difficult to distinguish whether the characteristic defect is caused by the inspection apparatus 10 or the exposure process by the occurrence frequency of the characteristic defect or the relationship between the DUT position and the exposure position.

  Therefore, the second inspection condition determination unit 40c determines the position of the probe card 24 in the first wafer inspection from the DUT positions and exposure positions where the characteristic defects are a predetermined number or more based on the result of the characteristic defects as shown in FIG. To determine how to define a new inspection group.

  In the example shown in FIG. 11, the semiconductor devices at the DUT positions 1 and 4 and the semiconductor devices at the exposure positions a, d, and g tend to have many characteristic defects. As described above, when the position of the probe card 24 in the first wafer inspection is shifted by one semiconductor device in the Y direction, it is difficult to determine the cause of the characteristic failure.

  Therefore, when there is a characteristic defect as shown in FIG. 11, the second inspection condition determination unit 40c shifts the position of the probe card 24 in the first wafer inspection in the Y direction and further shifts by one semiconductor device in the X direction. Define new inspection groups.

  As described above, the second inspection condition determination unit 40c determines how to shift the position of the probe card 24 in the first wafer inspection from the DUT position and the exposure position where the characteristic defects are a predetermined number or more. ing. The second inspection condition determination unit 40c determines a plurality of new inspection groups from the position of the probe card 24 determined as described above, and determines the inspection order of the plurality of new inspection groups. Then, the second inspection condition determination unit 40c stores information including new inspection group information and inspection order information in the storage unit 41 as second inspection condition data 41d.

  Returning to FIG. 5, the description of the control unit 40 will be continued. The second inspection processing unit 40d causes the inspection processing device 11 to re-inspect the characteristics of all the semiconductor devices formed on the semiconductor wafer W based on the second inspection condition data 41d stored in the storage unit 41. Specifically, the second inspection processing unit 40d reads the second inspection condition data 41d from the storage unit 41, and the inspection in which the semiconductor device is specified in accordance with the specified inspection order based on the second inspection condition data 41d. The inspection processing apparatus 11 is inspected for each group.

  As a result, the characteristics of all the semiconductor devices formed on the semiconductor wafer W are re-inspected by the inspection processing apparatus 11. Then, the second inspection processing unit 40d stores the result of the second wafer inspection in the storage unit 41 as the second inspection result data 41e. The second inspection processing unit 40d does not perform the second wafer inspection on the semiconductor wafer W that has been subjected to the first wafer inspection when the second inspection condition data 41d is not stored in the storage unit 41. .

  The determination unit 40e reads the second inspection result data 41e from the storage unit 41, and whether the reason why the characteristic defect distribution is a regular distribution is caused by the inspection apparatus 10 including the probe card 24, or exposure. It is determined whether it is caused by the process.

  For example, it is assumed that the second inspection condition data 41d includes information defining a new inspection group by shifting the position of the probe card 24 in the first wafer inspection by one semiconductor device in the X direction and the Y direction, respectively.

  Then, when the second wafer inspection is performed on the new inspection group, if the result of the second wafer inspection is as shown in FIG. 14, for example, the total result of characteristic defects is shown in FIG. As shown. FIG. 14 is a diagram illustrating an example of the distribution of characteristic defects of the semiconductor device, and FIG. 15 is a diagram illustrating a relationship example between the characteristic defects of the semiconductor device and the exposure positions a to 1 and the DUT positions 1 to 6. From these tabulation results, there is a tendency that the semiconductor devices at the DUT positions 2 and 6 and the semiconductor devices at the exposure positions a, d, and g have many characteristic defects.

  As described above, in the first wafer inspection, the semiconductor devices at the DUT positions 1 and 4 and the semiconductor devices at the exposure positions a, d, and g tend to have many characteristic defects. Therefore, the first wafer inspection and the second wafer inspection share the same tendency for many characteristic defects in the semiconductor devices at the exposure positions a, d, and g. Therefore, the determination unit 40e determines that the reason why the characteristic defect distribution is a regular distribution is due to the exposure process.

  On the other hand, when the second wafer inspection is performed on a new inspection group, if the result of the second wafer inspection is as shown in FIG. 16, for example, the total result of characteristic defects is shown in FIG. It becomes like this. FIG. 16 is a diagram illustrating an example of the distribution of characteristic defects of the semiconductor device, and FIG. 17 is a diagram illustrating a relationship example between the characteristic defects of the semiconductor device and the exposure positions a to 1 and the DUT positions 1 to 6. From these tabulation results, there is a tendency that the semiconductor devices at the DUT positions 1 and 4 and the semiconductor device at the exposure position k have many characteristic defects.

  In the first wafer inspection, as shown in FIG. 11, the semiconductor devices at the DUT positions 1 and 4 and the semiconductor devices at the exposure positions a, d, and g tend to have many characteristic defects. Therefore, the first wafer inspection and the second wafer inspection share a common tendency for the semiconductor devices at the DUT positions 1 and 4 to have many characteristic defects. Therefore, the determination unit 40e determines that the cause that the characteristic defect distribution is a regular distribution is due to the inspection apparatus 10 including the probe card 24.

  In this way, the determination unit 40e can distinguish whether the reason why the characteristic defect distribution is a regular distribution is due to the inspection apparatus 10 or due to the exposure process. An erroneous determination of the inspection apparatus 10 can be detected with high accuracy.

  In the above description, the first mode in which the second wafer inspection is performed on all the semiconductor devices formed on the semiconductor wafer W has been described. However, the inspection apparatus 10 performs the second wafer inspection on some semiconductor devices. The second mode to be performed can also be executed.

  When all semiconductor devices are inspected in the second wafer inspection, if the semiconductor device that has detected the characteristic failure in the first wafer inspection detects the characteristic failure in the second wafer inspection, the second wafer inspection is useless. turn into. Therefore, in such a case, the manufacturing cost of the semiconductor device is increased. Therefore, in the inspection apparatus 10 according to the embodiment, the second mode in which the second wafer inspection is performed on some semiconductor devices can be executed.

  Specifically, the second inspection condition determination unit 40c reads out the characteristic defect distribution data 41c stored in the storage unit 41, and the second defective condition semiconductor device has the second or more DUT positions and exposure positions out of a predetermined number or more. The semiconductor device that performs wafer inspection is sampled to generate second inspection condition data 41d.

  For example, it is assumed that there is a semiconductor device with poor characteristics as shown in FIG. In this case, the second inspection condition determination unit 40c performs the detection of the characteristic defect in the first wafer inspection with respect to the semiconductor devices at the exposure positions a, d, and g where the characteristic defect is large in the first wafer inspection. Randomly sample 3 DUT positions from 3, 5 and 6.

  Then, the second inspection condition determining unit 40c applies the DUT positions 2, 3, 5, and 6 to a part of the semiconductor devices at the exposure positions a, d, and g that are determined to have a characteristic defect in the first wafer inspection. The second inspection condition data 41d is generated so as to be the DUT position selected from.

  If the result of the second wafer inspection performed by the second inspection processing unit 40d based on the second inspection condition data 41d generated in this way is as shown in FIG. Is as shown in FIG. FIG. 18 is a diagram illustrating an example of the distribution of characteristic defects of the semiconductor device, and FIG. 19 is a diagram illustrating a relationship example between the characteristic defects of the semiconductor device and the exposure positions a to 1 and the DUT positions 1 to 6. From the total result, it can be seen that the semiconductor devices at the exposure positions a, d, and g have defective characteristics, as in the first wafer inspection result.

  Therefore, even if all the semiconductor devices are inspected in the second wafer inspection, the second inspection processing unit 40d determines that the semiconductor device at the same position as in the first wafer inspection is likely to have a characteristic defect, and the remaining The second wafer inspection is not performed on this semiconductor device. On the other hand, if the semiconductor devices at the exposure positions a, d, and g are not defective, the second wafer inspection is performed on the remaining semiconductor devices. As a result, useless inspection can be avoided, and as a result, an increase in manufacturing cost of the semiconductor device can be reduced.

  In the example shown in FIGS. 18 and 19 described above, the second wafer inspection is performed on each semiconductor device at the exposure positions a, d, and g. However, the sampling of the inspection target is not limited to this. I can't. For example, the second wafer inspection may be performed on each of two or more semiconductor devices at the exposure positions a, d, and g.

  In the first wafer inspection, when a plurality of characteristic inspections are performed on each semiconductor device, a part of the plurality of characteristic inspections performed in the first wafer inspection is performed in the second wafer inspection. May be.

  For example, the second inspection condition determination unit 40c selects the characteristic inspection having a larger number of characteristic defects than the other characteristic inspections from among the plurality of characteristic inspections, and generates the second inspection condition data 41d. Also good. By doing so, it is possible to shorten the inspection time in the second wafer inspection, and as a result, it is possible to reduce an increase in manufacturing cost of the semiconductor device.

  In particular, by performing the second wafer inspection on the characteristic determined as the regular characteristic defect among the characteristic inspections performed in the first wafer inspection, it is possible to further reduce the inspection time in the second wafer inspection. it can.

  Next, a processing procedure executed by the inspection apparatus 10 according to the embodiment will be described with reference to FIG. FIG. 20 is a flowchart illustrating a processing procedure executed by the inspection apparatus 10 according to the embodiment.

  As shown in FIG. 20, the first inspection processing unit 40a causes the inspection processing apparatus 11 to execute the first wafer inspection, and stores the result of the first wafer inspection in the storage unit 41 (step S10). Next, the characteristic defect distribution analysis unit 40b analyzes the characteristic defect distribution based on the result of the first wafer inspection stored in the storage unit 41 (step S11).

  Next, the second inspection condition determination unit 40c determines whether there is a regular distribution of characteristic defects based on the characteristic defect distribution data stored in the storage unit 41 (step S12). In this determination, when it is determined that there is a distribution of regular characteristic defects (Yes in step S12), the second inspection condition determination unit 40c determines the second inspection condition and stores it in the storage unit 41 (step S12). S13).

  Next, the second inspection processing unit 40d performs a second wafer inspection on some semiconductor devices (step S14). Then, the second inspection processing unit 40d determines whether or not the semiconductor device that has performed the second wafer inspection is determined to have a characteristic defect (step S15).

  When it is determined that the semiconductor device that has performed the second wafer inspection has a characteristic failure (Yes in step S15), the second inspection processing unit 40d determines that the characteristic failure detected in the first wafer inspection is caused by the exposure process It determines with it being inferior and displays a determination result on the display apparatus not shown provided in the test | inspection apparatus 10 (step S20).

  On the other hand, if it is determined that the semiconductor device that has undergone the second wafer inspection is not defective in characteristics (No at Step S15), the second inspection processing unit 40d performs the second wafer inspection on the remaining semiconductor devices (Step S16). ).

  Subsequently, the determination unit 40e analyzes the result of the second wafer inspection (step S17), and determines whether or not the analysis result is a characteristic defect caused by the exposure process (step S18). And when it determines with this analysis result being the characteristic defect resulting from an exposure process (step S18, Yes), the determination part 40e displays a determination result on the display apparatus not shown provided in the inspection apparatus 10 ( Step S20), the inspection process is terminated.

  If it is determined that the analysis result is not a characteristic defect due to the exposure process (No in step S18), the determination unit 40e similarly displays the determination result on a display device (not shown) provided in the inspection apparatus 10. (Step 19), and the inspection process is terminated. In Step S12, when it is determined that there is no regular characteristic defect distribution (No in Step S12), the inspection process is terminated.

  In step S12, when it is determined that there is a distribution of regular characteristic defects, the processing after step S13 is performed. However, even if there is no distribution of regular characteristic defects, a characteristic defect occurs. When the number of semiconductor devices is equal to or greater than a predetermined number, the processing after step S13 may be performed. Whether or not the distribution of regular characteristic defects is determined by, for example, determining whether or not the characteristic defects at a specific DUT position or exposure position are a predetermined number or more.

  As described above, in the inspection method and inspection apparatus according to the embodiment, the position of the probe card 24 for simultaneously inspecting a plurality of semiconductor devices is moved relative to the semiconductor wafer W, and the semiconductor wafer is subjected to the first wafer inspection. A first inspection process for inspecting the characteristics of all semiconductor devices formed on W is performed.

  Thereafter, the position of the probe card 24 with respect to the semiconductor wafer W is changed from the time of the first wafer inspection based on the distribution on the semiconductor wafer W of the semiconductor device determined to have a characteristic defect by the first inspection step, and then by the second wafer inspection. A second inspection step for reinspecting the characteristics of the semiconductor device is performed.

  Then, a determination process is performed for determining a characteristic defect that occurs in a manufacturing process performed in units of a plurality of semiconductor devices among the characteristic defects of the semiconductor device based on the result of the re-inspection in the second inspection process.

  Therefore, according to the inspection method and the inspection apparatus according to the embodiment, the reason why the characteristic defect distribution is a regular distribution is caused by the inspection apparatus 10 such as the probe card 24 or the exposure process. Can be distinguished. Therefore, it is possible to accurately detect an erroneous determination of the inspection apparatus 10.

  In the above description, the first wafer inspection and the second wafer inspection are performed for each semiconductor wafer W. However, the present invention is not limited to this. For example, the second wafer inspection may be performed based on the result of performing the first wafer inspection on the plurality of semiconductor wafers W.

  In this way, for example, even when the result of inspecting a plurality of semiconductor wafers is superimposed several times and the characteristic defect distribution as shown in FIG. And manufacturing defects can be accurately detected.

  In this case, for example, the first inspection processing unit 40a performs a first wafer inspection on a prescribed number of semiconductor wafers, and stores the results in the storage unit 41 as first inspection condition data 41a. Then, the characteristic defect distribution analysis unit 40b reads the plurality of first inspection condition data 41a from the storage unit 41, and superimposes these first inspection condition data 41a.

  For example, if the first inspection condition data 41a detects a characteristic defect in the inspection processing apparatus 11 for every 300 coordinates in the range of [X1 to X15: Y1 to Y20] shown in FIG. "If no characteristic failure is detected, information" 0 "is included. In this case, the characteristic defect distribution analysis unit 40b superimposes the first inspection condition data 41a by adding each coordinate of the first inspection condition data 41a.

  For example, when there are ten pieces of the first inspection condition data 41a, the coordinate data of [X10: Y12] are “0”, “1”, “0”, “0”, “1”, “1”, “ In the case of “1”, “0”, “0”, “0”, the coordinate data of [X10: Y12] becomes “5” as a result of superposition.

  Then, the characteristic defect distribution analysis unit 40b analyzes the characteristic defect chip distribution based on the first inspection condition data 41a superimposed in this manner, and whether the characteristic defect chip distribution shows a regular distribution. Determine. When the characteristic defective chip distribution shows a regular distribution, the second inspection condition determining unit 40c generates the second inspection condition data 41d, and the second inspection condition data 41d is used to perform the second inspection. The processing unit 40d performs the second wafer inspection.

  In the above description, the arrangement of the semiconductor devices that can be simultaneously contacted by the probe card 24 is four (2 columns × 2 rows) or six (3 columns × 2 rows), and the arrangement of the semiconductor devices that are simultaneously exposed in the exposure process is 2 ×. Although it is set to 4 of 2 rows and 12 of 3 columns × 4 rows, it is not limited to this. For example, it is sufficient if the arrangement of semiconductor devices that can be simultaneously contacted by the probe card 24 is included in the arrangement of semiconductor devices that are simultaneously exposed in the exposure process, or vice versa.

  Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10 inspection device, 22 performance board, 24 probe card, 32 moving mechanism, 40 control unit

Claims (5)

A first wafer inspection process for inspecting the characteristics of the semiconductor device formed on the semiconductor wafer in units of the plurality of units while moving the position of the probe card with which the probe needles are simultaneously brought into contact with the plurality of semiconductor devices with respect to the semiconductor wafer; ,
The position of the probe card with respect to the semiconductor wafer is shifted from the position of the first wafer inspection step based on the distribution of the semiconductor device determined to be defective in the characteristics of the first wafer inspection step on the semiconductor wafer. A second wafer inspection process for re-inspecting the characteristics of
A determination step of determining, among the characteristic defects of the semiconductor device, a characteristic defect that occurs in a manufacturing process performed in units of a plurality of semiconductor devices based on a result of re-inspection by the second wafer inspection step;
A method for inspecting a semiconductor device including: The second wafer inspection step includes
After reinspecting a part of the semiconductor devices determined to have the characteristic failure, if it is determined that the part of the semiconductor devices have no characteristic failure, reinspection of the remaining semiconductor devices is continued. A method for inspecting a semiconductor device according to claim 1. The second wafer inspection step includes
3. The method for inspecting a semiconductor device according to claim 1, wherein an inspection is performed for a characteristic determined as a characteristic defect in the first wafer inspection step. The manufacturing process includes
The method for inspecting a semiconductor device according to claim 1, wherein the inspection method is an exposure process. A probe card for simultaneously contacting a probe needle with a plurality of semiconductor devices;
A moving mechanism for moving the position of the probe card with respect to the semiconductor wafer;
A controller that detects characteristics of the semiconductor device formed on the semiconductor wafer using the probe card, and
The controller is
A first wafer inspection process for inspecting characteristics of a semiconductor device formed on the semiconductor wafer in a plurality of units while moving the position of the probe card with respect to the semiconductor wafer;
The position of the probe card with respect to the semiconductor wafer is shifted from the position of the first wafer inspection step based on the distribution on the semiconductor wafer of the semiconductor device determined to have a characteristic defect by the first wafer inspection process, and the semiconductor A second wafer inspection process for re-inspecting the characteristics of the apparatus;
A determination process for determining, among the characteristic defects of the semiconductor device, a characteristic defect generated in a manufacturing process performed in units of a plurality of semiconductor devices based on a result of re-inspection by the second wafer inspection process;
An inspection apparatus for a semiconductor device, wherein:

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