KR102425048B1 - Inspection apparatus of beam for testing of semiconductor, and method of inspection for beam - Google Patents

Abstract

A beam inspection apparatus for testing a semiconductor device is provided. The beam inspection apparatus for testing a semiconductor device is configured to determine whether an error occurs in data stored in a base board, a plurality of memory chips arranged on the base board, and data stored in the plurality of memory chips by the test beams irradiated to the plurality of memory chips. and an integrated control unit for checking and evaluating the uniformity of the beam and the size of the beam using whether data stored in the plurality of memory chips has errors. It may include a plurality of first memory chips provided to form a central region, and second memory chips arranged from the central region toward an edge of the base board to form a radiation region.

Description

Inspection apparatus of beam for testing of semiconductor, and method of inspection for beam

The present application relates to a beam inspection apparatus and a beam inspection method, and more particularly, to a beam inspection apparatus and a beam inspection method for testing a semiconductor device.

Semiconductor inspection equipment can be broadly divided into main tester, probe station, handler, and burn-in equipment. , It is classified into component inspection equipment such as handlers that evaluates the normal operation of the package at the final stage after completing the pre- and post-processing of semiconductors, and module inspection equipment that inspects whether a module works properly in the state of a module with several semiconductor elements mounted on the PCB. can do.

As semiconductor devices are miniaturized, various semiconductor inspection apparatuses are being developed.

For example, Korean Patent Publication No. 10-1679527 discloses a light generator for generating light irradiated to a semiconductor device, which is a device under test, and a test signal applying section for applying a test signal for driving the semiconductor device to the semiconductor device. , a photodetector that detects the reflected light reflected from the semiconductor device when the light is irradiated to the semiconductor device and outputs a detection signal; A first spectrum analyzer to measure; an analysis unit for deriving phase information of the detection signal at the predetermined frequency based on the first phase information and the second phase information, wherein the first spectrum analyzer operates the first spectrum analyzer Measures the first phase information with respect to the frequency of the reference signal, the second spectrum analyzer measures the second phase information for the frequency of the reference signal that operates the second spectrum analyzer, Disclosed is a semiconductor device inspection apparatus in which the frequency and phase of a reference signal are synchronized with the frequency and phase of the reference signal of the second spectrum analyzer.

One technical problem to be solved by the present application is to provide a high-reliability beam inspection apparatus and a beam inspection method for testing a semiconductor device.

Another technical problem to be solved by the present application is to provide a beam inspection apparatus and a beam inspection method capable of confirming information on the uniformity and flux of a beam for testing a semiconductor device.

Another technical problem to be solved by the present application is to provide a beam inspection apparatus and a beam inspection method for testing a semiconductor device having a reduced inspection time.

Another technical problem to be solved by the present application is to provide a beam inspection apparatus and a beam inspection method for semiconductor device testing that facilitate quantitative analysis of a beam through bit map analysis.

Another technical problem to be solved by the present application is to provide a beam inspection apparatus and a beam inspection method for testing a semiconductor device in which inspection costs are saved.

Another technical problem to be solved by the present application is to provide a beam inspection apparatus and a beam inspection method for testing a semiconductor device capable of easily inspecting beams of various types and sizes.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problem, the present application provides a beam inspection apparatus for testing a semiconductor device.

According to an embodiment, the beam inspection apparatus for testing a semiconductor device includes a base board, a plurality of memory chips arranged on the base board, and the plurality of memory chips by a test beam irradiated to the plurality of memory chips. and an integrated control unit configured to check whether an error occurs in data stored in the memory chip and evaluate the uniformity of the beam and the size of the beam using whether data stored in the plurality of memory chips has an error, wherein the plurality of memories The chip may include a plurality of first memory chips provided in one region of the base board to form a central region, and second memory chips arranged from the central region toward an edge of the base board to form a radiation region. can

According to an embodiment, the first memory chips are two-dimensionally arranged in rows and columns in the one region of the base board, and the second memory chips are located at the edge of the central region of the base board. It may include being one-dimensionally arranged toward the edge of.

According to an embodiment, the radiation area may include providing a plurality.

According to an embodiment, the test beam is irradiated to the central region and the radiation region, and the integrated control unit determines whether an error occurs in data stored in the first memory chips forming the central region, and the test beam and evaluating the size of the test beam based on whether data stored in the second memory chips forming the radiation region has an error.

According to an embodiment, the plurality of memory chips may include SRAM.

In order to solve the above technical problem, the present application provides a beam inspection method for testing a semiconductor device.

According to an embodiment, the method of inspecting a beam for testing a semiconductor device includes preparing a beam inspection apparatus for testing a semiconductor device, irradiating a test beam to the beam inspection device for testing a semiconductor device, and the irradiated test beam and evaluating the uniformity and size of may include evaluating whether or not an error occurs in data stored in the plurality of memory chips by the test beam.

According to an embodiment, the evaluating the uniformity and size of the test beam may include determining an error rate of data stored in the plurality of memory chips by the test beam, and location information of the plurality of memory chips in which the error occurred. It may include evaluating the uniformity and size of the test beam.

According to an embodiment of the present application, a beam inspection apparatus for testing a semiconductor device may include a base board, a plurality of memory chips arranged on the base board, and an integrated control unit, wherein the integrated control unit includes the plurality of memories It is possible to check whether an error occurs in the data stored in the plurality of memory chips due to the test beam irradiated to the chip, and to evaluate the uniformity of the beam and the size of the beam by using whether the error in the data stored in the plurality of memory chips occurs and the intensity of the beam can be quantified.

Accordingly, the uniformity of the actual flux value of the test beam used for testing the semiconductor device, as well as the actual size of the test beam can be easily and accurately evaluated, whereby the test of the semiconductor device using the test beam The reliability of the results can be improved.

1 is a flowchart illustrating an inspection method using a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application.
2 and 3 are diagrams for explaining a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application.
4 is a view for explaining a test beam irradiated to a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application.
5 is a view for explaining a plurality of memory chips included in the beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application and a beam inspection method using the same.
6 to 8 are views for explaining a cell array of a plurality of memory chips included in the beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application and a beam inspection method using the same.
9 is a view for explaining an integrated control unit included in the beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application.
10 is a diagram for describing a beam inspection apparatus for testing a semiconductor device according to a modified example of an embodiment of the present application.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

Also, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in this specification, 'and/or' is used in the sense of including at least one of the elements listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification exists, and one or more other features, numbers, steps, or configurations It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in this specification, "connection" is used in a sense including both indirectly connecting a plurality of components and directly connecting a plurality of components.

In addition, in the following description of the present invention, if it is determined that a detailed description of a related well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the present application, "beam" includes radiation, and may be interpreted as including radiation particles such as alpha particles, neutrons, and protons. SEU), multi bit upset (MBU), multi cell upset (MCU), etc. can be interpreted as including soft errors.

In addition, the subject who manufactures and sells the beam inspection apparatus for testing a semiconductor device described in the specification of the present application and the subject who performs the beam inspection method using the beam inspection apparatus for testing a semiconductor device described in the specification of the present application may be different. It is self-evident that

1 is a flowchart for explaining an inspection method using a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application, and FIGS. 2 and 2 are a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application 4 is a view for explaining a test beam irradiated to a beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application, and FIG. 5 is a beam inspection for testing a semiconductor device according to an embodiment of the present application It is a view for explaining a plurality of memory chips included in an apparatus and a beam inspection method using the same, and FIGS. 6 to 8 are cells of a plurality of memory chips included in the beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application. It is a view for explaining an array and a beam inspection method using the same, and FIG. 9 is a view for explaining an integrated control unit included in the beam inspection apparatus for testing a semiconductor device according to an embodiment of the present application.

1 and 2 , the beam inspection apparatuses 100 and 200 for testing semiconductor devices are prepared ( S110 ).

The beam inspection apparatuses 100 and 200 for testing semiconductor devices may include an inspection board 100 and an integrated control unit 200 .

The test board 100 may include a base board 110 and a plurality of memory chips 120 arranged on the base board 110 .

The base board 110 includes a first connector 112 and a second connector 114 connected to the integrated control unit 200 , and the plurality of memory chips 120 are disposed on the base board 110 . can be mounted and arranged.

According to an embodiment, in the plurality of memory chips 120 , an error in data stored in the plurality of memory chips 120 is easily and high by the test beam irradiated to the plurality of memory chips 120 . It may be a type of memory chip that occurs frequently. For example, the plurality of memory chips 120 may be SRAM. Accordingly, as will be described later, it can be easily and quickly checked whether an error occurs in the data stored in the plurality of memory chips 120 by the test beam, and thus, the uniformity of the test beam and the test beam An evaluation of the size of can be easily performed.

As shown in FIG. 3 , the plurality of memory chips 120 may form a center region 122 and a radiation region 124 on the base board 110 .

Specifically, the plurality of memory chips 120 include first memory chips provided in plurality in one region of the base board 110 to form the central region 122 , and the first memory chips in the central region 122 . Second memory chips arranged toward the edge of the base board 110 to form the radiation region 124 may be included.

According to an embodiment, the first memory chips and the second memory chips may be the same type of memory chip (eg, SRAM).

The first memory chips may be intensively disposed in the one region of the base board 110 to form the central region 122 . According to an embodiment, as shown in FIG. 3 , the first memory chips form rows and columns and are disposed in the one region of the base board 110 to form the central region 122 . . Alternatively, according to another embodiment, the first memory chips may be disposed in the one area of the base board 110 and may be randomly disposed to form the central area 122 .

The second memory chips may be arranged from the edge of the central region 122 toward the edge of the base board 110 to form the radiation region 124 . In other words, the radiation region 124 may be radiated from the central region 122 including the first memory chips, that is, the one region of the base board 110 . According to an embodiment, as shown in FIG. 3 , the second memory chips may be one-dimensionally arranged from the edge of the central region 122 toward the edge of the base board 110 . In other words, the second memory chips may be arranged one by one from the edge of the central region 122 toward the edge of the base board 110 . Alternatively, according to another embodiment, the second memory chips are arranged from the edge of the central region 122 toward the edge of the base board 110 , and may be two-dimensionally arranged in columns and rows.

The radiation region 124 including the second memory chips may be provided in plurality. That is, as shown in FIG. 3 , from four sides of the central region 122 in which the first memory chips are two-dimensionally arranged in rows and columns, toward the edge of the base board 110 , the As second memory chips are arranged, four radiation regions 124 may be provided. The technical idea according to the embodiment of the present application is not limited to four radiation areas 124, and it is apparent to those skilled in the art that three or less, or five or more radiation areas 124 may be provided.

Also, as described above, when a plurality of radiation regions 124 are provided, according to an embodiment, the plurality of radiation regions 124 may have the same length. Alternatively, according to another embodiment, the lengths of the plurality of radiation regions 124 may be different from each other.

Also, as described above, when a plurality of the radiation regions 124 are provided, the number of the second memory chips included in each of the plurality of radiation regions 124 may be the same according to an embodiment. have. Alternatively, according to another embodiment, the number of the second memory chips included in each of the plurality of radiation regions 124 may be different from each other.

Referring to FIG. 4 , the test beam 300 may be irradiated to the beam inspection apparatuses 100 and 200 for testing a semiconductor device ( S120 ).

According to one embodiment, the test beam 300, as described in the preamble (boilerplate) of the present application, to include radiation, including at least one of alpha particles, neutrons, and protons can

The test beam 300 may be irradiated to the base board 100 of the beam inspection apparatuses 100 and 200 for testing semiconductor devices. Specifically, the test beam 300 may be irradiated by aiming the central region 122 . Accordingly, the central region of the test beam 300 may be mainly irradiated to the central region 122 , and the peripheral region of the test beam 300 may be mainly irradiated to the radiation region 124 .

The uniformity and size of the irradiated test beam 300 may be evaluated (S130).

As described above, the first memory chip and the second memory chip are formed between the first memory chip and the second memory chip by the test beam 300 irradiated to the central region 122 and the radiation region 124 . It may be a type of memory chip in which errors of data stored in the second memory chip occur easily and with high frequency. Accordingly, an error may occur in data stored in the first memory chip and the second memory chip forming the central region 122 and the radiation region 124 by irradiation of the test beam 300 . .

The integrated control unit 200 may evaluate the uniformity of the test beam 300 based on whether data stored in the first memory chips forming the central region 122 has an error, and the radiation region 124 . ), the size of the test beam 300 may be evaluated based on whether data stored in the second memory chips forming an error occurs.

For example, as shown in FIG. 5 , the first memory chips A1 to A25 form the central region 122 , the test beam 300 is irradiated, and When the uniformity is excellent, that is, when substantially the same level of flux is provided to the first memory chips A1 to A25, each of the first memory chips A1 to A25 has substantially the same ratio and level of the test beam An error may occur in data stored in the first memory chips A1 to A25 by 300 . In other words, when data errors occur in the first memory chips A1 to A25 at substantially the same rate and level in the first memory chips A1 to A25 after the test beam 300 is irradiated, the test The flux value of the beam 300 may be evaluated as having a high uniformity according to a position. On the other hand, for example, among the first memory chips A1 to A25 , in the case of the first memory chips A1 to A10 located at the upper end, the rate and level of data errors are low, and the first memory located at the lower end In the case of chips A16 to A25, when the rate and level of data error are high, the flux value of the upper region of the test beam 300 is evaluated to be lower than the flux value of the lower region, and the test beam 300 The flux value can be evaluated as having low uniformity depending on the location.

Also, for example, as shown in FIG. 5 , the second memory chips B1 to B20 may form the radiation region 124 , and the test beam 300 may be irradiated. At this time, among the second memory chips B1 to B20, an error occurs in data stored in some of the second memory chips B1, B2, B6, B7, B11, B12, B16, and B17, and the remaining When an error does not occur in the data stored in the second memory chips B3 to B5, B8 to B10, B13 to B15, and B18 to B20, the second memory chips B1, B2, B6, B7, B11 in which an error occurs , B12, B16, B17), the actual size of the test beam 300 can be evaluated.

Also, each of the first and second memory chips A1 to A25 and B1 to B20 may include a plurality of cells. In this case, the uniformity and size of the test beam 300 is improved through the error rate and level of data stored in the plurality of cells included in the first and second memory chips A1 to A25 and B1 to B20. can be evaluated finely.

Specifically, for example, as shown in FIGS. 5 to 7 , after the test beam 300 is irradiated, a faulty cell and a normal cell may be identified in the first memory chips A1 to A25. . The first region of the test beam 300 corresponding to the cell in which the error occurs may be evaluated as having a flux value of the test beam 300 equal to or greater than a reference value, and the first memory chips A1, A2, A6, and A7. In the second region of the test beam 300 corresponding to the normal cell of The value may be evaluated to be less than or equal to the reference value. Accordingly, the second region of the test beam 300 corresponding to the normal cell may be evaluated as an abnormal region 300A or a non-uniform region 300A having a lower flux value compared to other regions.

In addition, specifically, for example, as shown in FIGS. 5 and 8 , after the test beam 300 is irradiated, in the second memory chips B1 to B20, an error occurrence cell and a normal cell are confirmed. can be In the third area of the test beam 300 corresponding to the cell in which the error occurs, it may be evaluated that the flux value of the test beam 300 is equal to or greater than a reference value. Accordingly, the boundary between the erroneous cell and the normal cell may be evaluated as a substantial size of the test beam 300 .

The uniformity and size of the irradiated test beam 300 may be evaluated by the integrated controller 200 of the beam inspection apparatuses 100 and 200 for testing a semiconductor device.

As shown in FIG. 9 , the integrated control unit 200 may include a power management unit 210 , an FPGA unit 220 , and a data processing unit 230 .

The power management unit 210 is connected to the second connector 114 of the base board 110 to supply power to the plurality of memory chips and the plurality of memory chips and/or memory cells included therein. voltage and current, and when a power failure occurs in the plurality of memory chips, the supply power may be cut off.

The FPGA unit 220 may be connected to the second connector 114 of the base board 110, store data for each bitmap, and perform matching analysis for logical bitmaps and physical bitmaps, Whether or not an error has occurred in the data stored in the plurality of memory chips and an error occurrence type may be distinguished and counted, and through this, the flux value of the test beam 300 may be calculated, evaluated, and derived. Also, the FPGA unit 220 may control the power management unit 210 and control pins for addressing and controlling the plurality of memory chips.

The data processing unit 230 may receive and process a bitmap for checking the flux value of the test beam 300 and an error counter map according to time from the FPGA unit 220, and monitor the processed data. may be displayed to the user.

It will be understood by those skilled in the art that the operation performed by the integrated control unit 200 in the above-described embodiment of the present invention may be performed by computer program instructions. These computer program instructions may be embodied in the processor of a general purpose computer, special purpose computer, or other programmable data processing equipment, such that the instructions performed by the processor of the computer or other programmable data processing equipment are not shown in the flowchart block(s). It creates means for performing the functions of the embodiments of the invention.

These computer program instructions may also be stored in a computer-usable or computer-readable memory that may direct a computer or other programmable data processing equipment to implement a function in a particular manner, and thus the computer-usable or computer-readable memory. The instructions stored in the . It is also possible to produce a manufactured item including an instruction means for performing a function according to an embodiment of the present invention.

The computer program instructions may also be mounted on a computer or other programmable data processing equipment, such that a series of operational steps are performed on the computer or other programmable data processing equipment to create a computer-executed process to create a computer or other programmable data processing equipment. It is also possible that instructions for performing the processing equipment provide steps for performing the functions described in the flowchart block(s).

Additionally, each block may represent a module, segment, or portion of code that includes one or more executable instructions for executing specified logical function(s). It is also possible for the functions mentioned in blocks to occur out of order in some alternative implementations. For example, it is possible that two blocks shown in succession are actually performed substantially simultaneously, or that the blocks are sometimes performed in the reverse order according to the corresponding function.

In the case of the test beam 300 for testing a semiconductor device, the specifications (eg, size, flux value, etc.) of the test beam 300 are described in the device for generating the test beam 300 , but the described specifications There were frequent cases where the actual physical property values of the test beam 300 and the test beam 300 did not match. When a semiconductor device is tested using the test beam 300 , reliability of a test result of the semiconductor device may be deteriorated, and a test time of the semiconductor device may be increased.

However, as described above, according to the embodiment of the present application, the test beam 300 is irradiated to the beam inspection apparatus 100 or 200 for testing a semiconductor device, and an error occurs in data stored in the plurality of memory chips. Through whether or not, the uniformity and size of the test beam 300 may be evaluated.

Accordingly, the actual uniformity and size of the test beam 300 used for testing the semiconductor device can be easily and accurately evaluated, and the reliability of the test result of the semiconductor device using the test beam 300 can be improved. can

10 is for explaining a beam inspection apparatus for testing a semiconductor device according to a modified example of an embodiment of the present application.

Referring to FIG. 10 , the inspection board 100 according to the embodiment of the present application described with reference to FIGS. 1 to 9 is provided, and the plurality of memories are provided in the core region 122a of the central region 122 . Chips may be omitted.

When the test beam 300 is irradiated by aiming at the central region 122, the probability that the core region 122a of the central region 122 to which the test beam 300 is irradiated has substantially the same uniformity this is high Accordingly, the plurality of memory chips may be omitted on the core region 122a, and accordingly, the number of the plurality of memory chips used for inspection of the test beam 300 may be reduced.

As mentioned above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

100: board for inspection
110: base board
112: first connector
114: second connector
120: a plurality of memory chips
122: central area
122a: core area
124: radiation area
200: integrated control
210: power management unit
220: FPGA unit
230: data processing unit
300: test beam
300A: Abnormal area
A1 to A25: first memory chip
B1 to B20: second memory chip

Claims (7)

base board;
a plurality of memory chips arranged on the base board; and
It is checked whether an error occurs in the data stored in the plurality of memory chips due to the test beam irradiated to the plurality of memory chips, and the uniformity of the beam and the beam is determined using whether or not an error occurs in the data stored in the plurality of memory chips. comprising an integrated control for estimating the size,
The plurality of memory chips,
a plurality of first memory chips provided in one region of the base board to form a central region; and
and second memory chips arranged from the central region toward an edge of the base board to form a radiation region.
The method of claim 1,
The first memory chips are two-dimensionally arranged in rows and columns in the one region of the base board,
and wherein the second memory chips are one-dimensionally arranged from an edge of the central region toward an edge of the base board.
The method of claim 1,
The radiation region is a beam inspection apparatus for testing a semiconductor device comprising a plurality of.
The method of claim 1,
The test beam is irradiated to the central region and the radiation region,
The integrated control unit,
evaluating the uniformity of the test beam based on whether data stored in the first memory chips forming the central region has an error,
and evaluating the size of the test beam based on whether data stored in the second memory chips forming the radiation region has an error.
The method of claim 1,
The plurality of memory chips include SRAM, or
The integrated control unit analyzes the intensity of the test beam by using the bitmaps of the plurality of memory chips.
preparing a beam inspection apparatus for testing a semiconductor device;
irradiating a test beam to the beam inspection apparatus for inspecting semiconductor devices; and
Comprising the step of evaluating the uniformity and size of the irradiated test beam,
The semiconductor element inspection beam inspection device,
a base board, and a plurality of memory chips arranged on the base board,
and evaluating the uniformity and size of the irradiated test beam based on whether or not an error occurs in data stored in the plurality of memory chips by the test beam.
7. The method of claim 6,
Evaluating the uniformity and size of the test beam comprises:
and evaluating the uniformity and size of the test beam by using the error occurrence rate of data stored in the plurality of memory chips by the test beam, and location information of the plurality of memory chips in which the error has occurred. For beam inspection methods.

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