JP2011210775A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of reducing inspection cost, analysis cost and manufacturing cost.SOLUTION: In a wafer inspection process (S1003), electrical inspection (test of logic part) for a logic circuit on a semiconductor wafer as an object (S1003a) and electrical inspection (test of memory part) for a memory circuit as the object (S1003b) are performed, and fault parts obtained from respective inspection results are overlapped on a compound map 24 to be displayed, for example. When the compound map 24 is used, a region where a logic fault 22 and a memory fault 23 coexist and are distributed can be discriminated, and detailed analysis on the memory fault 23 is preferentially performed on the region. Thus, efficient detailed analysis can be performed, when especially, the cause of fault in the logic fault 22 and the memory fault 23 is common.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device in which a logic circuit and a memory circuit are mixed.

  For example, Patent Document 1 discloses an analysis method for visually displaying a position of a failed chip in a semiconductor wafer and a position of a failed block in each failed chip for a logic product. Further, Patent Document 2 discloses a diagnostic map created based on a tester's fail log, a light emission map created based on a light emission analysis in a standby state of a device, and in-line foreign matter inspection for logic products. A method is described in which a superimposed map is created by superimposing a foreign substance map created on the basis of the map, and analysis is performed according to the degree of overlap.

JP 2004-31676 A JP 2009-135151 A

  In recent years, in semiconductor products, the miniaturization of the manufacturing process and the reduction of the area of the semiconductor chip have progressed, and for example, the minimum processing dimension of the process has reached several tens of nm. In logic circuits, the diversification of logic functions is progressing along with the progress of such technology, and the number of failures tends to increase due to the complexity of the circuit configuration and device structure. In particular, when the minimum processing dimension is less than 100 nm and reaches 45 nm or the like, the failure increases more remarkably. Therefore, in order to improve the quality of semiconductor products and improve the yield, the importance of failure analysis is increasing. Usually, in failure analysis, first, failure locations are narrowed down from electrical analysis results using a tester or the like, and then the cause of failure is determined by performing physical analysis on the location. However, in a logic circuit, it is not easy to narrow down this failure location.

  As a method of narrowing down the failure location of a logic circuit, for example, a so-called scan chain, which is one of the DFT (Design For Testability) methods, is incorporated in the logic circuit in advance, and the inspection result using this is analyzed with failure diagnosis software. The method of performing is widely known. In this case, normally, cells (logic gates) and nets (wirings) connecting each cell are narrowed down to, for example, about ten locations as candidates for failure locations. However, since each net has a length of several μm to several hundred μm on the layout, when a physical analysis is performed on a plurality of nets or cells, it takes a lot of time and the analysis itself may be difficult. . Therefore, it is desirable to further narrow down the fault location by performing electrical analysis using a tester or the like in more detail, but in this case, a high level of expertise is required for the person in charge of the analysis.

On the other hand, semiconductor products such as so-called SOC (System On a Chip) in which a logic circuit and a memory circuit are mixed in one semiconductor chip in recent years due to downsizing of semiconductor products (smaller area of a semiconductor chip) and multi-functionality. Has increased. When a failure occurs in the memory circuit, failure analysis is required as in the case of the logic circuit described above. However, in the memory circuit, the failure location can be narrowed down to a narrower range easily and compared with the logic circuit. That is, in a memory circuit, a memory cell that fails due to electrical analysis by a tester can be acquired in the form of a fail bit map. For example, in the case of a 1-bit SRAM (Static Random Access Memory) cell, a range of about 1 μm ² It will be narrowed down to.

  In a semiconductor product such as an SOC, in order to improve quality and yield in a comprehensive manner, failure analysis for both the logic circuit and the memory circuit as described above is required. At this time, as described above, in the logic circuit, it is not easy to narrow down the fault location, and in order to narrow down to a narrower range under the circumstances, the analyst needs high specialized knowledge. . On the other hand, in the memory circuit, although the failure location can be narrowed down to some extent easily by the fail bitmap, there are many cases where further narrowing down and verification of the failure location are necessary in consideration of the circuit configuration and operation method peculiar to the memory, Advanced expertise different from logic circuits is required. Therefore, the failure analysis of the logic circuit and the failure analysis of the memory circuit are usually performed independently by an analyst who specializes in each. However, it has been found by the present inventors that in such an analysis method, the analysis efficiency when the semiconductor product such as SOC is viewed as a whole is lowered. Specifically, for example, there is a case where although there is a common cause of failure in the logic circuit and the memory circuit, duplicate analysis work occurs as a result, resulting in a waste of time cost.

  Accordingly, one of the objects of the present invention is to provide a semiconductor device manufacturing method capable of reducing inspection costs, analysis costs, and product costs. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The method for manufacturing a semiconductor device according to the present embodiment includes (a) sequentially forming a plurality of layers for forming a semiconductor chip including a logic circuit and a memory circuit on the main surface of a semiconductor wafer; and (b). And a step of inspecting the formed semiconductor wafer. In the step (b), electrical inspection is performed on each of the logic circuit and the memory circuit formed on the semiconductor wafer, and the candidate position of the logic failure location and the memory failure location obtained from the result are obtained. Is displayed in a superimposed manner on the first composite map with the semiconductor wafer as the map space.

  By using such a first composite map, for example, it is possible to prevent or suppress the occurrence of duplicate detailed analysis work at a logic failure location and a memory failure location. Furthermore, for locations where logic failure locations and memory failure locations coexist, the analysis work is performed by preferentially performing detailed analysis for memory failure locations where it is easy to narrow down the area of the failure location. Efficiency. In addition, since logic failure locations and memory failure locations coexist and are distributed, there is a high possibility that the failure location layer can be narrowed down to a layer that is commonly used by the logic circuit and memory circuit, which also improves the efficiency of analysis work. Can be achieved. As a result, the analysis cost can be reduced. Moreover, since the yield can be improved early by improving the analysis efficiency, the product cost can be reduced.

  The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. In the semiconductor device manufacturing process, it is possible to reduce inspection costs, analysis costs, and product costs.

FIG. 7 is a flowchart showing an example of processing contents in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. In the flow of FIG. 1, it is a conceptual diagram explaining an example of the detailed content relevant to the failure analysis process. It is explanatory drawing which shows an example of the more detailed process content at the time of producing | generating the composite map of FIG. It is a supplementary figure explaining an example of the processing content of the memory analysis support software in FIG. It is the schematic which shows an example of the composite map produced | generated by the process of FIG. It is explanatory drawing which shows an example of the approach method at the time of performing a detailed analysis based on the classification | category of the composite map in FIG. (A) is a display example in which a part of the logic / memory failure common area in FIG. 5 is enlarged, and (b) is a device structure of the intersection of the logic failure and the memory failure in (a). It is sectional drawing which shows an example. It is sectional drawing which shows the schematic structural example of the batting diffusion which is one of the structures peculiar to logic. 1 shows an example of a shared contact, which is one of memory-specific structures, (a) is a circuit diagram of an SRAM memory cell, (b) is a plan view showing a layout configuration example of (a), (c) is It is sectional drawing which shows the example of a part of device structure in (b). FIG. 6 is a schematic diagram illustrating another display example in which a part of the logic / memory failure common area in FIG. 5 is enlarged. FIG. 7 is a conceptual diagram illustrating an example of detailed contents related to a failure analysis process included in the flow of FIG. 1 in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. It is explanatory drawing which shows an example of the more detailed process content at the time of producing | generating the composite map of FIG. It is explanatory drawing which shows an example of the effect by producing | generating the composite map of FIG. FIG. 9 is a conceptual diagram illustrating an example of detailed contents related to a failure analysis process included in the flow of FIG. 1 in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. It is explanatory drawing which shows an example of the more detailed process content at the time of producing | generating the composite map of FIG. It is explanatory drawing which shows an example of the effect by producing | generating the composite map of FIG. In the manufacturing method of the semiconductor device by Embodiment 4 of this invention, it is a flowchart which shows an example of the processing content.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a flowchart showing an example of processing contents in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, first, after a semiconductor wafer is prepared (S1000), a film forming process is performed on the semiconductor wafer using various semiconductor manufacturing apparatuses (S1001). In the film forming step (S1001), a thin film formation process (S1001a), a photolithography process (S1001b), an etching process (S1001c), an impurity addition process (S1001d), a heat treatment (S1001e), and a CMP (Chemical Mechanical Polishing) process (S1001f). The cleaning process (S1001g) is appropriately combined and repeated. Thus, a thin film having a predetermined shape is deposited over a plurality of layers, and a predetermined circuit is formed on the semiconductor wafer.

  In the thin film formation process (S1001a), a predetermined film is formed on the main surface of the semiconductor wafer using a CVD (Chemical Vapor Deposition) apparatus, a sputtering apparatus, or the like. In the photolithography process (S1001b), a resist is applied on the formed thin film, and a circuit pattern is transferred onto the resist by exposure and development using a mask (reticle). In the etching process (S1001c), a thin film is processed through a resist by an etching apparatus, and a predetermined circuit pattern is formed on the thin film. In the impurity addition process (S1001d), ion implantation is performed on the semiconductor wafer or thin film. In the heat treatment (S1001e), formation of an oxide film and annealing (reflow, recovery of crystallinity, etc.) are performed. In the CMP process (S1001f), the main surface of the semiconductor wafer is chemically and mechanically polished and planarized by a CMP apparatus. In the cleaning process (S1001g), various contaminations (contamination, particles, etc.) generated by the various processes described above are cleaned by a wet system using chemicals or a dry system using gas.

  In addition, an in-line inspection process is appropriately inserted between the various processes (S1002). In the in-line inspection process (S1002), foreign matter and defects on the main surface of the semiconductor wafer are detected using a foreign matter / defect inspection apparatus. The foreign matter / defect inspection apparatus is, for example, a device using a laser scattering method, a device that observes using a UV (ultraviolet) light source or a DUV (far ultraviolet) light source, or a SEM (Scanning Electron Microscope). What to observe is known. By using such a foreign substance / defect inspection apparatus, for example, a foreign substance or defect having a minimum number of commas of about several μm can be detected, and the detection position is output as a map on a semiconductor wafer through processing of a computer system. Is also possible.

  When the processing of the semiconductor wafer is completed through the film forming process (S1001) and the in-line inspection process (S1002), the quality of the product is determined using a probe card, a probe inspection apparatus, or the like for the semiconductor wafer. An electrical inspection is performed (S1003). For example, when each semiconductor chip formed on a semiconductor wafer is an SOC chip having a logic circuit and a memory circuit, as an electrical inspection, a logic unit test (S1003a), a memory unit test (S1003b), and an IDDQ test (S1003c) Etc. are performed.

  In the logic unit test (S1003a), for example, a scan test (S1003a1), LBIST (S1003a2), and the like are performed. In the scan test (S1003a1), a logical operation portion between flip-flops is inspected using a scan chain in which flip-flops in the logic circuit are serially connected. The probe inspection device sets the scan chain to the scan mode and sequentially sets the test input data (test vector), then shifts to the normal operation mode, applies the clock signal, and then shifts to the scan mode again. Test output data is taken out sequentially. Then, the test output data is collated with the expected value, and when the test output data does not match the expected value (that is, fails), the information is stored as a fail log. In the scan test (S1003a1), the scan chain (flip flop) itself is also inspected.

  In the LBIST (S1003a2), unlike the above-described scan test (S1003a1), setting of test input data for the scan chain and processing for test output data from the scan chain are incorporated into the logic BIST (Built In Self Test) circuit. The BIST circuit for logic includes, for example, a pseudo random number data generator such as LFSR (Linear Feedback Shift Register) and an output data compressor such as MISR (Multiple Input Signature Register). The pseudo random number data generator sequentially inputs the generated pseudo random number data to the scan chain, and the output data compressor sequentially compresses the data output from the scan chain. After activating the BIST circuit, the probe inspection device determines pass / fail (pass / fail) by comparing the data compressed by the output data compressor with an expected value.

  In the memory unit test (S1003b), for example, MBIST (S1003b1) and fail bit map test (S1003b2) are performed. In MBIST (S1003b1), the inspection is performed by a BIST circuit for memory incorporated around the memory circuit. The BIST circuit for memory includes, for example, a test pattern generator, an address generator, a control signal generator, a result comparator, and the like. The BIST circuit performs writing by applying an address signal, a write control signal, and a test input pattern to the memory circuit, and performs reading by applying an address signal and a read control signal to the memory circuit. The pattern is judged good / bad by the result comparator. There are various test pattern generators such as those that generate a simple pattern such as a checker pattern and those that generate a complex pattern close to a random number. After starting the BIST circuit, the probe inspection apparatus acquires the pass / fail judgment result obtained by the result comparator.

  In the fail bit map test (S1003b2), for example, a probe inspection apparatus inspects a memory circuit by applying an address signal, a control signal, and a test input pattern to the memory circuit via an internal pad on a semiconductor chip. . In this inspection, the probe inspection apparatus stores the failed address as a failure bit.

  In the IDDQ test (S1003c), for example, the probe inspection apparatus sets the test input data (test vector) for the logic circuit via the scan chain, and then observes the static power supply current of the logic circuit after a certain time. Further, the probe inspection apparatus observes the static power supply current of the memory circuit after a predetermined time after setting the test input pattern for the memory circuit.

  As a result of the wafer inspection (S1003), when an abnormal value different from the expected value is observed in the current value, voltage value, logical value, etc., the cause of the abnormality is investigated, and the film forming process (S1001) or in-line inspection process (S1002). A failure analysis step for reflecting the result is performed (S1004). For example, when it is found by the failure analysis process that there is an abnormality in a specific process in the film forming process (S1001), the processing conditions are reviewed, and in some cases, the device structure or circuit configuration is reviewed. Is called. In addition, when it is determined that the object is due to foreign matter or the like, the target processing apparatus is cleaned, or the location in the film forming process where the inline inspection process (S1002) is inserted and the inspection conditions are reviewed. Is done. As a result, the yield and quality of the semiconductor wafer can be improved.

  Typical examples of failure analysis include light emission analysis using a light emission analysis device and OBIRCH analysis using an OBIRCH (Optical Beam Induced Resistance Change) analysis device (S1004a). The light emission analysis device is a device that detects extremely weak light generated due to current leakage and captures its position and intensity as a two-dimensional image. By using this device, for example, light emission due to hot carrier generation under a high electric field that occurs when a transistor channel leak, PN junction leak, etc., or carrier re-generation that occurs when a forward current flows through the PN junction are used. Light emission or the like due to binding can be detected. The OBIRCH analysis device is a device that detects a failure location by utilizing the fact that the change in electrical resistance due to heat generation during laser irradiation differs at the failure location. By using the device, for example, a wiring or a via having a high resistance portion can be detected. The failure location obtained by such an analysis apparatus can be displayed as a map on a semiconductor wafer through processing by a computer system.

  Such a failure analysis step (S1004) is fundamentally performed by a physical analysis such as an operation for narrowing down a place where a physical analysis is to be performed and a shape observation by an electron microscope or the like or an analysis by a composition analyzer for the place. It consists of work to investigate the cause. In order to improve the yield and the like at an early stage, it is necessary to narrow down the location where the physical analysis should be performed as early as possible and to a small range. However, a large amount of fail information from the wafer inspection process (S1003) was simply obtained. Alone, it is not clear how to narrow down efficiently.

  In this case, as described above, it is conceivable that an analyst who specializes in logic circuits narrows down the logic circuit, and at the same time, an analyst who specializes in memory circuits narrows down the memory circuit. However, especially in the logic circuit, failure points for each semiconductor chip can be obtained only in a wide range such as multiple nets and multiple cells. It takes a lot of time together with the knowledge, and in some cases, it may not be able to be narrowed down sufficiently. In addition, after narrowing down the logic circuit and performing physical analysis over time, it was found that it was the same as the cause of the failure of the memory circuit, resulting in duplicate work in the analysis of the logic circuit and the analysis of the memory circuit. There is also a risk. Therefore, it is beneficial to use a failure analysis process described below.

  FIG. 2 is a conceptual diagram for explaining an example of detailed contents related to the failure analysis step (S1004) in the flow of FIG. The failure analysis step (S1004) of FIG. 2 uses the logic failure result 20 and the memory failure result 21 to combine the failure location (logic failure) 22 of the logic circuit and the failure location (memory failure) 23 of the memory circuit 24. As a process of superimposing and displaying on the map of the entire semiconductor wafer. The logic failure result 20 includes net and cell information representing a failure location, which is generated based on the result of the logic unit test (S1003a) described above (fail log, etc.). The memory failure result 21 includes fail bit information obtained from the memory unit test (S1003b) described above.

  FIG. 3 is an explanatory diagram showing an example of more detailed processing contents when the composite map 24 of FIG. 2 is generated. First, in the wafer inspection step (S1003), as described above, the logic circuit of the semiconductor wafer is inspected using the logic tester 30a, and the fail information (for example, test input data and test output data) at that time is used as the fail log 30b. Saved. Further, as described above, the memory circuit of the semiconductor wafer is inspected using the memory tester (or the logic tester or the logic / memory tester) 32a, and the fail bit information (fail logic address information) at that time is the memory failure result 21a. Saved as Then, a failure analysis step (S1004) is performed based on the fail log 30b and the memory failure result 21a.

  In the failure analysis step (S1004) regarding the logic circuit, first, the failure diagnosis software 31a reads the above-described fail log 30b, narrows down the failure location (net, cell) in the logic circuit, and the failure location is identified as the logic failure result 20a. Save as. In the failure diagnosis software, for example, a failure location is narrowed down by a result cause method, a cause result method, and a combination thereof. In the cause-of-results method, the failure location is narrowed down to, for example, a circuit module or a relatively large number of nets and / or cells by going up the failure propagation path from the fail log (test output data). . In the cause-and-effect method, further narrow-down is performed using the failure dictionary method or the like for the range narrowed down to a certain extent by the above-described cause-and-cause method, and as a result, for example, about 10 points of nets and / or cells It is narrowed down to. The failure dictionary is a summary of how the input / output data appears when a failure occurs in the location by performing a simulation with the failure (cause) embedded in a predetermined location in advance. By collating with the failure dictionary, it becomes possible to narrow down the failure location.

  Some of the fault diagnosis software 31a corresponds to the IDDQ test of FIG. In this case, for example, wirings (nets) that are adjacent to each other on the layout are defined, and when test input data (fail vector) that has failed in the IDDQ test is set, they have different potentials. By detecting the adjacent wiring, the failure location is narrowed down. When the fault diagnosis sost 31a as described above is used, although there is no particular limitation, the faults together with failure modes such as a wiring open failure, a wiring short-circuit failure, a 0/1 stuck-at failure, an in-cell failure, a delay failure, a Via open failure, etc. A location (net cell) is obtained. However, as described above, it is usually difficult to narrow down to a single net or cell, and in many cases about ten candidates for failure locations are obtained.

  When the failure diagnosis software 31a stores the net and cell of the failure location as the logic failure result 20a, the logic analysis support software 31b then refers to the design data 35 including the layout information and the net or cell that becomes the failure location. Physical coordinates (layout coordinates) are extracted and stored as a logic failure result 20b. Such logic analysis support software 31b can be easily realized by using, for example, a general layout design tool.

  On the other hand, in the failure analysis step (S1004) relating to the memory circuit, the memory analysis support software 33 performs processing for converting the logical address information stored in the memory failure result 21a into physical coordinates. The memory analysis support software 33 includes an address conversion function 33a that converts a logical address into a physical address, and a coordinate conversion function 33b that converts a physical address into physical coordinates (layout coordinates). FIG. 4 is a supplementary diagram for explaining an example of processing contents of the memory analysis support software in FIG.

  In a memory circuit on an actual layout, memory cells are not always arranged in the order of external addresses. This external address is called a logical address, and an address based on the actual memory cell arrangement is called a physical address. In the example of FIG. 4, as logical addresses, address spaces # 0 to # 31 are provided corresponding to 32 memory cells for each of I / O (input / output terminals) 0 to 7. Since the test is performed using this logical address when the test is performed, the logical address information is also obtained as fail address information, for example, information such as “I / O0 address # 0 fails” is obtained.

  On the other hand, there is no concept of I / O in the physical address, and an address space such as an X address of # 0 to # 63 and a Y address of # 0 to # 3 is defined based on the actual array of memory cells in the memory circuit. Has been. For example, the logical address “I / O0 address # 0” corresponds to the physical address “(X, Y) = (# 0, # 0)”. Normally, the logical address and the physical address can be converted using a conversion formula or the like, and the address conversion function 33a in FIG. 3 performs this processing.

  Thus, when the physical address of the fail bit is determined, the relationship between the physical address and the physical coordinates in the semiconductor chip is recognized with reference to the design data 35 including the layout information. In the example of FIG. 4, the memory circuit (memory mat) is arranged in the order of the physical addresses described above with the coordinates of X = 154.43 μm and Y = 105.01 μm as the origin, with the lower left of the semiconductor chip including the memory circuit as the origin. ing. Since the physical size and the like of each memory cell is predetermined, given an arbitrary physical address, its physical coordinates can be calculated. Such processing is performed by the coordinate conversion function 33b of FIG. The physical coordinates of the fail bit obtained as a result are stored in the memory failure result 21c.

  When the physical coordinates of the cell or net having the logic failure and the physical coordinates of the memory cell having the memory failure are determined by the above processing, the physical coordinates of the entire semiconductor wafer are obtained through image processing by a computer system. The positional relationship is displayed on a display or the like, so that the above-described composite map 24 can be generated. Hereinafter, an example of the effect obtained by generating such a composite map 24 will be described.

  FIG. 5 is a schematic diagram illustrating an example of a composite map generated by the process of FIG. As shown in FIG. 5, the composite map 24 displays the positions of the logic failure 22 and the memory failure 23 of each semiconductor chip 51 on the semiconductor wafer 50. The entire semiconductor wafer can be classified into, for example, a logic / memory fault common area 52, a logic fault only frequent area 53, and a memory fault only frequent area 54 based on the deviation of these faults in the wafer plane. . These classifications may be performed, for example, by automatically recognizing how many logic faults 22 and memory faults 23 exist for each predetermined unit area.

  FIG. 6 is an explanatory diagram showing an example of an approach method when performing detailed analysis based on the classification of the composite map 24 in FIG. As shown in FIG. 6, for the logic / memory failure common area 52, the memory analysis is performed using the logic / memory common layer as a promising candidate for the failure location. For the logic failure only frequent region 53, logic analysis is performed focusing on the logic layer, and particularly focusing on the structure unique to the logic. Further, for the memory failure only frequent region 54, the memory analysis is performed focusing on the memory layer and particularly the structure peculiar to the memory. Note that “logic failure only” is used here, but this does not necessarily mean that there is no memory failure, and there are cases where the rate of logic failure is extremely high compared to memory failure (for example, 90% or more). Including. The same applies to the case of “memory failure only”.

First, the case where the classification in FIG. 6 is the logic / memory failure common area 52 will be described. FIG. 7A shows a display example in which a part of the logic / memory failure common area 52 in FIG. 5 is enlarged, and FIG. 7B shows the logic failure and memory in FIG. It is sectional drawing which shows the example of a device structure of the intersection part of a failure. In FIG. 7A, a memory failure (fail bit) 23 exists in a part of memory cells in the memory mat (memory circuit) 70, and further, a logic failure (net) has an overlapping portion with the memory failure 23. Fault) 22 exists. As described in FIG. 3, the network failure obtained by the failure diagnosis software 31a usually has a plurality of locations as candidates, and the failure location is narrowed down to such a degree that further physical analysis can be performed. Is not easy. Further, even if the number is narrowed down to one, a single net has a length of, for example, several μm to several hundred μm, so that much time is required for its physical analysis. Therefore, by making the intersection 71 between the net failure (logic failure) 22 and the memory failure 23 as a promising candidate for the failure location, not only can the area on the plane be narrowed down to the unit of the memory cell (for example, 1 μm ² ). It is also possible to narrow down the layers on the cross section.

  That is, as shown in FIG. 7B, in the SOC or the like, various transistors used in the logic circuit and various transistors used in the memory circuit are formed on the diffusion layer DF (silicon substrate), and the upper layer is contacted. The layer CNT and a plurality (here, five layers) of metal wiring layers M1 to M5 are sequentially formed. Various transistors in the logic circuit and the memory circuit are appropriately connected through the metal wiring layers M1 to M5. In the example of FIG. 7B, for example, wiring in the logic circuit is performed using the metal wiring layers M1 to M5, and wiring in the memory circuit is performed using the metal wiring layers M1 to M3. As a result, the diffusion layer DF, the contact layer CNT, and the metal wiring layers M1 to M3 become the logic / memory common layer 74, and the metal wiring layers M4 and M5 become the logic dedicated layer 73. If the logic function is diversified, the wiring structure becomes more complicated, and the number of logic dedicated layers 73 is further increased. As a result, the number of failure points is also increased. In addition, it can be generally realized with fewer metal wiring layers than the logic circuit, and the number of layers is fixedly determined.

  In such a cross-sectional structure, when the logic fault 22 and the memory fault 23 occur in a predetermined area of the semiconductor wafer as in the logic / memory fault common area 52 of FIG. It can be said that there is a high possibility that the cause of failure exists at 74. Among them, in particular, when the logic fault 22 and the memory fault 23 have the intersection 71 as shown in FIG. 7A, there is a high possibility that the cause of the fault exists at the intersection 71. In the example of FIG. 7B, for example, there is a common failure occurrence location 72 such as a short circuit between the metal wiring layer M3 related to the memory failure 23 and the metal wiring layer M4 corresponding to the logic failure (net failure). As a result, an intersection 71 exists. In this case, the area on the plane to be subjected to physical analysis can be narrowed down to a very small range. However, regardless of the presence or absence of the intersection 71, at the stage where the logic failure 22 and the memory failure 23 occur in the predetermined area, the layer where the failure cause exists can be narrowed down to the logic / memory common layer 74. The subsequent analysis can be facilitated.

  When the cause of failure is narrowed down to the logic / memory common layer 74, it is necessary to narrow down the area on the plane. For example, when the intersection 71 does not exist in the logic fault 22 and the memory fault 23, if the fault location is narrowed down based on the logic fault 22, it becomes difficult to narrow down as described above, and much time is required. Therefore, the memory failure 23 is analyzed with priority. That is, in the logic / memory failure common area 52, for example, a foreign matter is generated when the metal wiring layer M1 which is one of the logic / memory common layers 74 is formed. Are very likely to be common. Therefore, further detailed analysis may be performed paying attention to the memory failure 23 for which it is easy to narrow down the failure location and to estimate the failure mechanism. Specifically, for example, the reproducibility of failure is confirmed by electrical analysis using a tester, etc., the failure location is further narrowed down, the failure mechanism is estimated, etc. The actual cause of failure is observed using physical analysis.

  As a result, logic circuit analysis work can be reduced or reduced, and duplication work that can occur when there is a common cause of failure in the memory circuit and the logic circuit can be reduced. In other words, the logic circuit analysis work is reduced or reduced using the analysis result of the memory circuit. As a result, the time cost can be reduced and the yield of the semiconductor wafer can be improved at an early stage.

  Next, the case where the classification in FIG. 6 is the logic failure only frequent region 53 will be described. In this case, it is necessary to perform an analysis on the logic circuit. However, since it has been found that only logic faults occur frequently by classification based on the composite map 24, the logic shown in FIG. The dedicated layer 73 can be a strong candidate for the cause of failure. Furthermore, if the analysis is performed in the suspicion of a logic-specific structure or a static failure of the logic circuit, the analysis can be completed at an earlier stage than when a net or cell of a failure location is simply given.

  Examples of the structure peculiar to logic include batting diffusion. FIG. 8 is a cross-sectional view illustrating a schematic configuration example of batting diffusion which is one of logic-specific structures. The batting diffusion means a structure in which the n-type active region and the p-type active region are in contact in a logic circuit in which the gate electrode and the source / drain surface are silicided by salicide. In the example of FIG. 8, p-type active regions 81 a and 81 b that are sources and drains of a pMOS transistor are formed in an n-type well 83, and an n-type active region 82 is formed so as to be in contact with the p-type active region 81 b. Yes. The n-type active region 82 is, for example, a power feeding tap toward the n-type well 83. A structure in which the p-type active region 81b and the n-type active region 82 are in contact is called a batting diffusion 84, and the area of the logic circuit can be reduced by this structure.

  Next, the case where the classification in FIG. In this case, it is necessary to perform an analysis on the memory circuit. However, since it is found that only memory failures occur frequently by classification based on the composite map 24, the memory layer (FIG. 7B) In the example, for the diffusion layer DF, the contact layer CNT, and the metal wiring layers M1 to M3), the analysis may be performed by suspecting a memory-specific structure, a static failure of the memory circuit, or the like. As a result, the analysis can be completed at an earlier stage than when a failure address is simply given.

  As a structure peculiar to a memory, a shared contact etc. are mentioned, for example. FIG. 9 shows an example of a shared contact which is one of the structures peculiar to the memory, where (a) is a circuit diagram of the SRAM memory cell, and (b) is a plan view showing a layout configuration example of (a). (C) is sectional drawing which shows the example of a part of device structure in (b). As shown in FIG. 9A, the SRAM memory cell includes, for example, four nMOS transistors MN1 to MN4 and two pMOS transistors MP1 and MP2. The gates of MN1 and MP1 are connected to the drains of MN2 and MP2, and the gates of MN2 and MP2 are connected to the drains of MN1 and MP1. The sources of MN1 and MN2 are connected to the ground power supply voltage GND, and the sources of MP1 and MP2 are connected to the power supply voltage VDD. The gate of MN3 is connected to the word line WL, one of the source and drain is connected to the drains of MP1 and MN1, and the other is connected to the bit line BL. The gate of MN4 is connected to WL and one of the source and drain is connected. Are connected to the drains of MP2 and MN2, and the other is connected to the inverted bit line BLB.

For example, as shown in FIG. 9B, such an SRAM cell is realized by a pMOS region and nMOS regions arranged on both sides thereof, and MN1, MN3 are provided in one of the nMOS regions and MN2, MN2, in the other. MN4 is formed, and MP1 and MP2 are formed in the pMOS region. Here, the gate electrode (for example, polysilicon) of MN1 and the drain diffusion layer of MP2, and the gate electrode of MN2 and the drain diffusion layer of MP1 can be connected in common. Therefore, in order to reduce the area of the SRAM memory cell, as shown in FIGS. 9B and 9C, for example, in the pMOS region, the contacts DC and MN2 connected to the drain diffusion layer (P ⁺ ) of MP1. A contact GC connected to the gate electrode GT is formed by a common contact (SHC). Similarly, a contact DC connected to the drain diffusion layer (P ⁺ ) of MP2 and a contact GC connected to the gate electrode GT of MN1 are formed by a common contact (SHC). This SHC is called a shared contact.

  By the way, the example of reducing or reducing the logic circuit analysis work using the memory circuit analysis result has been described so far. However, by using the composite map 24, the memory circuit analysis work is reversed. It is also possible to reduce by using the analysis result of the logic circuit. FIG. 10 is a schematic diagram showing another display example in which a part of the logic / memory failure common area 52 in FIG. 5 is enlarged. In FIG. 10, a line-shaped memory failure 23 exists in the memory mat (memory circuit) 70 in the semiconductor chip 51, and further, a logic failure 22 (here, a cell failure of the scan flip-flop SFF) occurs in the logic circuit. This logic fault 22 exists in close proximity to the extension of the memory fault 23 line.

  The logic fault 22 exists on the scan chain between the scan-in terminal SIN and the scan-out terminal SOUT and is detected as one of a plurality of fault location candidates, or in some cases, one scan flip-flop SFF. To be detected. In such a case, the cause of the memory failure 23 does not exist on the line or the decoder 101 that drives the memory failure 23, and the logic failure 22 in the logic circuit connected between the external pin PN and the decoder 101 exists. There is a good chance that it exists. As a result, if the composite map 24 is not used, there may occur a situation in which the memory analysis work is wasted because the cause of the failure cannot be determined as a result of the memory analysis.

  Therefore, by using the composite map 24, it is possible to sufficiently estimate the possibility that the cause of the fault exists in the logic circuit, and as a result, it is possible to save the waste of the memory analysis work. On the contrary, from the viewpoint of the logic fault 22, for example, when there are a plurality of logic faults 22 on the extended line of the memory fault 23, an intersection point on the circuit is selected from the line. It is also possible to narrow down to the places that you have. Therefore, by using the composite map 24, the efficiency of the analysis can be improved in both the logic analysis and the memory analysis. Such a fault location can be automatically extracted by recognizing a location where the distance between each logic fault 22 and each memory fault 23 is shorter than a certain value, for example. is there.

  As described above, by using the manufacturing method of the semiconductor device according to the first embodiment, it is typically possible to realize a reduction in inspection cost or a reduction in product cost due to an early yield improvement.

(Embodiment 2)
In the second embodiment, a method for manufacturing a semiconductor device in which an in-line inspection result is further reflected on the composite map described in the first embodiment will be described. FIG. 11 is a conceptual diagram illustrating an example of detailed contents related to the failure analysis step (S1004) included in the flow of FIG. 1 in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  The failure analysis step (S1004) of FIG. 11 uses the logic failure result 20 and the memory failure result 21 as in the case of FIG. 2 to use the logic circuit failure location (logic failure) 22 and the memory circuit failure location (memory). Failure) 23 as a composite map and displayed on the map of the entire semiconductor wafer. In addition to this, in the failure analysis step (S1004) of FIG. 11, the detection position of the foreign matter / defect 111 obtained in the inline inspection step (S1002) of FIG. 1 is overlaid on the map of the entire semiconductor wafer as a composite map 24b. Display processing. The detection location (coordinates) of the foreign object / defect 111 is included in the foreign object / defect inspection result 110 output in the inline inspection process (S1002). Although not particularly limited, the size of the foreign matter / defect 111 displayed on the composite map 24b is, for example, about a few μm at the minimum.

  FIG. 12 is an explanatory diagram showing an example of more detailed processing contents when the composite map 24b of FIG. 11 is generated. The processing content of FIG. 12 is the addition of the processing content of the inline inspection process (S1002) to the processing content of FIG. 3 described above, and accordingly, the inline inspection result is reflected instead of the composite map 24 of FIG. The composite map 24b is generated. Since the other processing contents are the same as those in the case of FIG. 3, detailed description thereof is omitted. In the in-line inspection step (S1002), as described in FIG. 1, the in-line inspection apparatus (foreign matter / defect inspection device) 120a inspects for the presence of foreign matter / defects during a predetermined process in the film forming step (S1001). If a foreign object / defect is detected, the coordinates are stored as foreign object / defect data 120b.

  By generating such a composite map 24b, the following effects can be obtained in addition to the various effects described in the first embodiment. FIG. 13 is an explanatory diagram showing an example of the effect obtained by generating the composite map 24b of FIG. As shown in FIG. 13, by generating the composite map 24b reflecting the foreign object / defect data 120b, detailed classification (S1300) based on the composite map 24b becomes possible. In the detailed classification (S1300), it is determined whether the foreign matter / defect detection location matches the logic failure 22 or the memory failure 23 (S1301) or does not match (S1304). This determination processing can be automatically performed by a computer system.

  If they match (S1301), there is a high possibility that the foreign object / defect 111 causes the logic failure 22 or the memory failure 23 to cause a decrease in yield. In particular, when the foreign matter / defect 111, the logic failure 22 and the memory failure 23 all overlap, there is a high possibility that the foreign matter / defect 111 has a very high influence on the yield (S1302). Therefore, the process process in the film forming step (S1001) where the foreign matter / defect has occurred is investigated with the highest priority, and measures can be taken to improve the yield quickly and effectively (S1303). At this time, since the position of the foreign object / defect 111 and the process processing in which the foreign object / defect 111 has occurred are known in advance, logic analysis or memory analysis for narrowing down the failure location is unnecessary or can be performed in a short period of time. As a result, inspection costs and analysis costs can be reduced.

  On the other hand, if there is a mismatch (S1304), there will be a logic fault 22 and a memory fault 23 that could not be detected in the inline inspection process (S1002) (S1304). In this case, for example, a detailed analysis of the logic failure 22 and the memory failure 23 is performed, and an inline inspection process is reviewed (an inline inspection is inserted between process processes related to the cause of the failure) based on the analysis result (S1305). . As a result, the yield can be further improved. Alternatively, for example, adjustment is performed from the viewpoint of a cause of failure that is not caused by a process (S1305). As a result, the analysis time can be shortened to some extent (inspection cost can be reduced).

  As described above, by using the method of manufacturing the semiconductor device of the second embodiment, typically, as in the case of the first embodiment, a product resulting from a reduction in inspection cost or an early improvement in yield. Cost reduction can be realized, and in addition, by reflecting the results of in-line inspection, it is possible to further reduce inspection costs and reduce product costs by improving yields at an early stage.

(Embodiment 3)
In the third embodiment, a method for manufacturing a semiconductor device in which the emission analysis result is further reflected on the composite map described in the second embodiment will be described. FIG. 14 is a conceptual diagram illustrating an example of detailed contents related to the failure analysis step (S1004) included in the flow of FIG. 1 in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

  The failure analysis step (S1004) in FIG. 14 uses the logic failure result 20, the memory failure result 21, and the foreign object / defect inspection result 110 to obtain the logic failure 22, the memory failure 23, and the This includes a process of displaying the defect 111 as a composite map in an overlapping manner on the map of the entire semiconductor wafer. In addition to this, the failure analysis step (S1004) in FIG. 14 is a map of the entire semiconductor wafer with the light emission location 141 obtained in the light emission analysis (S1004a) in the failure analysis step (S1004) in FIG. It includes the process of overlaying and displaying. The light emission location (coordinates) 141 is included in the light emission data 140 created based on information from the light emission analysis device or the like.

  FIG. 15 is an explanatory diagram showing an example of more detailed processing contents when the composite map 24c of FIG. 14 is generated. The processing content of FIG. 15 is further added to the processing content of FIG. 12 described above in addition to the processing content accompanying the light emission analysis in the failure analysis step (S1004), and accordingly, instead of the composite map 24b of FIG. The composite map 24c reflecting the light emission analysis result is generated. Since the other processing contents are the same as those in the case of FIG. 12, detailed description thereof is omitted. In the failure analysis step (S1004), as described with reference to FIG. 1, the light emission analysis device 150a acquires the light emission image 150b for the semiconductor wafer, and the light emission analysis support software 151 uses the coordinate extraction function 151a to perform the light emission described above. The light emission coordinates in the image 150b are extracted with reference to the design data 35 including layout information. The light emission analysis support software 151 stores the extracted coordinates as light emission data 140.

  By generating such a composite map 24c, the following effects can be obtained in addition to the various effects described in the second embodiment. FIG. 16 is an explanatory diagram showing an example of the effect obtained by generating the composite map 24c of FIG. As shown in FIG. 13, when there is a logic failure 22 or a memory failure 23 that could not be detected by the in-line inspection (S1304), as shown in FIG. 16, by using the composite map 24c, the logic failure 22 or Further detailed classification (S1600) can be performed for the memory failure 23. In the detailed classification (S1600), it is determined whether the light emission location 141 matches the logic failure 22 or the memory failure 23 (S1601) or does not match (S1604). This determination processing can be automatically performed by a computer system.

  If they match (S1601), there is a high possibility that the abnormality corresponding to the light emitting location 141 causes the logic failure 22 or the memory failure 23 to cause a decrease in yield. In particular, when all of the light emission location 141, the logic failure 22 and the memory failure 23 overlap, there is a high possibility that the abnormality corresponding to the light emission location 141 has a very high influence on the yield (S1602). Therefore, the yield can be improved early and effectively by investigating the light emitting spot 141 with the highest priority and taking countermeasures (S1603). At this time, for example, the light emission spot 141 by the light emission analysis device is mainly generated due to the abnormality of the transistor. It is fully known beforehand. Therefore, the logic analysis and the memory analysis for narrowing down the failure location are unnecessary or can be performed in a short period of time, and accordingly, the analysis cost and the inspection cost can be reduced. On the other hand, if there is a mismatch (S1604), adjustment is performed from the viewpoint of a wiring system failure or some static failure (S1605). As a result, the analysis time can be shortened to some extent (reduction in analysis cost and inspection cost).

  As described above, by using the method of manufacturing the semiconductor device of the third embodiment, typically, as in the case of the second embodiment, a product resulting from a reduction in inspection cost or an early improvement in yield. Cost reduction can be realized, and in addition, by reflecting the light emission analysis result, the product cost can be reduced by further reducing the inspection cost and improving the yield at an early stage.

(Embodiment 4)
In the first to third embodiments, the composite map is created for the semiconductor wafer. Of course, the composite map can also be created for the semiconductor chip. FIG. 17 is a flowchart showing an example of processing contents in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. The flow shown in FIG. 17 is obtained by further adding an assembly step (S1005), an assembly inspection step (S1006), and a failure analysis step (S1007) to the flow described in FIG. Since the other steps are the same as those in FIG. 1, detailed description thereof is omitted.

  In the assembly process (S1005), the semiconductor chip that has become a non-defective product in the wafer inspection process (S1003) is assembled (packaged). In the assembly inspection step (S1006), inspection is performed on each semiconductor chip (assembly). The inspection contents include a logic unit test (S1006a) and a memory unit test (S1006b) using a tester, an IDDQ test (S1006c), and the like, as in the case of the wafer inspection (S1003) described above. However, the detailed inspection conditions (for example, timing conditions, types of input data, etc.) may overlap or be different from those in the wafer inspection (S1003).

  In the failure analysis step (S1007), as in the case of the failure analysis step (S1004) for the wafer inspection (S1003) described above, the composite maps 24, 24b, and 24c as described in the first to third embodiments are generated. Based on this, various analyzes as described in the first to third embodiments are efficiently performed. However, the composite map in this case does not use the semiconductor wafer as the map space but uses the semiconductor chip as the map space. When the cause of the failure is determined by this analysis, measures are taken for the film formation step (S1001) and the in-line inspection step (S1002) as in the case of the failure analysis step (S1004). As a result, the yield can be improved at an early stage. Further, when the cause of the failure is determined, measures such as addition of inspection items are taken for the wafer inspection step (S1003) in some cases. Thereby, it is not necessary to assemble a defective product, and the cost can be reduced.

  As described above, by using the manufacturing method of the semiconductor device of the fourth embodiment, typically, as in the case of the first to third embodiments, the inspection cost is reduced or the early yield is improved. The product cost can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, in the third embodiment, the emission analysis result is superimposed on the composite map 24b of the second embodiment. Of course, the emission analysis result can be superimposed on the composite map 24 of the first embodiment. It is.

  The method of manufacturing a semiconductor device according to the present embodiment is particularly useful when applied to a manufacturing process of a semiconductor product in which a logic circuit and a memory circuit are mixed.

20, 20a, 20b Logic failure result 21, 21a, 21b, 21c Memory failure result 22 Logic failure 23 Memory failure 24, 24b, 24c Composite map 30a Logic tester 30b Fail log 31a Failure diagnosis sost 31b Logic analysis support software 32a Memory tester or Logic tester 33 Memory analysis support software 33a Address conversion function 33b, 151a Coordinate conversion function 35 Design data 50 Semiconductor wafer 51 Semiconductor chip 52 Logic / memory fault common area 53 Logic fault only frequent area 54 Memory fault only frequent area 70 Memory mat 71 Logic Intersection of failure and memory failure 72 Common failure occurrence location 73 Logic dedicated layer 74 Logic / memory common layer DF, P ⁺ diffusion layer CNT contact layer M1 to M5 Metal wiring layer 81a, 81b P-type active region 82 n-type active region 83, NWEL n-type well 84 Batting diffusion WL Word line BL Bit line BLB Inverted bit line MN nMOS transistor MP pMOS transistor VDD Power supply voltage GND Ground power supply voltage GT Gate electrode SHC shared contact DC, GC contact SFF scan flip-flop PN external pin SIN scan-in terminal SOUT scan-out terminal 100 memory cell 101 decoder 110 foreign matter / defect inspection result 111 foreign matter / defect 120a in-line inspection device 120b foreign matter / defect data 140 light emission data 141 Light emission point 151 Light emission analysis support software

Claims (10)

(A) sequentially forming a plurality of layers for forming a semiconductor chip including a logic circuit and a memory circuit on a main surface of a semiconductor wafer;
(B) a step of inspecting the semiconductor wafer formed by the step (a),
The step (b)
(B1) performing an electrical inspection on the logic circuit formed on the semiconductor wafer;
(B2) selecting a candidate for a logic fault location in the logic circuit by inputting the result of the electrical inspection in the step (b1) to fault diagnosis software;
(B3) referring to layout information of the semiconductor wafer and the semiconductor chip, and deriving layout coordinates on the semiconductor wafer where the candidates for the logic fault locations are respectively located;
(B4) conducting an electrical test on the memory circuit formed on the semiconductor wafer and storing the resulting faulty memory address;
(B5) referring to the layout information, deriving layout coordinates on the semiconductor wafer where the memory cell corresponding to the failed memory address is located;
(B6) Using the layout coordinates obtained in the steps (b3) and (b5), using the semiconductor wafer as a map space, the candidate position of the logic fault location and the memory cell corresponding to the fault memory address Generating a first composite map in which the positions are displayed in an overlapping manner, and a method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the plurality of layers include a common layer used in common by the logic circuit and the memory circuit, and a dedicated layer used only by the logic circuit. The method of manufacturing a semiconductor device according to claim 2.
If the logic failure location candidates and the memory cells corresponding to the failed memory address coexist in the first area that is a part of the first composite map, the failure occurs in the first area. A method of manufacturing a semiconductor device, wherein a detailed analysis based on a memory cell corresponding to a memory address is preferentially performed. In the manufacturing method of the semiconductor device according to claim 3,
In the first area, when there is a location having an intersection between the candidate for the logic failure location and the memory cell corresponding to the failure memory address, the detailed analysis for the location having the intersection is preferentially performed. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
(C) Performed in the course of the step (a), inspecting the foreign matter and / or defect on the semiconductor wafer, and deriving layout coordinates on the semiconductor wafer where the detected foreign matter and / or defect is located. And further comprising a process
The step (b) further includes
(B7) using the layout coordinates obtained in the step (c), and generating a second composite map in which the detection positions of the foreign matters and / or defects are displayed on the first composite map. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The step (b) further includes
(B8) performing a light emission analysis on the logic circuit and / or the memory circuit formed on the semiconductor wafer using an apparatus for observing light emission at an abnormal location;
(B9) deriving layout coordinates on the semiconductor wafer at the position where the emission is observed;
(B10) generating a third composite map in which the layout coordinates obtained in the step (b9) are used to superimpose and display the position where the emission is observed on the first composite map. A method for manufacturing a semiconductor device. (A) sequentially forming a plurality of layers for forming a semiconductor chip including a logic circuit and a memory circuit on a main surface of a semiconductor wafer;
(B) a step of inspecting the semiconductor wafer formed by the step (a);
(C) assembling the semiconductor chip determined to be non-defective in the step (b) on a package;
(D) a step of inspecting the semiconductor chip assembled in the step (c),
The step (d)
(D1) performing an electrical inspection on the logic circuit formed on the semiconductor chip;
(D2) selecting a candidate for a logic fault location in the logic circuit by inputting the result of the electrical inspection in the step (d1) to fault diagnosis software;
(D3) deriving layout coordinates on the semiconductor chip where the candidate of the logic fault location is located with reference to the layout information of the semiconductor chip;
(D4) performing an electrical test on the memory circuit formed on the semiconductor chip and storing the resulting faulty memory address;
(D5) referring to the layout information and deriving layout coordinates on the semiconductor chip where the memory cell corresponding to the failed memory address is located;
(D6) Using the layout coordinates obtained in the steps (d3) and (d5), using the semiconductor chip as a map space, the candidate position of the logic fault location and the memory cell corresponding to the fault memory address Generating a first composite map in which the positions are displayed in an overlapping manner, and a method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 7.
The method for manufacturing a semiconductor device, wherein the plurality of layers include a common layer used in common by the logic circuit and the memory circuit, and a dedicated layer used only by the logic circuit. The method of manufacturing a semiconductor device according to claim 7.
(E) Performed in the middle of the step (a), inspecting foreign matter and / or defects on the semiconductor wafer, and deriving layout coordinates on the semiconductor wafer where the detected foreign matter and / or defects are located. And further comprising a process
The step (d) further includes
(D7) Using the layout coordinates corresponding to the target semiconductor chip in the layout coordinates obtained in the step (e), the detection positions of the foreign matter and / or defects are displayed on the first composite map. The manufacturing method of the semiconductor device characterized by including the process of producing | generating the 2nd composite map displayed in piles. The method of manufacturing a semiconductor device according to claim 7.
The step (d) further includes
(D8) performing a light emission analysis on the logic circuit and / or the memory circuit formed on the semiconductor chip using a device for observing light emission at an abnormal location;
(D9) deriving layout coordinates on the semiconductor chip at the position where the emission is observed;
(D10) generating a third composite map in which the layout coordinates obtained in the step (d9) are used to superimpose and display the position where the emission is observed on the first composite map. A method for manufacturing a semiconductor device.

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